166 lines
4.4 KiB
NASM
166 lines
4.4 KiB
NASM
; ***************************************************************************
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; copyright : (C) 2025 by Martin Preuss
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; email : martin@libchipcard.de
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;
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; ***************************************************************************
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; * This file is part of the project "AqHome". *
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; * Please see toplevel file COPYING of that project for license details. *
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; ***************************************************************************
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.cseg
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; ---------------------------------------------------------------------------
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; @routine UART_HW_Uart1_Init @global
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;
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
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; @clobbers R16, R17, X
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UART_HW_Uart1_Init:
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rcall UART_HW_InterfaceInit
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; set baudrate
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.if clock == 8000000
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ldi r16, 25 ; (19.2Kb/s at 8MHz)
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ldi r17, 0
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.endif
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.if clock == 1000000
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ldi r16, 2 ; (19.2Kb/s at 1MHz)
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ldi r17, 0
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.endif
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sts UBRR1H, r17
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sts UBRR1L, r16
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; set character format
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ldi r16, (1<<USBS1)|(3<<UCSZ10)
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sts UCSR1C, r16
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_HW_Uart1_StartRx @global
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;
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; @clobbers none
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UART_HW_Uart1_StartRx:
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lds r16, UCSR1B
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sbr r16, (1<<RXCIE1) | (1<<RXEN1) ; enable RX complete interrupt, enable receive
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sts UCSR1B, r16
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_HW_Uart1_StopRx @global
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;
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; @clobbers none
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UART_HW_Uart1_StopRx:
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lds r16, UCSR1B
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cbr r16, (1<<RXCIE1 | (1<<RXEN1)) ; disable RX complete interrupt, disable receive
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sts UCSR1B, r16
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_HW_Uart1_StartTx @global
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;
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
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; @clobbers none
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UART_HW_Uart1_StartTx:
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lds r16, UCSR1B
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sbr r16, (1<<UDRIE1) | (1<<TXEN1) ; enable TX data register empty interrupt, enable transceive
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sts UCSR1B, r16
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_HW_Uart1_StopTx @global
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;
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
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; @clobbers none
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UART_HW_Uart1_StopTx:
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lds r16, UCSR1B
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cbr r16, (1<<UDRIE1) | (1<<TXEN1) ; disable TX data register empty interrupt, disable transceive
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sts UCSR1B, r16
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_HW_Uart1_RxCharIsr @global
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;
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
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; @clobbers R16 (R17, R18, X)
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UART_HW_Uart1_RxCharIsr:
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lds r16, UCSR1A ; check for errors
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andi r16, (1<<FE1) | (1<<DOR1) | (1<<UPE1)
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breq UART_HW_Uart1_RxCharIsr_recv ; no error, receive next char
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ldd r16, Y+UART_HW_IFACE_OFFS_STATUS ; set error status
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ori r16, UART_HW_STATUS_HWERR ; -> HWERR
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rjmp UART_HW_Uart1_RxCharIsr_setStatusAndEnd
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UART_HW_Uart1_RxCharIsr_recv:
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lds r16, UCSR1A
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sbrs r16, RXC1
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rjmp UART_HW_Uart1_RxCharIsr_end ; no data
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lds r16, UDR1
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rcall UART_HW_InterfaceWriteToReadBuffer ; (R17, R18, X)
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brcs UART_HW_Uart1_RxCharIsr_end
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ldd r16, Y+UART_HW_IFACE_OFFS_STATUS ; set overrun error
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ori r16, UART_HW_STATUS_OVERRUN ; -> OVERRUN
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UART_HW_Uart1_RxCharIsr_setStatusAndEnd:
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std Y+UART_HW_IFACE_OFFS_STATUS, r16
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UART_HW_Uart1_RxCharIsr_end:
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_HW_Uart1_TxCharIsr @global
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;
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
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; @clobbers R16, (R17, R18, X)
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UART_HW_Uart1_TxCharIsr:
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lds r16, UCSR1A
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sbrs r16,UDRE1
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rjmp UART_HW_Uart1_TxCharIsr_end ; not ready
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rcall UART_HW_InterfaceReadFromWriteBuffer ; (R17, R18, X)
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brcs UART_HW_Uart1_TxCharIsr_send ; got a byte, go send
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; disable further DRE1 interrupts
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lds r16, UCSR1B
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cbr r16, (1<<UDRIE1) ; disable TX data register empty interrupt
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sts UCSR1B, r16
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; set underrun status (TODO: maybe change this later)
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ldd r16, Y+UART_HW_IFACE_OFFS_STATUS ; set underrun error
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ori r16, UART_HW_STATUS_UNDERRUN
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std Y+UART_HW_IFACE_OFFS_STATUS, r16
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rjmp UART_HW_Uart1_TxCharIsr_end
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UART_HW_Uart1_TxCharIsr_send:
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sts UDR1, r16
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UART_HW_Uart1_TxCharIsr_end:
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ret
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; @end
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