; ***************************************************************************
; copyright   : (C) 2025 by Martin Preuss
; email       : martin@libchipcard.de
;
; ***************************************************************************
; * This file is part of the project "AqHome".                              *
; * Please see toplevel file COPYING of that project for license details.   *
; ***************************************************************************



.cseg



; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_Init @global
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
; @clobbers R16, R17, X

UART_HW_Uart1_Init:
  rcall UART_HW_InterfaceInit

  ; set baudrate
.if clock == 8000000
  ldi r16, 25 ; (19.2Kb/s at 8MHz)
  ldi r17, 0
.endif

.if clock == 1000000
  ldi r16, 2  ; (19.2Kb/s at 1MHz)
  ldi r17, 0  
.endif

  sts UBRR1H, r17
  sts UBRR1L, r16

  ; set character format 
  ldi r16, (1<<USBS1)|(3<<UCSZ10)
  sts UCSR1C, r16

  ret
; @end



; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_StartRx @global
;
; @clobbers none

UART_HW_Uart1_StartRx:
  lds r16, UCSR1B
  sbr r16, (1<<RXCIE1) | (1<<RXEN1)  ; enable RX complete interrupt, enable receive
  sts UCSR1B, r16
  ret
; @end



; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_StopRx @global
;
; @clobbers none

UART_HW_Uart1_StopRx:
  lds r16, UCSR1B
  cbr r16, (1<<RXCIE1 | (1<<RXEN1))   ; disable RX complete interrupt, disable receive
  sts UCSR1B, r16
  ret
; @end



; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_StartTx @global
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
; @clobbers none

UART_HW_Uart1_StartTx:
  lds r16, UCSR1B
  sbr r16, (1<<UDRIE1) | (1<<TXEN1)         ; enable TX data register empty interrupt, enable transceive
  sts UCSR1B, r16
  ret
; @end



; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_StopTx @global
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
; @clobbers none

UART_HW_Uart1_StopTx:
  lds r16, UCSR1B
  cbr r16, (1<<UDRIE1) | (1<<TXEN1)  ; disable TX data register empty interrupt, disable transceive
  sts UCSR1B, r16
  ret
; @end



; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_RxCharIsr @global
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
; @clobbers R16 (R17, R18, X)

UART_HW_Uart1_RxCharIsr:
  lds r16, UCSR1A                              ; check for errors
  andi r16, (1<<FE1) | (1<<DOR1) | (1<<UPE1)
  breq UART_HW_Uart1_RxCharIsr_recv            ; no error, receive next char
  ldd r16, Y+UART_HW_IFACE_OFFS_STATUS         ; set error status
  ori r16, UART_HW_STATUS_HWERR                ; -> HWERR
  rjmp UART_HW_Uart1_RxCharIsr_setStatusAndEnd
UART_HW_Uart1_RxCharIsr_recv:
  lds r16, UCSR1A
  sbrs r16, RXC1
    rjmp UART_HW_Uart1_RxCharIsr_end           ; no data
  lds r16, UDR1
  rcall UART_HW_InterfaceWriteToReadBuffer     ; (R17, R18, X)
  brcs UART_HW_Uart1_RxCharIsr_end
  ldd r16, Y+UART_HW_IFACE_OFFS_STATUS         ; set overrun error
  ori r16, UART_HW_STATUS_OVERRUN              ; -> OVERRUN
UART_HW_Uart1_RxCharIsr_setStatusAndEnd:
  std Y+UART_HW_IFACE_OFFS_STATUS, r16
UART_HW_Uart1_RxCharIsr_end:
  ret
; @end



; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_TxCharIsr @global
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
; @clobbers R16, (R17, R18, X)

UART_HW_Uart1_TxCharIsr:
  lds r16, UCSR1A
  sbrs r16,UDRE1
    rjmp UART_HW_Uart1_TxCharIsr_end           ; not ready
  rcall UART_HW_InterfaceReadFromWriteBuffer   ; (R17, R18, X)
  brcs UART_HW_Uart1_TxCharIsr_send            ; got a byte, go send

  ; disable further DRE1 interrupts
  lds r16, UCSR1B
  cbr r16, (1<<UDRIE1)                         ; disable TX data register empty interrupt
  sts UCSR1B, r16
  ; set underrun status (TODO: maybe change this later)
  ldd r16, Y+UART_HW_IFACE_OFFS_STATUS         ; set underrun error
  ori r16, UART_HW_STATUS_UNDERRUN
  std Y+UART_HW_IFACE_OFFS_STATUS, r16
  rjmp UART_HW_Uart1_TxCharIsr_end
UART_HW_Uart1_TxCharIsr_send:
  sts UDR1, r16
UART_HW_Uart1_TxCharIsr_end:
  ret
; @end