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receiving works again.

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This commit is contained in:
Martin Preuss
2025-05-31 15:36:52 +02:00
parent 061119819f
commit be74442e7f
2 changed files with 31 additions and 19 deletions
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46
avr/modules/uart_bitbang2/bytelevel.asm
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@@ -134,28 +134,40 @@ uartBitbang_SendByte_loopEnd:
; ;
; @return CFLAG set if okay, clear otherwise ; @return CFLAG set if okay, clear otherwise
; @return R16 byte received ; @return R16 byte received
; @clobbers R16, R20, R21, R22 (R17) ; @clobbers R16, R17, R20, R21, R22
uartBitbang_ReceiveByte: uartBitbang_ReceiveByte:
cbi COM_DATA_DDR, COM_DATA_PIN ; set DATA port as input cbi COM_DATA_DDR, COM_DATA_PIN ; set DATA port as input
cbi COM_DATA_OUTPUT, COM_DATA_PIN ; disable internal pullup for RXD cbi COM_DATA_OUTPUT, COM_DATA_PIN ; disable internal pullup for RXD
ldi r21, 8 ; bits left ldi r21, 8 ; bits left
clr r20 ; byte currently receiving clr r20 ; byte currently receiving
; wait for startbit ; wait for startbit
rcall uartBitbang_WaitForDataLow ; (R17, R22) ldi r16, 10
brcc uartBitbang_ReceiveByte_error uartBitbang_ReceiveByte_loopStartBit1:
Utils_WaitNanoSecs COM_HALFBIT_LENGTH, 10, r22 ; goto middle of startbit to maximize sync stability ldi r17, 100 ; wait for 100us
uartBitbang_ReceiveByte_loopStartBit2:
sbis COM_DATA_INPUT, COM_DATA_PIN
rjmp uartBitbang_ReceiveByte_gotStartBit
Utils_WaitNanoSecs 1000, 0, r22 ; wait for 1us
dec r17
brne uartBitbang_ReceiveByte_loopStartBit2
dec r16
brne uartBitbang_ReceiveByte_loopStartBit1
rjmp uartBitbang_ReceiveByte_error
uartBitbang_ReceiveByte_gotStartBit:
Utils_WaitNanoSecs COM_HALFBIT_LENGTH, 0, r22 ; goto middle of startbit to maximize sync stability (4)
uartBitbang_ReceiveByte_loop: uartBitbang_ReceiveByte_loop:
Utils_WaitNanoSecs COM_BIT_LENGTH, 8, r22 ; 8 cycles used in the complete loop between waits Utils_WaitNanoSecs COM_BIT_LENGTH, 8, r22 ; 8 cycles used in the complete loop between waits
sec ; +1 sec ; +1
sbic COM_DATA_INPUT, COM_DATA_PIN ; LOW: +2, HIGH: +1 sbic COM_DATA_INPUT, COM_DATA_PIN ; LOW: +2, HIGH: +1
rjmp uartBitbang_ReceiveByte_shiftIn ; HIGH: +2, rjmp, use set CFLAG rjmp uartBitbang_ReceiveByte_shiftIn ; HIGH: +2, rjmp, use set CFLAG
clc ; LOW: +1 clc ; LOW: +1
uartBitbang_ReceiveByte_shiftIn: uartBitbang_ReceiveByte_shiftIn:
ror r20 ; +1 ror r20 ; +1
dec r21 ; +1 dec r21 ; +1
brne uartBitbang_ReceiveByte_loop ; +2, sum per loop: 8 cycles brne uartBitbang_ReceiveByte_loop ; +2, sum per loop: 8 cycles
rcall uartBitbang_WaitForDataHigh ; wait for start of stopbit rcall uartBitbang_WaitForDataHigh ; wait for start of stopbit
brcc uartBitbang_ReceiveByte_error brcc uartBitbang_ReceiveByte_error
mov r16, r20 mov r16, r20
sec sec

4
avr/modules/uart_bitbang2/msglevel.asm
View File

@@ -78,7 +78,7 @@ uartBitbang_RawReceiveMsg:
breq uartBitbang_RawReceiveMsg_forMe breq uartBitbang_RawReceiveMsg_forMe
cpi r16, 0xff cpi r16, 0xff
breq uartBitbang_RawReceiveMsg_forMe breq uartBitbang_RawReceiveMsg_forMe
clr r16 clr r16 ; not for me
rjmp uartBitbang_RawReceiveMsg_clcRet rjmp uartBitbang_RawReceiveMsg_clcRet
uartBitbang_RawReceiveMsg_forMe: uartBitbang_RawReceiveMsg_forMe:
subi r19, 1 subi r19, 1
@@ -87,10 +87,10 @@ uartBitbang_RawReceiveMsg_forMe:
; read size of msg payload (e.g. number of msg bytes following minus CRC byte) ; read size of msg payload (e.g. number of msg bytes following minus CRC byte)
rcall uartBitbang_ReceiveByte ; read byte (R16, R17, R20, R21, R22) rcall uartBitbang_ReceiveByte ; read byte (R16, R17, R20, R21, R22)
brcc uartBitbang_RawReceiveMsg_eIo brcc uartBitbang_RawReceiveMsg_eIo
inc r16 ; account for crc byte
subi r19, 1 subi r19, 1
brcs uartBitbang_RawReceiveMsg_eBadSize brcs uartBitbang_RawReceiveMsg_eBadSize
st X+, r16 ; store msg payload size st X+, r16 ; store msg payload size
inc r16 ; account for crc byte
sub r19, r16 ; check msg size against remaining buffer size sub r19, r16 ; check msg size against remaining buffer size
brcs uartBitbang_RawReceiveMsg_eBadSize brcs uartBitbang_RawReceiveMsg_eBadSize
mov r19, r16 mov r19, r16