avr: added modules spi_sw, 23LC512, 25LC256
This commit is contained in:
Martin Preuss
@@ -198,6 +198,19 @@ MODULE_END_COM2W:
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.include "modules/spi_hw/main.asm"
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#endif
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#ifdef MODULES_SPI_SW
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.include "modules/spi_sw/main.asm"
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#endif
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#ifdef MODULES_RAM_23LC512
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.include "modules/ram/23LC512/main.asm"
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#endif
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#ifdef MODULES_EE_25LC256
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.include "modules/eeprom/25LC256/main.asm"
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#endif
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#ifdef MODULES_DS18B20
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.include "modules/ds18b20/main2.asm"
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#ifdef MODULES_NETWORK
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@@ -133,6 +133,18 @@ modulesInit:
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bigcall SPIHW_Init
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#endif
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#ifdef MODULES_SPI_SW
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bigcall SPISW_Init
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#endif
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#ifdef MODULES_RAM_23LC512
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bigcall RAM_23LC512_Init
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#endif
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#ifdef MODULES_EE_25LC256
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bigcall EE_25LC256_Init
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#endif
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#ifdef MODULES_LCD
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bigcall LCD_Init
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#endif
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@@ -4,38 +4,47 @@
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<subdirs>
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basetimer
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beeper_simple
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bmp280
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bootloader
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brightness
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ccs811
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clock
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cny70
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com2w
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com2w_router
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ds18b20
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eeprom
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f_keepup
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f_stabilize
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flash
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heap
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lcd
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lcd2
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led
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motion
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network
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owimaster
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ram
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reed
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rtc
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sgp30
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sgp40
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si7021
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sk6812
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spi_hw
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spi_sw
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tcrt1000
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timer
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twimaster
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network
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uart_bitbang
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uart_bitbang2
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uart_irq
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uart_fd
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uart_hw
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bootloader
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f_keepup
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uart_hw2
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uart_irq
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valsched
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xram
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heap
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brightness
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rtc
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</subdirs>
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</gwbuild>
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10
avr/modules/eeprom/0BUILD
Normal file
10
avr/modules/eeprom/0BUILD
Normal file
@@ -0,0 +1,10 @@
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<?xml?>
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<gwbuild>
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<subdirs>
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25LC256
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</subdirs>
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</gwbuild>
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10
avr/modules/eeprom/25LC256/0BUILD
Normal file
10
avr/modules/eeprom/25LC256/0BUILD
Normal file
@@ -0,0 +1,10 @@
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<?xml?>
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<gwbuild>
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<extradist>
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main.asm
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</extradist>
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</gwbuild>
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224
avr/modules/eeprom/25LC256/main.asm
Normal file
224
avr/modules/eeprom/25LC256/main.asm
Normal file
@@ -0,0 +1,224 @@
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; ***************************************************************************
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; copyright : (C) 2026 by Martin Preuss
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; email : martin@libchipcard.de
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;
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; ***************************************************************************
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; * This file is part of the project "AqHome". *
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; * Please see toplevel file COPYING of that project for license details. *
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; ***************************************************************************
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#ifndef AQH_AVR_MODULES_EE_25LC256_MAIN_ASM
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#define AQH_AVR_MODULES_EE_25LC256_MAIN_ASM
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; ***************************************************************************
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; defs
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.equ EE_25LC256_SIZE = 32768
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.equ EE_25LC256_CMD_READ = 0x03
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.equ EE_25LC256_CMD_WRITE = 0x02
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.equ EE_25LC256_CMD_WRDI = 0x04
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.equ EE_25LC256_CMD_WREN = 0x06
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.equ EE_25LC256_CMD_RDSR = 0x05
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.equ EE_25LC256_CMD_WRSR = 0x01
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; ***************************************************************************
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; data
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.dseg
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; ***************************************************************************
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; code
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.cseg
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; ---------------------------------------------------------------------------
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; @routine EE_25LC256_Init @global
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;
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; @param X destination address
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EE_25LC256_Init:
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sbi EEPROMCS_DDR, EEPROMCS_PIN ; EEPROMCS: output
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sbi EEPROMCS_OUTPUT, EEPROMCS_PIN ; EEPROMCS high
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sec
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine EE_25LC256_StartWriting @global
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;
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; @param X destination address
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; @clobbers r16-r19, r23
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EE_25LC256_StartWriting:
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ldi r16, EE_25LC256_CMD_WRITE
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rjmp ee25LC256StartTransfer ; (r16-r19, r23)
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; @end
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; ---------------------------------------------------------------------------
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; @routine EE_25LC256_StartReading @global
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;
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; @param X source address
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; @clobbers r16-r19, r23
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EE_25LC256_StartReading:
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ldi r16, EE_25LC256_CMD_READ
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rjmp ee25LC256StartTransfer ; (r16-r19, r23)
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; @end
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; ---------------------------------------------------------------------------
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; @routine EE_25LC256_EndTransfer @global
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;
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; @clobbers none
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EE_25LC256_EndTransfer:
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sbi EEPROMCS_OUTPUT, EEPROMCS_PIN ; CS high
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bigcall SPISW_MasterStop ; (none)
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine EE_25LC256_ReadBytes @global
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;
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; @param X source address
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; @param Y destination address
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; @param R25:r24 number of bytes to read
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; @clobbers r16-r19, r23-r25, Y
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EE_25LC256_ReadBytes:
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rcall EE_25LC256_StartReading ; (r16-r19, r23)
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EE_25LC256_ReadBytes_loop:
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ldi r16, 0xff
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bigcall SPISW_MasterExchangeByteMode0 ; (r17, r18, r19, r23)
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st Y+, r16
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sbiw r25:r24, 1
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brne EE_25LC256_ReadBytes_loop
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rcall EE_25LC256_EndTransfer
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine EE_25LC256_WriteBytes @global
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;
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; @param X destination address
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; @param Y source address
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; @param R25:r24 number of bytes to write
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; @clobbers r16-r19, r23-r25, Y
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EE_25LC256_WriteBytes:
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rcall EE_25LC256_WriteEnable ; (r16-r19, r23)
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rcall EE_25LC256_StartWriting ; (r16-r19, r23)
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EE_25LC256_WriteBytes_loop:
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ld r16, Y+
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bigcall SPISW_MasterExchangeByteMode0 ; (r17, r18, r19, r23)
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sbiw r25:r24, 1
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brne EE_25LC256_WriteBytes_loop
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rcall EE_25LC256_EndTransfer ; (none)
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine EE_25LC256_ReadStatusRegister
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;
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; @return r16 mode register
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; @clobbers r17-r19, r23
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EE_25LC256_ReadStatusRegister:
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ldi r16, EE_25LC256_CMD_RDSR
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rcall ee25LC256StartCommand
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clr r16
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bigcall SPISW_MasterExchangeByteMode0 ; (r17, r18, r19, r23)
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push r16
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rcall EE_25LC256_EndTransfer
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pop r16
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine EE_25LC256_WriteEnable
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;
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; @clobbers r16-r19, r23
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EE_25LC256_WriteEnable:
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ldi r16, EE_25LC256_CMD_WREN
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rcall ee25LC256StartCommand ; (r16-r19, r23)
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rcall EE_25LC256_EndTransfer ; (none)
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine ee25LC256StartTransfer
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;
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; @param r16 command
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; @param X address
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; @clobbers r16-r19, r23
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ee25LC256StartTransfer:
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rcall ee25LC256StartCommand
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; send address
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mov r16, xh
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bigcall SPISW_MasterExchangeByteMode0 ; (r17, r18, r19, r23)
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mov r16, xl
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bigcall SPISW_MasterExchangeByteMode0 ; (r17, r18, r19, r23)
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine ee25LC256StartCommand
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;
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; @param r16 command
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; @clobbers r16-r19, r23
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ee25LC256StartCommand:
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push r16
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bigcall SPISW_MasterStart
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pop r16
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nop
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sbi EEPROMCS_DDR, EEPROMCS_PIN ; CS: output
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cbi EEPROMCS_OUTPUT, EEPROMCS_PIN ; CS low
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nop
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; send command
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bigcall SPISW_MasterExchangeByteMode0 ; (r17, r18, r19, r23)
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ret
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; @end
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#endif
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10
avr/modules/ram/0BUILD
Normal file
10
avr/modules/ram/0BUILD
Normal file
@@ -0,0 +1,10 @@
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<?xml?>
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<gwbuild>
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<subdirs>
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23LC512
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</subdirs>
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</gwbuild>
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9
avr/modules/ram/23LC512/0BUILD
Normal file
9
avr/modules/ram/23LC512/0BUILD
Normal file
@@ -0,0 +1,9 @@
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<?xml?>
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<gwbuild>
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<extradist>
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main.asm
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</extradist>
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</gwbuild>
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286
avr/modules/ram/23LC512/main.asm
Normal file
286
avr/modules/ram/23LC512/main.asm
Normal file
@@ -0,0 +1,286 @@
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; ***************************************************************************
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; copyright : (C) 2026 by Martin Preuss
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; email : martin@libchipcard.de
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;
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; ***************************************************************************
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; * This file is part of the project "AqHome". *
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; * Please see toplevel file COPYING of that project for license details. *
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; ***************************************************************************
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#ifndef AQH_AVR_MODULES_RAM_23LC512_MAIN_ASM
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#define AQH_AVR_MODULES_RAM_23LC512_MAIN_ASM
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; ***************************************************************************
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; defs
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.equ RAM_23LC512_LASTADDR = 65535
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.equ RAM_23LC512_PATTERNSIZE = 0
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.equ RAM_23LC512_CMD_READ = 0x03
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.equ RAM_23LC512_CMD_WRITE = 0x02
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.equ RAM_23LC512_CMD_RDMR = 0x05
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.equ RAM_23LC512_CMD_WRMR = 0x01
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; ***************************************************************************
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; data
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.dseg
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; ***************************************************************************
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; code
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.cseg
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; ---------------------------------------------------------------------------
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; @routine RAM_23LC512_Init @global
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;
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; @param X destination address
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RAM_23LC512_Init:
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sbi RAMCS_DDR, RAMCS_PIN ; RAMCS: output
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sbi RAMCS_OUTPUT, RAMCS_PIN ; RAMCS high
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sec
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine RAM_23LC512_StartWriting @global
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;
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; @param X destination address
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; @clobbers r16-r19, r23
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RAM_23LC512_StartWriting:
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ldi r16, RAM_23LC512_CMD_WRITE
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rjmp ram23LC512StartTransfer ; (r16-r19, r23)
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; @end
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; ---------------------------------------------------------------------------
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; @routine RAM_23LC512_StartReading @global
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;
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; @param X source address
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; @clobbers r16-r19, r23
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RAM_23LC512_StartReading:
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ldi r16, RAM_23LC512_CMD_READ
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rjmp ram23LC512StartTransfer ; (r16-r19, r23)
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; @end
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; ---------------------------------------------------------------------------
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; @routine RAM_23LC512_EndTransfer @global
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;
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RAM_23LC512_EndTransfer:
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sbi RAMCS_OUTPUT, RAMCS_PIN ; CS high
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bigcall SPISW_MasterStop
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine RAM_23LC512_ReadBytes @global
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;
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; @param X source address
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; @param Y destination address
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; @param R25:r24 number of bytes to read
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; @clobbers r16-r19, r23-r25
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RAM_23LC512_ReadBytes:
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rcall RAM_23LC512_StartReading ; (r16-r19, r23)
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RAM_23LC512_ReadBytes_loop:
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ldi r16, 0xff
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bigcall SPISW_MasterExchangeByteMode0 ; (r17, r18, r19, r23)
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st Y+, r16
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sbiw r25:r24, 1
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brne RAM_23LC512_ReadBytes_loop
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rcall RAM_23LC512_EndTransfer
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine RAM_23LC512_WriteBytes @global
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;
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; @param X destination address
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; @param Y source address
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; @param R25:r24 number of bytes to write
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; @clobbers r16-r19, r23-r25
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RAM_23LC512_WriteBytes:
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rcall RAM_23LC512_StartWriting ; (r16-r19, r23)
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RAM_23LC512_WriteBytes_loop:
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ld r16, Y+
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bigcall SPISW_MasterExchangeByteMode0 ; (r17, r18, r19, r23)
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sbiw r25:r24, 1
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brne RAM_23LC512_WriteBytes_loop
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rcall RAM_23LC512_EndTransfer
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine RAM_23LC512_Fill @global
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;
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; @param X destination address
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; @param R16 byte to write
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; @param R25:r24 number of bytes to write
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; @clobbers r16-r19, r22-r25
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RAM_23LC512_Fill:
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mov r22, r16
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rcall RAM_23LC512_StartWriting ; (r16-r19, r23)
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RAM_23LC512_Fill_loop:
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mov r16, r22
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bigcall SPISW_MasterExchangeByteMode0 ; (r17, r18, r19, r23)
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sbiw r25:r24, 1
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brne RAM_23LC512_Fill_loop
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rcall RAM_23LC512_EndTransfer
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine RAM_23LC512_WritePattern @global
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;
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; @clobbers r16-r19, r23-r25
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RAM_23LC512_WritePattern:
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clr xl
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clr xh
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rcall RAM_23LC512_StartWriting ; (r16-r19, r23)
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ldi r24, LOW(RAM_23LC512_PATTERNSIZE)
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ldi r25, HIGH(RAM_23LC512_PATTERNSIZE)
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clr xl
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clr xh
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RAM_23LC512_WritePattern_loop:
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mov r16, xh
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bigcall SPISW_MasterExchangeByteMode0 ; (r17, r18, r19, r23)
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adiw xh:xl, 1
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sbiw r25:r24, 1
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brne RAM_23LC512_WritePattern_loop
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rcall RAM_23LC512_EndTransfer
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ret
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; @end
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||||
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||||
; ---------------------------------------------------------------------------
|
||||
; @routine RAM_23LC512_ReadPattern @global
|
||||
;
|
||||
; @clobbers r16-r19, r23-r25
|
||||
|
||||
RAM_23LC512_ReadPattern:
|
||||
clr xl
|
||||
clr xh
|
||||
rcall RAM_23LC512_StartReading ; (r16-r19, r23)
|
||||
ldi r24, LOW(RAM_23LC512_PATTERNSIZE)
|
||||
ldi r25, HIGH(RAM_23LC512_PATTERNSIZE)
|
||||
clr xl
|
||||
clr xh
|
||||
RAM_23LC512_ReadPattern_loop:
|
||||
ldi r16, 0xff
|
||||
bigcall SPISW_MasterExchangeByteMode0 ; (r17, r18, r19, r23)
|
||||
cp r16, xh
|
||||
clc
|
||||
brne RAM_23LC512_ReadPattern_ret
|
||||
adiw xh:xl, 1
|
||||
sbiw r25:r24, 1
|
||||
brne RAM_23LC512_ReadPattern_loop
|
||||
rcall RAM_23LC512_EndTransfer
|
||||
sec
|
||||
RAM_23LC512_ReadPattern_ret:
|
||||
ret
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
; ---------------------------------------------------------------------------
|
||||
; @routine RAM_23LC512_ReadModeRegister
|
||||
;
|
||||
; @return r16 mode register
|
||||
; @clobbers r17-r19, r23
|
||||
|
||||
RAM_23LC512_ReadModeRegister:
|
||||
ldi r16, RAM_23LC512_CMD_RDMR
|
||||
rcall ram23LC512StartCommand
|
||||
clr r16
|
||||
bigcall SPISW_MasterExchangeByteMode0 ; (r17, r18, r19, r23)
|
||||
push r16
|
||||
rcall RAM_23LC512_EndTransfer
|
||||
pop r16
|
||||
ret
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
; ---------------------------------------------------------------------------
|
||||
; @routine ram23LC512StartTransfer
|
||||
;
|
||||
; @param r16 command
|
||||
; @param X address
|
||||
; @clobbers r16-r19, r23
|
||||
|
||||
ram23LC512StartTransfer:
|
||||
rcall ram23LC512StartCommand
|
||||
|
||||
; send address
|
||||
mov r16, xh
|
||||
bigcall SPISW_MasterExchangeByteMode0 ; (r17, r18, r19, r23)
|
||||
mov r16, xl
|
||||
bigcall SPISW_MasterExchangeByteMode0 ; (r17, r18, r19, r23)
|
||||
|
||||
ret
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
; ---------------------------------------------------------------------------
|
||||
; @routine ram23LC512StartCommand
|
||||
;
|
||||
; @param r16 command
|
||||
; @clobbers r16-r19, r23
|
||||
|
||||
ram23LC512StartCommand:
|
||||
push r16
|
||||
bigcall SPISW_MasterStart
|
||||
pop r16
|
||||
nop
|
||||
sbi RAMCS_DDR, RAMCS_PIN ; CS: output
|
||||
cbi RAMCS_OUTPUT, RAMCS_PIN ; CS low
|
||||
nop
|
||||
|
||||
; send command
|
||||
bigcall SPISW_MasterExchangeByteMode0 ; (r17, r18, r19, r23)
|
||||
|
||||
ret
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
11
avr/modules/spi_sw/0BUILD
Normal file
11
avr/modules/spi_sw/0BUILD
Normal file
@@ -0,0 +1,11 @@
|
||||
<?xml?>
|
||||
|
||||
<gwbuild>
|
||||
|
||||
<extradist>
|
||||
main.asm
|
||||
</extradist>
|
||||
|
||||
</gwbuild>
|
||||
|
||||
|
||||
131
avr/modules/spi_sw/main.asm
Normal file
131
avr/modules/spi_sw/main.asm
Normal file
@@ -0,0 +1,131 @@
|
||||
; ***************************************************************************
|
||||
; copyright : (C) 2025 by Martin Preuss
|
||||
; email : martin@libchipcard.de
|
||||
;
|
||||
; ***************************************************************************
|
||||
; * This file is part of the project "AqHome". *
|
||||
; * Please see toplevel file COPYING of that project for license details. *
|
||||
; ***************************************************************************
|
||||
|
||||
|
||||
; ***************************************************************************
|
||||
; macros
|
||||
|
||||
; @param @0 register to use
|
||||
|
||||
|
||||
|
||||
; ***************************************************************************
|
||||
; defines
|
||||
|
||||
|
||||
|
||||
; ***************************************************************************
|
||||
; data
|
||||
|
||||
.dseg
|
||||
|
||||
|
||||
|
||||
; ***************************************************************************
|
||||
; code
|
||||
|
||||
.cseg
|
||||
|
||||
|
||||
|
||||
; ---------------------------------------------------------------------------
|
||||
; @routine SPISW_Init @global
|
||||
;
|
||||
|
||||
SPISW_Init:
|
||||
sec
|
||||
ret
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
; ---------------------------------------------------------------------------
|
||||
; @routine SPISW_MasterStart @global
|
||||
;
|
||||
; Start SPI software master.
|
||||
; @clobbers none
|
||||
|
||||
SPISW_MasterStart:
|
||||
; setup pins
|
||||
sbi SPISW_MOSI_DDR, SPISW_MOSI_PIN ; MOSI: output
|
||||
cbi SPISW_MISO_DDR, SPISW_MISO_PIN ; MISO: input
|
||||
sbi SPISW_SCK_DDR, SPISW_SCK_PIN ; SCK: output
|
||||
cbi SPISW_SCK_OUTPUT, SPISW_SCK_PIN ; clock low
|
||||
ret
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
; ---------------------------------------------------------------------------
|
||||
; @routine SPISW_MasterStop @global
|
||||
;
|
||||
; Stop SPI software master. Put all ports to high-Z mode.
|
||||
; @clobbers none
|
||||
|
||||
SPISW_MasterStop:
|
||||
; setup pins
|
||||
cbi SPISW_MOSI_DDR, SPISW_MOSI_PIN ; MOSI: input
|
||||
cbi SPISW_MOSI_OUTPUT, SPISW_MOSI_PIN ; disable pullup
|
||||
cbi SPISW_MISO_DDR, SPISW_MISO_PIN ; MISO: input
|
||||
cbi SPISW_MISO_OUTPUT, SPISW_MISO_PIN ; disable pullup
|
||||
cbi SPISW_SCK_DDR, SPISW_SCK_PIN ; SCK: input
|
||||
cbi SPISW_SCK_OUTPUT, SPISW_SCK_PIN ; disable pullup
|
||||
ret
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
; ---------------------------------------------------------------------------
|
||||
; @routine SPIHW_MasterExchangeByteMode0 @global
|
||||
;
|
||||
; @param r16 byte to send
|
||||
; @return r16 byte received
|
||||
; @clobbers r17, r18, r19, r23
|
||||
|
||||
SPISW_MasterExchangeByteMode0:
|
||||
push r15
|
||||
inr r15, SREG
|
||||
cli
|
||||
|
||||
ldi r23, 8
|
||||
SPISW_MasterExchangeByteMode0_loop:
|
||||
; clock low
|
||||
cbi SPISW_SCK_OUTPUT, SPISW_SCK_PIN
|
||||
nop
|
||||
|
||||
; write MOSI
|
||||
sbrs r16, 7
|
||||
cbi SPISW_MOSI_OUTPUT, SPISW_MOSI_PIN
|
||||
sbrc r16, 7
|
||||
sbi SPISW_MOSI_OUTPUT, SPISW_MOSI_PIN
|
||||
nop
|
||||
lsl r16
|
||||
|
||||
; clock high
|
||||
sbi SPISW_SCK_OUTPUT, SPISW_SCK_PIN
|
||||
nop
|
||||
|
||||
; read MISO
|
||||
lsl r17
|
||||
sbic SPISW_MISO_INPUT, SPISW_MISO_PIN
|
||||
inc r17
|
||||
dec r23
|
||||
brne SPISW_MasterExchangeByteMode0_loop
|
||||
mov r16, r17
|
||||
|
||||
outr SREG, r15
|
||||
pop r15
|
||||
ret
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user