added uart_bitbang2.
This commit is contained in:
Martin Preuss
367
avr/modules/uart_bitbang2/lowlevel.asm
Normal file
367
avr/modules/uart_bitbang2/lowlevel.asm
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; ***************************************************************************
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; copyright : (C) 2025 by Martin Preuss
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; email : martin@libchipcard.de
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;
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; ***************************************************************************
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; * This file is part of the project "AqHome". *
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; * Please see toplevel file COPYING of that project for license details. *
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; ***************************************************************************
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; ***************************************************************************
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; code
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; ---------------------------------------------------------------------------
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; @macro UART_BB_M_WAIT_FOR_PIN_LOW IN_REG_DATA, IN_PINNUM
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; 0 1
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; Wait for a pin to become low
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; @param %0 DATA register for input pin (e.g. PINB)
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; @param %1 pin number for input (e.g. PORTB1)
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; @return CFLAG set if okay, clear otherwise
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; @clobbers R17, R22
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.macro UART_BB_M_WAIT_FOR_PIN_LOW
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ldi r17, 200
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l_loop:
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sbis @0, @1
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rjmp l_reached
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Utils_WaitNanoSecs 5000, 0, r22 ; wait for 5us
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dec r17
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brne l_loop
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clc
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rjmp l_end
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l_reached:
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sec
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l_end:
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.endmacro
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; @end
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; ---------------------------------------------------------------------------
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; @macro UART_BB_M_WAIT_FOR_PIN_HIGH IN_REG_DATA, IN_PINNUM
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; 0 1
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; Wait for a pin to become high (up to 1ms)
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; @param %0 DATA register for input pin (e.g. PINB)
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; @param %1 pin number for input (e.g. PORTB1)
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; @return CFLAG set if okay, clear otherwise
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; @clobbers R17, R22
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.macro UART_BB_M_WAIT_FOR_PIN_HIGH
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ldi r17, 200
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l_loop:
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sbic @0, @1
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rjmp l_reached
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Utils_WaitNanoSecs 5000, 0, r22 ; wait for 5us
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dec r17
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brne l_loop
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clc
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rjmp l_end
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l_reached:
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sec
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l_end:
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.endmacro
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; @end
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; ---------------------------------------------------------------------------
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; @routine uartBitbang_SendByte
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;
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; Send a byte.
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; We only set the data pin to low at the beginning for the startbit. After that
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; we only change the pin direction (e.g. input vs output):
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; - for 0 bit: set DDR to output, forcing the data line low
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; - for 1 bit: set DDR to input, letting the external pullup R pull the data line to HIGH
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; since the output pin is still set to 0 the internal pullup is disabled
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; Expects interrupts to be disabled.
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;
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; @param R16 byte to send
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; @return CFLAG set if okay, clear otherwise
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; @clobbers R16, R21, R22
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uartBitbang_SendByte:
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cbi COM_DATA_DDR, COM_DATA_PIN ; set DATA port as input
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cbi COM_DATA_OUTPUT, COM_DATA_PIN ; disable internal pullup for DATA
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ldi r21, 8 ; +1 bits left
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; send startbit
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sbi COM_DATA_DDR, COM_DATA_PIN ; +2 set DATA as output
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cbi COM_DATA_OUTPUT, COM_DATA_PIN ; +2 set DATA low
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Utils_WaitNanoSecs COM_BIT_LENGTH, 1, r22 ; wait for one bit duration
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; send data bits
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uartBitbang_SendByte_loop: ; 9 for low bit
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lsr r16 ; 1+ bit to send -> CARRY
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brcs uartBitbang_SendByte_setHigh ; HI: +2, LO: +1
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uartBitbang_SendByte_setLow:
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sbi COM_DATA_DDR, COM_DATA_PIN ; +2 set DATA as output
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cbi COM_DATA_OUTPUT, COM_DATA_PIN ; +2 set DATA low
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Utils_WaitNanoSecs COM_BIT_LENGTH, 11, r22
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rjmp uartBitbang_SendByte_loopEnd ; +2
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uartBitbang_SendByte_setHigh:
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cbi COM_DATA_DDR, COM_DATA_PIN ; +2 set DATA as input, pullup R makes it ONE
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nop ; +1 (to make pin change available)
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Utils_WaitNanoSecs COM_HALFBIT_LENGTH, 0, r22 ; wait for half a bit length for line to safely settle
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sbis COM_DATA_INPUT, COM_DATA_PIN ; +1 if no skip, +2 if skipped
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rjmp uartBitbang_SendByte_error ; +2 if error (collision: we wanted line to be high but it is low)
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Utils_WaitNanoSecs COM_HALFBIT_LENGTH, 11, r22
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uartBitbang_SendByte_loopEnd:
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dec r21 ; +1
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brne uartBitbang_SendByte_loop ; +2, sum per loop: 10 cycles
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; send stopbit
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cbi COM_DATA_DDR, COM_DATA_PIN ; +2 set DATA as input, pullup R makes it ONE
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Utils_WaitNanoSecs COM_BIT_LENGTH, 0, r22 ; wait for one bit length
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sec
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ret
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uartBitbang_SendByte_error:
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clc
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine uartBitbangReceiveByte
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;
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; Read a byte.
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; Expects interrupts to be disabled.
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;
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; @return CFLAG set if okay, clear otherwise
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; @return R16 byte received
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; @clobbers R16, R20, R21, R22 (R17)
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uartBitbang_ReceiveByte:
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cbi COM_DATA_DDR, COM_DATA_PIN ; set DATA port as input
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cbi COM_DATA_OUTPUT, COM_DATA_PIN ; disable internal pullup for RXD
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ldi r21, 8 ; bits left
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clr r20 ; byte currently receiving
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; wait for startbit
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rcall uartBitbang_WaitForDataLow ; (R17, R22)
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brcc uartBitbang_ReceiveByte_error
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Utils_WaitNanoSecs COM_HALFBIT_LENGTH, 10, r22 ; goto middle of startbit to maximize sync stability
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uartBitbang_ReceiveByte_loop:
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Utils_WaitNanoSecs COM_BIT_LENGTH, 8, r22 ; 8 cycles used in the complete loop between waits
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sec ; +1
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sbic COM_DATA_INPUT, COM_DATA_PIN ; LOW: +2, HIGH: +1
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rjmp uartBitbang_ReceiveByte_shiftIn ; HIGH: +2, rjmp, use set CFLAG
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clc ; LOW: +1
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uartBitbang_ReceiveByte_shiftIn:
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ror r20 ; +1
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dec r21 ; +1
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brne uartBitbang_ReceiveByte_loop ; +2, sum per loop: 8 cycles
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rcall uartBitbang_WaitForDataHigh ; wait for start of stopbit
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brcc uartBitbang_ReceiveByte_error
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mov r16, r20
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sec
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ret
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uartBitbang_ReceiveByte_error:
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clc
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine uartBitbang_WaitForDataLow
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;
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; Wait up to 1ms for data pin to become low
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; @return CFLAG set if okay, clear otherwise
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; @clobbers R17, R22
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uartBitbang_WaitForDataLow:
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cbi COM_DATA_DDR, COM_DATA_PIN ; set DATA port as input
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cbi COM_DATA_OUTPUT, COM_DATA_PIN ; disable internal pullup for TXD
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UART_BB_M_WAIT_FOR_PIN_LOW COM_DATA_INPUT, COM_DATA_PIN
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine uartBitbang_WaitForDataHigh
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;
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; Wait up to 1ms for data pin to become high
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; @return CFLAG set if okay, clear otherwise
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; @clobbers R17, R22
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uartBitbang_WaitForDataHigh:
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cbi COM_DATA_DDR, COM_DATA_PIN ; set DATA port as input
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cbi COM_DATA_OUTPUT, COM_DATA_PIN ; disable internal pullup for TXD
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UART_BB_M_WAIT_FOR_PIN_HIGH COM_DATA_INPUT, COM_DATA_PIN
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine uartBitbang_WaitForAttnHigh
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;
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; Wait up to 1ms for data pin to become high
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; @return CFLAG set if okay, clear otherwise
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; @clobbers R17, R22
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uartBitbang_WaitForAttnHigh:
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cbi COM_ATTN_DDR, COM_ATTN_PIN ; set ATTN port as input
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cbi COM_ATTN_OUTPUT, COM_ATTN_PIN ; disable internal pullup for ATTN
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UART_BB_M_WAIT_FOR_PIN_HIGH COM_ATTN_INPUT, COM_ATTN_PIN
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine uartBitbang_ReceivePacketIntoBuffer
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;
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; Receive a packet into buffer pointed to by X.
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; Expects interrupts to be disabled.
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;
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; @param R16 COM address to listen to
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; @param R17 maximum value for accepted msg data (i.e. buffersize minus 3)
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; @param X buffer to receive to
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; @return CFLAG set if okay (packet received), cleared on error
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; @return R16 error code if CFLAG is cleared (COM2_ERROR_NOTFORME, COM2_ERROR_IOERROR, COM2_ERROR_DATAERROR)
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; @clobbers: r16, r17, r18, X (r19, r20, r21, r22)
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uartBitbang_ReceivePacketIntoBuffer:
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mov r18, r17
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push r16
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; read destination address
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rcall uartBitbang_ReceiveByte ; read byte (R16, R17, R20, R21, R22)
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pop r17 ; pop from R16 to R17
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brcc uartBitbang_ReceivePacketIntoBuffer_ioError
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#ifndef COM_ACCEPT_ALL_DEST ; accept every destination address
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; compare destination address (accept "FF" and own address)
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cp r16, r17
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breq uartBitbang_ReceivePacketIntoBuffer_acceptAddr
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cpi r16, 0xff
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breq uartBitbang_ReceivePacketIntoBuffer_acceptAddr
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clr r16
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rjmp uartBitbang_ReceivePacketIntoBuffer_error ; clc/ret
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#endif
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uartBitbang_ReceivePacketIntoBuffer_acceptAddr:
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st X+, r16 ; store dest address, lock buffer
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; read msg length
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rcall uartBitbang_ReceiveByte ; read packet length (R16, R17, R20, R21, R22)
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brcc uartBitbang_ReceivePacketIntoBuffer_ioError
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st X+, r16
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cp r16, r18 ; (COM2_BUFFER_SIZE-3)
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brcc uartBitbang_ReceivePacketIntoBuffer_contentError ; packet too long
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inc r16 ; account for checksum byte
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mov r17, r16
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uartBitbang_ReceivePacketIntoBuffer_loop:
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push r17
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rcall uartBitbang_ReceiveByte ; read byte (R16, R17, R20, R21, R22)
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pop r17
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brcc uartBitbang_ReceivePacketIntoBuffer_ioError
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st X+, r16
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dec r17
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brne uartBitbang_ReceivePacketIntoBuffer_loop
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sec
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ret
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uartBitbang_ReceivePacketIntoBuffer_ioError:
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ldi r16, NET_IFACE_OFFS_ERR_IO_LOW
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rjmp uartBitbang_ReceivePacketIntoBuffer_error
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uartBitbang_ReceivePacketIntoBuffer_contentError:
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ldi r16, NET_IFACE_OFFS_ERR_CONTENT_LOW
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uartBitbang_ReceivePacketIntoBuffer_error:
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clc
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine uartBitbang_SendPacket
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;
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; Send packet over wire, handle ATTN line.
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;
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; @param X ptr to buffer to send
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; @return CFLAGS set if okay, cleared otherwise (index of error variable in R16)
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; @return R16 index of error variable (if CFLAGS cleared)
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; @clobbers R16, R22 (R17, R21, X)
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uartBitbang_SendPacket:
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rcall uartBitbang_AcquireBus
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brcc uartBitbang_SendPacket_lineBusyError
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rcall uartBitbang_WaitForOneBitLength ; wait for one bit duration (R22)
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rcall uartBitbang_WaitForOneBitLength ; wait for one bit duration (R22)
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adiw xh:xl, COM2_MSG_OFFS_MSGLEN
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ld r17, X
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sbiw xh:xl, COM2_MSG_OFFS_MSGLEN
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inc r17 ; account for dest addr
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inc r17 ; account for msglen byte
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inc r17 ; account for crc byte
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uartBitbang_SendPacket_loop:
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ld r16, X+
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rcall uartBitbang_SendByte ; send byte (R16, R21, R22)
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brcc uartBitbang_SendPacket_releaseBusRet
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dec r17
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brne uartBitbang_SendPacket_loop
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sec
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uartBitbang_SendPacket_releaseBusRet:
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cbi COM_ATTN_DDR, COM_ATTN_PIN ; release ATTN line (by setting direction to IN)
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brcc uartBitbang_SendPacket_ioError
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; packet successfully sent
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ret
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uartBitbang_SendPacket_ioError:
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ldi r16, NET_IFACE_OFFS_ERR_COLLISIONS_LOW
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ret
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uartBitbang_SendPacket_lineBusyError:
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ldi r16, NET_IFACE_OFFS_ERR_BUSY_LOW
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine uartBitbang_AcquireBus
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;
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; Reserve bus if free (otherwise return error)
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; Expects interrupts to be disabled.
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;
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; @return CFLAG set if okay (bus acquired), cleared on error
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; @clobbers: none
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uartBitbang_AcquireBus:
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; check for ATTN line: busy?
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cbi COM_ATTN_DDR, COM_ATTN_PIN ; set ATTN as input
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cbi COM_ATTN_OUTPUT, COM_ATTN_PIN ; disable pullup on ATTN
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nop ; needed to sample current input
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sbis COM_ATTN_INPUT, COM_ATTN_PIN ; ATTN low?
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rjmp uartBitbang_AcquireBus_busy ; jump if it is
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sbi COM_ATTN_DDR, COM_ATTN_PIN ; set ATTN as output
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cbi COM_ATTN_OUTPUT, COM_ATTN_PIN ; set ATTN low
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sec
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ret
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uartBitbang_AcquireBus_busy:
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clc
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine uartBitbang_WaitForOneBitLength
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;
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; wait for one bit length (minus cycles for call and ret).
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;
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; @clobbers r22
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uartBitbang_WaitForOneBitLength:
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Utils_WaitNanoSecs COM_BIT_LENGTH, 7, r22 ; wait for one bit duration (minus RCALL/RET)
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ret
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; @end
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