From 30654509b1e6c7db8e6db9f170e5eaec31bdc565 Mon Sep 17 00:00:00 2001
From: Martin Preuss <martin@aquamaniac.de>
Date: Mon, 21 Apr 2025 00:45:59 +0200
Subject: [PATCH] added uart_bitbang2.

---
 avr/modules/uart_bitbang2/0BUILD       |  14 +
 avr/modules/uart_bitbang2/defs.asm     |  10 +
 avr/modules/uart_bitbang2/iface.asm    | 274 ++++++++++++++++++
 avr/modules/uart_bitbang2/lowlevel.asm | 367 +++++++++++++++++++++++++
 avr/modules/uart_bitbang2/main.asm     |  10 +
 5 files changed, 675 insertions(+)
 create mode 100644 avr/modules/uart_bitbang2/0BUILD
 create mode 100644 avr/modules/uart_bitbang2/defs.asm
 create mode 100644 avr/modules/uart_bitbang2/iface.asm
 create mode 100644 avr/modules/uart_bitbang2/lowlevel.asm
 create mode 100644 avr/modules/uart_bitbang2/main.asm

diff --git a/avr/modules/uart_bitbang2/0BUILD b/avr/modules/uart_bitbang2/0BUILD
new file mode 100644
index 0000000..71d9bfa
--- /dev/null
+++ b/avr/modules/uart_bitbang2/0BUILD
@@ -0,0 +1,14 @@
+<?xml?>
+
+<gwbuild>
+
+  <extradist>
+    bytelevel.asm
+    defs.asm
+    main.asm
+    packetlevel.asm
+  </extradist>
+
+</gwbuild>
+
+
diff --git a/avr/modules/uart_bitbang2/defs.asm b/avr/modules/uart_bitbang2/defs.asm
new file mode 100644
index 0000000..a6bd53a
--- /dev/null
+++ b/avr/modules/uart_bitbang2/defs.asm
@@ -0,0 +1,10 @@
+; ***************************************************************************
+; copyright   : (C) 2025 by Martin Preuss
+; email       : martin@libchipcard.de
+;
+; ***************************************************************************
+; * This file is part of the project "AqHome".                              *
+; * Please see toplevel file COPYING of that project for license details.   *
+; ***************************************************************************
+
+
diff --git a/avr/modules/uart_bitbang2/iface.asm b/avr/modules/uart_bitbang2/iface.asm
new file mode 100644
index 0000000..f507bd5
--- /dev/null
+++ b/avr/modules/uart_bitbang2/iface.asm
@@ -0,0 +1,274 @@
+; ***************************************************************************
+; copyright   : (C) 2025 by Martin Preuss
+; email       : martin@libchipcard.de
+;
+; ***************************************************************************
+; * This file is part of the project "AqHome".                              *
+; * Please see toplevel file COPYING of that project for license details.   *
+; ***************************************************************************
+
+#ifndef UART_BITBANG_IFACE_H
+#define UART_BITBANG_IFACE_H
+
+; ***************************************************************************
+; includes
+
+.include "modules/uart_bitbang2/defs.asm"
+.include "modules/uart_bitbang2/lowlevel.asm"
+
+.include "modules/network/iface.asm"
+
+
+
+; ***************************************************************************
+; data
+
+.dseg
+
+uart_bitbang_iface: .byte NET_IFACE_SIZE
+
+
+
+
+
+; ***************************************************************************
+; code
+
+.cseg
+
+
+
+; ---------------------------------------------------------------------------
+; @routine UART_BitBang_Init @global
+;
+; @return CFLAG set if okay, clear on error
+; @clobbers R16, R17, X, Y
+
+UART_BitBang_Init:
+  ldi yl, LOW(uart_bitbang_iface)
+  ldi yh, HIGH(uart_bitbang_iface)
+  rcall NET_Interface_Init                ; (R16, R17, X)
+
+  ; init hw
+  sbi COM_IRQ_ADDR_ATTN, COM_IRQ_BIT_ATTN ; enable pin change irq for ATTN line
+  in r16, GIMSK                           ; enable pin change irq PCIE0 or PCIE1
+  ori r16, (1<<COM_IRQ_GIMSK_ATTN)
+  out GIMSK, R16
+  ldi r16, (1<<COM_IRQ_GIFR_ATTN)         ; clear pending irq by writing 1 to ATTN bit
+  out GIFR, r16
+
+  sec
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine UART_BitBang_Fini
+;
+; @return CFLAG set if okay, clear on error
+; @clobbers R16, Y
+
+UART_BitBang_Fini:
+  cbi COM_DATA_DDR, COM_DATA_PIN          ; set TXD port as input
+  cbi COM_ATTN_DDR, COM_ATTN_PIN          ; set ATTN port as input
+
+  cbi COM_IRQ_ADDR_ATTN, COM_IRQ_BIT_ATTN ; disable pin change irq for ATTN line
+  in r16, GIMSK                           ; enable pin change irq PCIE0 or PCIE1
+  andi r16, ~(1<<COM_IRQ_GIMSK_ATTN)
+  out GIMSK, R16
+  
+  ldi r16, (1<<COM_IRQ_GIFR_ATTN)         ; clear pending irq by writing 1 to ATTN bit
+  out GIFR, r16
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine UART_BitBang_Every100ms @global
+;
+; Routine doing periodical stuff (like sending outbound mesages)
+;
+; @param Y pointer to start of interface data
+; @clobbers R16 (R17, R18, R21, R22, R24, R25, X)
+
+UART_BitBang_Every100ms:
+  push r15
+    in r15, SREG
+    cli
+    rcall NET_Interface_Periodically         ; (R16)
+    rcall uartBitBang_sendNextPkg            ; (R16, R17, R18, R21, R22, R24, R25, X)
+    out SREG, r15
+  pop r15
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine uartBitBang_sendNextPkg @global
+;
+; Check whether there is an outgoing message in interface data
+; and send it if possible.
+;
+; @return CFLAG set if okay, clear on error
+; @param Y pointer to start of interface data
+; @clobbers R16 (R17, R18, R21, R22, R24, R25, X)
+
+uartBitBang_sendNextPkg:
+  rcall NET_Interface_PeekNextOutgoingMsgNum ; (R17, R18, X)
+  brcc uartBitBang_sendNextPkg_end
+  rcall NET_Buffer_Locate                    ; get pointer to buffer (R17)
+  brcc uartBitBang_sendNextPkg_end
+  adiw xh:xl, 1                              ; skip buffer header
+  rcall uartBitbang_SendPacket               ; (R16, R17, R21, R22, X)
+  brcc uartBitBang_sendNextPkg_error
+  rcall NET_Interface_GetNextOutgoingMsgNum  ; remove from stack (R17, R18, X)
+  rcall NET_Buffer_ReleaseByNum              ; release buffer (R16, X)
+  ldi r16, NET_IFACE_OFFS_PACKETSOUT_LOW
+  rcall NET_Interface_IncCounter16           ; (R24, R25)
+  sec
+  rjmp uartBitBang_sendNextPkg_end
+uartBitBang_sendNextPkg_error:
+  rcall NET_Interface_IncCounter16           ; (R24, R25)
+uartBitBang_sendNextPkg_end:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine uartBitbang_receiveNextPkg
+;
+; Receive packet.
+;
+; @return CFLAG set if okay (packet received), cleared on error
+; @clobbers R16, R17, X (R18, R19, R20, R21, R22, R24, R25)
+
+uartBitbang_receiveNextPkg:
+  rcall NET_Buffer_Alloc                          ; (R16, R17, X)
+  brcs uartBitbang_receiveNextPkg_gotBuffer
+  ldi r16, NET_IFACE_OFFS_ERR_NOBUF_LOW
+  rcall NET_Interface_IncCounter16                ; (R24, R25)
+  clc
+  rjmp uartBitbang_receiveNextPkg_end
+uartBitbang_receiveNextPkg_gotBuffer:
+  push r16                                        ; buffer number
+    adiw xh:xl, 1
+    rcall uartBitbang_receiveAndCheckPkg          ; (r16, r17, r18, r19, r20, r21, r22, X)
+  pop r17                                         ; pop buffer number to R17
+  brcs uartBitbang_receiveNextPkg_gotPkg
+  tst r16                                         ; error code=0: pkg not for me
+  breq uartBitbang_receiveNextPkg_RelBuffer
+uartBitbang_receiveNextPkg_incCntRelBuffer:
+  rcall NET_Interface_IncCounter16                ; (R24, R25)
+uartBitbang_receiveNextPkg_RelBuffer:
+  mov r16, r17
+  rcall NET_Buffer_ReleaseByNum                   ; (R16, X)
+  clc
+  rjmp uartBitbang_receiveNextPkg_end
+uartBitbang_receiveNextPkg_gotPkg:
+  mov r16, r17
+  rcall NET_AddIncomingMsgNum                     ; (R17, R18, X)
+  ldi r16, NET_IFACE_OFFS_ERR_NOBUF_LOW
+  brcc uartBitbang_receiveNextPkg_incCntRelBuffer
+  ldi r16, NET_IFACE_OFFS_PACKETSIN_LOW
+  rcall NET_Interface_IncCounter16                ; (R24, R25)
+  sec
+uartBitbang_receiveNextPkg_end:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine uartBitbang_receiveAndCheckPkg
+;
+; Receive a packet into buffer pointed to by X and CRC check it.
+; Expects interrupts to be disabled.
+;
+; @param X   buffer to receive to
+; @param Y pointer to start of interface data
+; @return CFLAG set if okay (packet received), cleared on error
+; @return R16 error var offset if CFLAG is cleared
+; @clobbers: r16 (r17, r18, r19, r20, r21, r22, X)
+
+uartBitbang_receiveAndCheckPkg:
+  ldd r16, Y+NET_IFACE_OFFS_ADDRESS
+  ldi r17, (NET_BUFFERS_SIZE-2)
+  push xl
+    push xh
+      rcall uartBitbang_ReceivePacketIntoBuffer ; (r16, r17, r18, r19, r20, r21, r22, X)
+    pop xh
+  pop xl
+  brcc uartBitbang_receiveAndCheckPkg_end
+  rcall NETMSG_CheckMessageInBuffer             ; (R16, R17, R18, R19, R20, X)
+  ldi r16, NET_IFACE_OFFS_ERR_CONTENT_LOW
+uartBitbang_receiveAndCheckPkg_end:
+  ret
+; @end
+
+
+
+
+
+; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+; ISR
+; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+
+; ---------------------------------------------------------------------------
+; @routine UART_BitBang_PcintIsr @global @isr
+;
+; ISR for PCINT0/1
+;
+; @clobbers: none
+
+UART_BitBang_PcintIsr:
+  push r15
+    in r15, SREG
+    sbic COM_ATTN_INPUT, COM_ATTN_PIN
+      rjmp uartBitbangPcintIsr_end
+    ; low, read packet
+    push r16
+      push r17
+        push r18
+          push r19
+            push r20
+              push r21
+                push r22
+                  push r24
+                    push r25
+                      push xl
+                        push xh
+                          push yl
+                            push yh
+                              ldi yl, LOW(uart_bitbang_iface)
+                              ldi yh, HIGH(uart_bitbang_iface)
+                              rcall uartBitbang_receiveNextPkg ; (R16, R17, R18, R19, R20, R21, R22, R24, R25, X)
+                            pop yh
+                          pop yl
+                        pop xh
+                      pop xl
+                    pop r25
+                  pop r24
+                pop r22
+              pop r21
+            pop r20
+          pop r19
+        pop r18
+      pop r17
+    pop r16
+uartBitbangPcintIsr_end:
+    out SREG, r15
+  pop r15
+  reti
+; @end
+
+
+
+
+#endif ; UART_BITBANG_IFACE_H
+
diff --git a/avr/modules/uart_bitbang2/lowlevel.asm b/avr/modules/uart_bitbang2/lowlevel.asm
new file mode 100644
index 0000000..8e33535
--- /dev/null
+++ b/avr/modules/uart_bitbang2/lowlevel.asm
@@ -0,0 +1,367 @@
+; ***************************************************************************
+; copyright   : (C) 2025 by Martin Preuss
+; email       : martin@libchipcard.de
+;
+; ***************************************************************************
+; * This file is part of the project "AqHome".                              *
+; * Please see toplevel file COPYING of that project for license details.   *
+; ***************************************************************************
+
+
+
+; ***************************************************************************
+; code
+
+; ---------------------------------------------------------------------------
+; @macro UART_BB_M_WAIT_FOR_PIN_LOW IN_REG_DATA, IN_PINNUM
+;                                 0            1
+; Wait for a pin to become low
+; @param %0 DATA register for input pin (e.g. PINB)
+; @param %1 pin number for input (e.g. PORTB1)
+; @return CFLAG set if okay, clear otherwise
+; @clobbers R17, R22
+
+.macro UART_BB_M_WAIT_FOR_PIN_LOW
+  ldi r17, 200
+l_loop:
+    sbis @0, @1
+      rjmp l_reached
+    Utils_WaitNanoSecs 5000, 0, r22                ; wait for 5us
+    dec r17
+  brne l_loop
+  clc
+  rjmp l_end
+l_reached:
+  sec
+l_end:
+.endmacro
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @macro UART_BB_M_WAIT_FOR_PIN_HIGH IN_REG_DATA, IN_PINNUM
+;                                 0            1
+; Wait for a pin to become high (up to 1ms)
+; @param %0 DATA register for input pin (e.g. PINB)
+; @param %1 pin number for input (e.g. PORTB1)
+; @return CFLAG set if okay, clear otherwise
+; @clobbers R17, R22
+
+.macro UART_BB_M_WAIT_FOR_PIN_HIGH
+  ldi r17, 200
+l_loop:
+    sbic @0, @1
+      rjmp l_reached
+    Utils_WaitNanoSecs 5000, 0, r22                ; wait for 5us
+    dec r17
+  brne l_loop
+  clc
+  rjmp l_end
+l_reached:
+  sec
+l_end:
+.endmacro
+; @end
+
+
+
+
+
+
+; ---------------------------------------------------------------------------
+; @routine uartBitbang_SendByte
+;
+; Send a byte.
+; We only set the data pin to low at the beginning for the startbit. After that
+; we only change the pin direction (e.g. input vs output):
+; - for 0 bit: set DDR to output, forcing the data line low
+; - for 1 bit: set DDR to input, letting the external pullup R pull the data line to HIGH
+;              since the output pin is still set to 0 the internal pullup is disabled
+; Expects interrupts to be disabled.
+;
+; @param R16 byte to send
+; @return CFLAG set if okay, clear otherwise
+; @clobbers R16, R21, R22
+
+uartBitbang_SendByte:
+  cbi COM_DATA_DDR, COM_DATA_PIN                   ; set DATA port as input
+  cbi COM_DATA_OUTPUT, COM_DATA_PIN                ; disable internal pullup for DATA
+  ldi r21, 8                                       ; +1 bits left
+  ; send startbit
+  sbi COM_DATA_DDR, COM_DATA_PIN                   ; +2 set DATA as output
+  cbi COM_DATA_OUTPUT, COM_DATA_PIN                ; +2 set DATA low
+  Utils_WaitNanoSecs COM_BIT_LENGTH, 1, r22        ; wait for one bit duration
+  ; send data bits
+uartBitbang_SendByte_loop:                         ; 9 for low bit
+    lsr r16                                        ; 1+ bit to send -> CARRY
+    brcs uartBitbang_SendByte_setHigh              ; HI: +2, LO: +1
+uartBitbang_SendByte_setLow:
+    sbi COM_DATA_DDR, COM_DATA_PIN                 ; +2 set DATA as output
+    cbi COM_DATA_OUTPUT, COM_DATA_PIN              ; +2 set DATA low
+    Utils_WaitNanoSecs COM_BIT_LENGTH, 11, r22
+    rjmp uartBitbang_SendByte_loopEnd              ; +2
+uartBitbang_SendByte_setHigh:
+    cbi COM_DATA_DDR, COM_DATA_PIN                 ; +2 set DATA as input, pullup R makes it ONE
+    nop                                            ; +1 (to make pin change available)
+    Utils_WaitNanoSecs COM_HALFBIT_LENGTH, 0, r22  ; wait for half a bit length for line to safely settle
+    sbis COM_DATA_INPUT, COM_DATA_PIN              ; +1 if no skip, +2 if skipped
+      rjmp uartBitbang_SendByte_error              ; +2 if error (collision: we wanted line to be high but it is low)
+    Utils_WaitNanoSecs COM_HALFBIT_LENGTH, 11, r22
+uartBitbang_SendByte_loopEnd:
+    dec r21                                        ; +1
+  brne uartBitbang_SendByte_loop                   ; +2, sum per loop: 10 cycles
+  ; send stopbit
+  cbi COM_DATA_DDR, COM_DATA_PIN                   ; +2 set DATA as input, pullup R makes it ONE
+  Utils_WaitNanoSecs COM_BIT_LENGTH, 0, r22        ; wait for one bit length
+  sec
+  ret
+
+uartBitbang_SendByte_error:
+  clc
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine uartBitbangReceiveByte
+;
+; Read a byte.
+; Expects interrupts to be disabled.
+;
+; @return CFLAG set if okay, clear otherwise
+; @return R16 byte received
+; @clobbers R16, R20, R21, R22 (R17)
+
+uartBitbang_ReceiveByte:
+  cbi COM_DATA_DDR, COM_DATA_PIN               ; set DATA port as input
+  cbi COM_DATA_OUTPUT, COM_DATA_PIN            ; disable internal pullup for RXD
+  ldi r21, 8                                   ; bits left
+  clr r20                                      ; byte currently receiving
+  ; wait for startbit
+  rcall uartBitbang_WaitForDataLow             ; (R17, R22)
+  brcc uartBitbang_ReceiveByte_error
+  Utils_WaitNanoSecs COM_HALFBIT_LENGTH, 10, r22  ; goto middle of startbit to maximize sync stability
+uartBitbang_ReceiveByte_loop:
+    Utils_WaitNanoSecs COM_BIT_LENGTH, 8, r22  ; 8 cycles used in the complete loop between waits
+    sec                                        ; +1
+    sbic COM_DATA_INPUT, COM_DATA_PIN          ; LOW: +2, HIGH: +1
+      rjmp uartBitbang_ReceiveByte_shiftIn     ; HIGH: +2, rjmp, use set CFLAG
+    clc                                        ; LOW: +1
+uartBitbang_ReceiveByte_shiftIn:
+    ror r20                                    ; +1
+    dec r21                                    ; +1
+  brne uartBitbang_ReceiveByte_loop                                  ; +2, sum per loop: 8 cycles
+  rcall uartBitbang_WaitForDataHigh            ; wait for start of stopbit
+  brcc uartBitbang_ReceiveByte_error
+  mov r16, r20
+  sec
+  ret
+uartBitbang_ReceiveByte_error:
+  clc
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine uartBitbang_WaitForDataLow
+;
+; Wait up to 1ms for data pin to become low
+; @return CFLAG set if okay, clear otherwise
+; @clobbers R17, R22
+
+uartBitbang_WaitForDataLow:
+  cbi COM_DATA_DDR, COM_DATA_PIN          ; set DATA port as input
+  cbi COM_DATA_OUTPUT, COM_DATA_PIN       ; disable internal pullup for TXD
+  UART_BB_M_WAIT_FOR_PIN_LOW COM_DATA_INPUT, COM_DATA_PIN
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine uartBitbang_WaitForDataHigh
+;
+; Wait up to 1ms for data pin to become high
+; @return CFLAG set if okay, clear otherwise
+; @clobbers R17, R22
+
+uartBitbang_WaitForDataHigh:
+  cbi COM_DATA_DDR, COM_DATA_PIN          ; set DATA port as input
+  cbi COM_DATA_OUTPUT, COM_DATA_PIN       ; disable internal pullup for TXD
+  UART_BB_M_WAIT_FOR_PIN_HIGH COM_DATA_INPUT, COM_DATA_PIN
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine uartBitbang_WaitForAttnHigh
+;
+; Wait up to 1ms for data pin to become high
+; @return CFLAG set if okay, clear otherwise
+; @clobbers R17, R22
+
+uartBitbang_WaitForAttnHigh:
+  cbi COM_ATTN_DDR, COM_ATTN_PIN          ; set ATTN port as input
+  cbi COM_ATTN_OUTPUT, COM_ATTN_PIN       ; disable internal pullup for ATTN
+  UART_BB_M_WAIT_FOR_PIN_HIGH COM_ATTN_INPUT, COM_ATTN_PIN
+  ret
+; @end
+
+
+
+
+
+
+; ---------------------------------------------------------------------------
+; @routine uartBitbang_ReceivePacketIntoBuffer
+;
+; Receive a packet into buffer pointed to by X.
+; Expects interrupts to be disabled.
+;
+; @param R16 COM address to listen to
+; @param R17 maximum value for accepted msg data (i.e. buffersize minus 3)
+; @param X   buffer to receive to
+; @return CFLAG set if okay (packet received), cleared on error
+; @return R16 error code if CFLAG is cleared (COM2_ERROR_NOTFORME, COM2_ERROR_IOERROR, COM2_ERROR_DATAERROR)
+; @clobbers: r16, r17, r18, X (r19, r20, r21, r22)
+
+uartBitbang_ReceivePacketIntoBuffer:
+  mov r18, r17
+  push r16
+    ; read destination address
+    rcall uartBitbang_ReceiveByte             ; read byte (R16, R17, R20, R21, R22)
+  pop r17                                     ; pop from R16 to R17
+  brcc uartBitbang_ReceivePacketIntoBuffer_ioError
+#ifndef COM_ACCEPT_ALL_DEST                    ; accept every destination address
+  ; compare destination address (accept "FF" and own address)
+  cp r16, r17
+  breq uartBitbang_ReceivePacketIntoBuffer_acceptAddr
+  cpi r16, 0xff
+  breq uartBitbang_ReceivePacketIntoBuffer_acceptAddr
+  clr r16
+  rjmp uartBitbang_ReceivePacketIntoBuffer_error        ; clc/ret
+#endif
+uartBitbang_ReceivePacketIntoBuffer_acceptAddr:
+  st X+, r16                                  ; store dest address, lock buffer
+  ; read msg length
+  rcall uartBitbang_ReceiveByte               ; read packet length (R16, R17, R20, R21, R22)
+  brcc uartBitbang_ReceivePacketIntoBuffer_ioError
+  st X+, r16
+  cp r16, r18                                 ; (COM2_BUFFER_SIZE-3)
+  brcc uartBitbang_ReceivePacketIntoBuffer_contentError ; packet too long
+  inc r16                                     ; account for checksum byte
+  mov r17, r16
+uartBitbang_ReceivePacketIntoBuffer_loop:
+    push r17
+      rcall uartBitbang_ReceiveByte           ; read byte (R16, R17, R20, R21, R22)
+    pop r17
+    brcc uartBitbang_ReceivePacketIntoBuffer_ioError
+    st X+, r16
+    dec r17
+  brne uartBitbang_ReceivePacketIntoBuffer_loop
+  sec
+  ret
+uartBitbang_ReceivePacketIntoBuffer_ioError:
+  ldi r16, NET_IFACE_OFFS_ERR_IO_LOW
+  rjmp uartBitbang_ReceivePacketIntoBuffer_error
+uartBitbang_ReceivePacketIntoBuffer_contentError:
+  ldi r16, NET_IFACE_OFFS_ERR_CONTENT_LOW
+uartBitbang_ReceivePacketIntoBuffer_error:
+  clc
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine uartBitbang_SendPacket
+;
+; Send packet over wire, handle ATTN line.
+;
+; @param  X ptr to buffer to send
+; @return CFLAGS set if okay, cleared otherwise (index of error variable in R16)
+; @return R16 index of error variable (if CFLAGS cleared)
+; @clobbers R16, R22 (R17, R21, X)
+
+uartBitbang_SendPacket:
+  rcall uartBitbang_AcquireBus
+  brcc uartBitbang_SendPacket_lineBusyError
+  
+  rcall uartBitbang_WaitForOneBitLength          ; wait for one bit duration (R22)
+  rcall uartBitbang_WaitForOneBitLength          ; wait for one bit duration (R22)
+
+  adiw xh:xl, COM2_MSG_OFFS_MSGLEN
+  ld r17, X
+  sbiw xh:xl, COM2_MSG_OFFS_MSGLEN
+  inc r17                                        ; account for dest addr
+  inc r17                                        ; account for msglen byte
+  inc r17                                        ; account for crc byte
+
+uartBitbang_SendPacket_loop:
+    ld r16, X+
+    rcall uartBitbang_SendByte                   ; send byte (R16, R21, R22)
+    brcc uartBitbang_SendPacket_releaseBusRet
+    dec r17
+  brne uartBitbang_SendPacket_loop
+  sec
+uartBitbang_SendPacket_releaseBusRet:
+  cbi COM_ATTN_DDR, COM_ATTN_PIN                 ; release ATTN line (by setting direction to IN)
+  brcc uartBitbang_SendPacket_ioError
+  ; packet successfully sent
+  ret
+uartBitbang_SendPacket_ioError:
+  ldi r16, NET_IFACE_OFFS_ERR_COLLISIONS_LOW
+  ret
+uartBitbang_SendPacket_lineBusyError:
+  ldi r16, NET_IFACE_OFFS_ERR_BUSY_LOW
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine uartBitbang_AcquireBus
+;
+; Reserve bus if free (otherwise return error)
+; Expects interrupts to be disabled.
+;
+; @return CFLAG set if okay (bus acquired), cleared on error
+; @clobbers: none
+
+uartBitbang_AcquireBus:
+  ; check for ATTN line: busy?
+  cbi COM_ATTN_DDR, COM_ATTN_PIN                 ; set ATTN as input
+  cbi COM_ATTN_OUTPUT, COM_ATTN_PIN              ; disable pullup on ATTN
+  nop                                            ; needed to sample current input
+  sbis COM_ATTN_INPUT, COM_ATTN_PIN              ; ATTN low?
+    rjmp uartBitbang_AcquireBus_busy             ; jump if it is
+  sbi COM_ATTN_DDR, COM_ATTN_PIN                 ; set ATTN as output
+  cbi COM_ATTN_OUTPUT, COM_ATTN_PIN              ; set ATTN low
+  sec
+  ret
+uartBitbang_AcquireBus_busy:
+  clc
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine uartBitbang_WaitForOneBitLength
+;
+; wait for one bit length (minus cycles for call and ret).
+;
+; @clobbers r22
+
+uartBitbang_WaitForOneBitLength:
+  Utils_WaitNanoSecs COM_BIT_LENGTH, 7, r22       ; wait for one bit duration (minus RCALL/RET)
+  ret
+; @end
+
+
+
+
diff --git a/avr/modules/uart_bitbang2/main.asm b/avr/modules/uart_bitbang2/main.asm
new file mode 100644
index 0000000..a6bd53a
--- /dev/null
+++ b/avr/modules/uart_bitbang2/main.asm
@@ -0,0 +1,10 @@
+; ***************************************************************************
+; copyright   : (C) 2025 by Martin Preuss
+; email       : martin@libchipcard.de
+;
+; ***************************************************************************
+; * This file is part of the project "AqHome".                              *
+; * Please see toplevel file COPYING of that project for license details.   *
+; ***************************************************************************
+
+