added uart_bitbang2.
This commit is contained in:
Martin Preuss
14
avr/modules/uart_bitbang2/0BUILD
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14
avr/modules/uart_bitbang2/0BUILD
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@@ -0,0 +1,14 @@
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<?xml?>
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<gwbuild>
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<extradist>
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bytelevel.asm
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defs.asm
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main.asm
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packetlevel.asm
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</extradist>
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</gwbuild>
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10
avr/modules/uart_bitbang2/defs.asm
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10
avr/modules/uart_bitbang2/defs.asm
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@@ -0,0 +1,10 @@
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; ***************************************************************************
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; copyright : (C) 2025 by Martin Preuss
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; email : martin@libchipcard.de
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;
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; ***************************************************************************
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; * This file is part of the project "AqHome". *
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; * Please see toplevel file COPYING of that project for license details. *
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; ***************************************************************************
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274
avr/modules/uart_bitbang2/iface.asm
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274
avr/modules/uart_bitbang2/iface.asm
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@@ -0,0 +1,274 @@
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; ***************************************************************************
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; copyright : (C) 2025 by Martin Preuss
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; email : martin@libchipcard.de
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;
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; ***************************************************************************
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; * This file is part of the project "AqHome". *
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; * Please see toplevel file COPYING of that project for license details. *
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; ***************************************************************************
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#ifndef UART_BITBANG_IFACE_H
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#define UART_BITBANG_IFACE_H
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; ***************************************************************************
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; includes
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.include "modules/uart_bitbang2/defs.asm"
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.include "modules/uart_bitbang2/lowlevel.asm"
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.include "modules/network/iface.asm"
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; ***************************************************************************
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; data
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.dseg
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uart_bitbang_iface: .byte NET_IFACE_SIZE
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; ***************************************************************************
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; code
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.cseg
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; ---------------------------------------------------------------------------
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; @routine UART_BitBang_Init @global
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;
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; @return CFLAG set if okay, clear on error
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; @clobbers R16, R17, X, Y
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UART_BitBang_Init:
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ldi yl, LOW(uart_bitbang_iface)
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ldi yh, HIGH(uart_bitbang_iface)
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rcall NET_Interface_Init ; (R16, R17, X)
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; init hw
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sbi COM_IRQ_ADDR_ATTN, COM_IRQ_BIT_ATTN ; enable pin change irq for ATTN line
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in r16, GIMSK ; enable pin change irq PCIE0 or PCIE1
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ori r16, (1<<COM_IRQ_GIMSK_ATTN)
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out GIMSK, R16
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ldi r16, (1<<COM_IRQ_GIFR_ATTN) ; clear pending irq by writing 1 to ATTN bit
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out GIFR, r16
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sec
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_BitBang_Fini
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;
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; @return CFLAG set if okay, clear on error
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; @clobbers R16, Y
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UART_BitBang_Fini:
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cbi COM_DATA_DDR, COM_DATA_PIN ; set TXD port as input
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cbi COM_ATTN_DDR, COM_ATTN_PIN ; set ATTN port as input
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cbi COM_IRQ_ADDR_ATTN, COM_IRQ_BIT_ATTN ; disable pin change irq for ATTN line
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in r16, GIMSK ; enable pin change irq PCIE0 or PCIE1
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andi r16, ~(1<<COM_IRQ_GIMSK_ATTN)
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out GIMSK, R16
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ldi r16, (1<<COM_IRQ_GIFR_ATTN) ; clear pending irq by writing 1 to ATTN bit
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out GIFR, r16
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_BitBang_Every100ms @global
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;
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; Routine doing periodical stuff (like sending outbound mesages)
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;
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; @param Y pointer to start of interface data
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; @clobbers R16 (R17, R18, R21, R22, R24, R25, X)
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UART_BitBang_Every100ms:
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push r15
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in r15, SREG
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cli
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rcall NET_Interface_Periodically ; (R16)
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rcall uartBitBang_sendNextPkg ; (R16, R17, R18, R21, R22, R24, R25, X)
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out SREG, r15
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pop r15
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine uartBitBang_sendNextPkg @global
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;
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; Check whether there is an outgoing message in interface data
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; and send it if possible.
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;
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; @return CFLAG set if okay, clear on error
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; @param Y pointer to start of interface data
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; @clobbers R16 (R17, R18, R21, R22, R24, R25, X)
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uartBitBang_sendNextPkg:
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rcall NET_Interface_PeekNextOutgoingMsgNum ; (R17, R18, X)
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brcc uartBitBang_sendNextPkg_end
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rcall NET_Buffer_Locate ; get pointer to buffer (R17)
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brcc uartBitBang_sendNextPkg_end
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adiw xh:xl, 1 ; skip buffer header
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rcall uartBitbang_SendPacket ; (R16, R17, R21, R22, X)
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brcc uartBitBang_sendNextPkg_error
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rcall NET_Interface_GetNextOutgoingMsgNum ; remove from stack (R17, R18, X)
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rcall NET_Buffer_ReleaseByNum ; release buffer (R16, X)
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ldi r16, NET_IFACE_OFFS_PACKETSOUT_LOW
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rcall NET_Interface_IncCounter16 ; (R24, R25)
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sec
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rjmp uartBitBang_sendNextPkg_end
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uartBitBang_sendNextPkg_error:
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rcall NET_Interface_IncCounter16 ; (R24, R25)
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uartBitBang_sendNextPkg_end:
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine uartBitbang_receiveNextPkg
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;
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; Receive packet.
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;
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; @return CFLAG set if okay (packet received), cleared on error
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; @clobbers R16, R17, X (R18, R19, R20, R21, R22, R24, R25)
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uartBitbang_receiveNextPkg:
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rcall NET_Buffer_Alloc ; (R16, R17, X)
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brcs uartBitbang_receiveNextPkg_gotBuffer
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ldi r16, NET_IFACE_OFFS_ERR_NOBUF_LOW
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rcall NET_Interface_IncCounter16 ; (R24, R25)
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clc
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rjmp uartBitbang_receiveNextPkg_end
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uartBitbang_receiveNextPkg_gotBuffer:
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push r16 ; buffer number
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adiw xh:xl, 1
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rcall uartBitbang_receiveAndCheckPkg ; (r16, r17, r18, r19, r20, r21, r22, X)
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pop r17 ; pop buffer number to R17
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brcs uartBitbang_receiveNextPkg_gotPkg
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tst r16 ; error code=0: pkg not for me
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breq uartBitbang_receiveNextPkg_RelBuffer
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uartBitbang_receiveNextPkg_incCntRelBuffer:
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rcall NET_Interface_IncCounter16 ; (R24, R25)
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uartBitbang_receiveNextPkg_RelBuffer:
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mov r16, r17
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rcall NET_Buffer_ReleaseByNum ; (R16, X)
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clc
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rjmp uartBitbang_receiveNextPkg_end
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uartBitbang_receiveNextPkg_gotPkg:
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mov r16, r17
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rcall NET_AddIncomingMsgNum ; (R17, R18, X)
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ldi r16, NET_IFACE_OFFS_ERR_NOBUF_LOW
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brcc uartBitbang_receiveNextPkg_incCntRelBuffer
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ldi r16, NET_IFACE_OFFS_PACKETSIN_LOW
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rcall NET_Interface_IncCounter16 ; (R24, R25)
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sec
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uartBitbang_receiveNextPkg_end:
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine uartBitbang_receiveAndCheckPkg
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;
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; Receive a packet into buffer pointed to by X and CRC check it.
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; Expects interrupts to be disabled.
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;
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; @param X buffer to receive to
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; @param Y pointer to start of interface data
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; @return CFLAG set if okay (packet received), cleared on error
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; @return R16 error var offset if CFLAG is cleared
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; @clobbers: r16 (r17, r18, r19, r20, r21, r22, X)
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uartBitbang_receiveAndCheckPkg:
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ldd r16, Y+NET_IFACE_OFFS_ADDRESS
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ldi r17, (NET_BUFFERS_SIZE-2)
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push xl
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push xh
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rcall uartBitbang_ReceivePacketIntoBuffer ; (r16, r17, r18, r19, r20, r21, r22, X)
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pop xh
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pop xl
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brcc uartBitbang_receiveAndCheckPkg_end
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rcall NETMSG_CheckMessageInBuffer ; (R16, R17, R18, R19, R20, X)
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ldi r16, NET_IFACE_OFFS_ERR_CONTENT_LOW
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uartBitbang_receiveAndCheckPkg_end:
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ret
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; @end
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; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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; ISR
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; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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; ---------------------------------------------------------------------------
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; @routine UART_BitBang_PcintIsr @global @isr
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;
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; ISR for PCINT0/1
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;
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; @clobbers: none
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UART_BitBang_PcintIsr:
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push r15
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in r15, SREG
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sbic COM_ATTN_INPUT, COM_ATTN_PIN
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rjmp uartBitbangPcintIsr_end
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; low, read packet
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push r16
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push r17
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push r18
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push r19
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push r20
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push r21
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push r22
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push r24
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push r25
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push xl
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push xh
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push yl
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push yh
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ldi yl, LOW(uart_bitbang_iface)
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ldi yh, HIGH(uart_bitbang_iface)
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rcall uartBitbang_receiveNextPkg ; (R16, R17, R18, R19, R20, R21, R22, R24, R25, X)
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pop yh
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pop yl
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pop xh
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pop xl
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pop r25
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pop r24
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pop r22
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pop r21
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pop r20
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pop r19
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pop r18
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pop r17
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pop r16
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uartBitbangPcintIsr_end:
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out SREG, r15
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pop r15
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reti
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; @end
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#endif ; UART_BITBANG_IFACE_H
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367
avr/modules/uart_bitbang2/lowlevel.asm
Normal file
367
avr/modules/uart_bitbang2/lowlevel.asm
Normal file
@@ -0,0 +1,367 @@
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; ***************************************************************************
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; copyright : (C) 2025 by Martin Preuss
|
||||
; email : martin@libchipcard.de
|
||||
;
|
||||
; ***************************************************************************
|
||||
; * This file is part of the project "AqHome". *
|
||||
; * Please see toplevel file COPYING of that project for license details. *
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||||
; ***************************************************************************
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; ***************************************************************************
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; code
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; ---------------------------------------------------------------------------
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; @macro UART_BB_M_WAIT_FOR_PIN_LOW IN_REG_DATA, IN_PINNUM
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; 0 1
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; Wait for a pin to become low
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; @param %0 DATA register for input pin (e.g. PINB)
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; @param %1 pin number for input (e.g. PORTB1)
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; @return CFLAG set if okay, clear otherwise
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; @clobbers R17, R22
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.macro UART_BB_M_WAIT_FOR_PIN_LOW
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ldi r17, 200
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l_loop:
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sbis @0, @1
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rjmp l_reached
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Utils_WaitNanoSecs 5000, 0, r22 ; wait for 5us
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dec r17
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brne l_loop
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clc
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rjmp l_end
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l_reached:
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sec
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l_end:
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.endmacro
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; @end
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; ---------------------------------------------------------------------------
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; @macro UART_BB_M_WAIT_FOR_PIN_HIGH IN_REG_DATA, IN_PINNUM
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; 0 1
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; Wait for a pin to become high (up to 1ms)
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; @param %0 DATA register for input pin (e.g. PINB)
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; @param %1 pin number for input (e.g. PORTB1)
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; @return CFLAG set if okay, clear otherwise
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; @clobbers R17, R22
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.macro UART_BB_M_WAIT_FOR_PIN_HIGH
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ldi r17, 200
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l_loop:
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sbic @0, @1
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rjmp l_reached
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Utils_WaitNanoSecs 5000, 0, r22 ; wait for 5us
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dec r17
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brne l_loop
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clc
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rjmp l_end
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l_reached:
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sec
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l_end:
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.endmacro
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; @end
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; ---------------------------------------------------------------------------
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; @routine uartBitbang_SendByte
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;
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; Send a byte.
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; We only set the data pin to low at the beginning for the startbit. After that
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; we only change the pin direction (e.g. input vs output):
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; - for 0 bit: set DDR to output, forcing the data line low
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; - for 1 bit: set DDR to input, letting the external pullup R pull the data line to HIGH
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; since the output pin is still set to 0 the internal pullup is disabled
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; Expects interrupts to be disabled.
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;
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; @param R16 byte to send
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; @return CFLAG set if okay, clear otherwise
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; @clobbers R16, R21, R22
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uartBitbang_SendByte:
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cbi COM_DATA_DDR, COM_DATA_PIN ; set DATA port as input
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cbi COM_DATA_OUTPUT, COM_DATA_PIN ; disable internal pullup for DATA
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ldi r21, 8 ; +1 bits left
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; send startbit
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sbi COM_DATA_DDR, COM_DATA_PIN ; +2 set DATA as output
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cbi COM_DATA_OUTPUT, COM_DATA_PIN ; +2 set DATA low
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Utils_WaitNanoSecs COM_BIT_LENGTH, 1, r22 ; wait for one bit duration
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; send data bits
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uartBitbang_SendByte_loop: ; 9 for low bit
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lsr r16 ; 1+ bit to send -> CARRY
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brcs uartBitbang_SendByte_setHigh ; HI: +2, LO: +1
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uartBitbang_SendByte_setLow:
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sbi COM_DATA_DDR, COM_DATA_PIN ; +2 set DATA as output
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cbi COM_DATA_OUTPUT, COM_DATA_PIN ; +2 set DATA low
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||||
Utils_WaitNanoSecs COM_BIT_LENGTH, 11, r22
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rjmp uartBitbang_SendByte_loopEnd ; +2
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||||
uartBitbang_SendByte_setHigh:
|
||||
cbi COM_DATA_DDR, COM_DATA_PIN ; +2 set DATA as input, pullup R makes it ONE
|
||||
nop ; +1 (to make pin change available)
|
||||
Utils_WaitNanoSecs COM_HALFBIT_LENGTH, 0, r22 ; wait for half a bit length for line to safely settle
|
||||
sbis COM_DATA_INPUT, COM_DATA_PIN ; +1 if no skip, +2 if skipped
|
||||
rjmp uartBitbang_SendByte_error ; +2 if error (collision: we wanted line to be high but it is low)
|
||||
Utils_WaitNanoSecs COM_HALFBIT_LENGTH, 11, r22
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||||
uartBitbang_SendByte_loopEnd:
|
||||
dec r21 ; +1
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||||
brne uartBitbang_SendByte_loop ; +2, sum per loop: 10 cycles
|
||||
; send stopbit
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||||
cbi COM_DATA_DDR, COM_DATA_PIN ; +2 set DATA as input, pullup R makes it ONE
|
||||
Utils_WaitNanoSecs COM_BIT_LENGTH, 0, r22 ; wait for one bit length
|
||||
sec
|
||||
ret
|
||||
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uartBitbang_SendByte_error:
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||||
clc
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ret
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; @end
|
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|
||||
|
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|
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; ---------------------------------------------------------------------------
|
||||
; @routine uartBitbangReceiveByte
|
||||
;
|
||||
; Read a byte.
|
||||
; Expects interrupts to be disabled.
|
||||
;
|
||||
; @return CFLAG set if okay, clear otherwise
|
||||
; @return R16 byte received
|
||||
; @clobbers R16, R20, R21, R22 (R17)
|
||||
|
||||
uartBitbang_ReceiveByte:
|
||||
cbi COM_DATA_DDR, COM_DATA_PIN ; set DATA port as input
|
||||
cbi COM_DATA_OUTPUT, COM_DATA_PIN ; disable internal pullup for RXD
|
||||
ldi r21, 8 ; bits left
|
||||
clr r20 ; byte currently receiving
|
||||
; wait for startbit
|
||||
rcall uartBitbang_WaitForDataLow ; (R17, R22)
|
||||
brcc uartBitbang_ReceiveByte_error
|
||||
Utils_WaitNanoSecs COM_HALFBIT_LENGTH, 10, r22 ; goto middle of startbit to maximize sync stability
|
||||
uartBitbang_ReceiveByte_loop:
|
||||
Utils_WaitNanoSecs COM_BIT_LENGTH, 8, r22 ; 8 cycles used in the complete loop between waits
|
||||
sec ; +1
|
||||
sbic COM_DATA_INPUT, COM_DATA_PIN ; LOW: +2, HIGH: +1
|
||||
rjmp uartBitbang_ReceiveByte_shiftIn ; HIGH: +2, rjmp, use set CFLAG
|
||||
clc ; LOW: +1
|
||||
uartBitbang_ReceiveByte_shiftIn:
|
||||
ror r20 ; +1
|
||||
dec r21 ; +1
|
||||
brne uartBitbang_ReceiveByte_loop ; +2, sum per loop: 8 cycles
|
||||
rcall uartBitbang_WaitForDataHigh ; wait for start of stopbit
|
||||
brcc uartBitbang_ReceiveByte_error
|
||||
mov r16, r20
|
||||
sec
|
||||
ret
|
||||
uartBitbang_ReceiveByte_error:
|
||||
clc
|
||||
ret
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
; ---------------------------------------------------------------------------
|
||||
; @routine uartBitbang_WaitForDataLow
|
||||
;
|
||||
; Wait up to 1ms for data pin to become low
|
||||
; @return CFLAG set if okay, clear otherwise
|
||||
; @clobbers R17, R22
|
||||
|
||||
uartBitbang_WaitForDataLow:
|
||||
cbi COM_DATA_DDR, COM_DATA_PIN ; set DATA port as input
|
||||
cbi COM_DATA_OUTPUT, COM_DATA_PIN ; disable internal pullup for TXD
|
||||
UART_BB_M_WAIT_FOR_PIN_LOW COM_DATA_INPUT, COM_DATA_PIN
|
||||
ret
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
; ---------------------------------------------------------------------------
|
||||
; @routine uartBitbang_WaitForDataHigh
|
||||
;
|
||||
; Wait up to 1ms for data pin to become high
|
||||
; @return CFLAG set if okay, clear otherwise
|
||||
; @clobbers R17, R22
|
||||
|
||||
uartBitbang_WaitForDataHigh:
|
||||
cbi COM_DATA_DDR, COM_DATA_PIN ; set DATA port as input
|
||||
cbi COM_DATA_OUTPUT, COM_DATA_PIN ; disable internal pullup for TXD
|
||||
UART_BB_M_WAIT_FOR_PIN_HIGH COM_DATA_INPUT, COM_DATA_PIN
|
||||
ret
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
; ---------------------------------------------------------------------------
|
||||
; @routine uartBitbang_WaitForAttnHigh
|
||||
;
|
||||
; Wait up to 1ms for data pin to become high
|
||||
; @return CFLAG set if okay, clear otherwise
|
||||
; @clobbers R17, R22
|
||||
|
||||
uartBitbang_WaitForAttnHigh:
|
||||
cbi COM_ATTN_DDR, COM_ATTN_PIN ; set ATTN port as input
|
||||
cbi COM_ATTN_OUTPUT, COM_ATTN_PIN ; disable internal pullup for ATTN
|
||||
UART_BB_M_WAIT_FOR_PIN_HIGH COM_ATTN_INPUT, COM_ATTN_PIN
|
||||
ret
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
; ---------------------------------------------------------------------------
|
||||
; @routine uartBitbang_ReceivePacketIntoBuffer
|
||||
;
|
||||
; Receive a packet into buffer pointed to by X.
|
||||
; Expects interrupts to be disabled.
|
||||
;
|
||||
; @param R16 COM address to listen to
|
||||
; @param R17 maximum value for accepted msg data (i.e. buffersize minus 3)
|
||||
; @param X buffer to receive to
|
||||
; @return CFLAG set if okay (packet received), cleared on error
|
||||
; @return R16 error code if CFLAG is cleared (COM2_ERROR_NOTFORME, COM2_ERROR_IOERROR, COM2_ERROR_DATAERROR)
|
||||
; @clobbers: r16, r17, r18, X (r19, r20, r21, r22)
|
||||
|
||||
uartBitbang_ReceivePacketIntoBuffer:
|
||||
mov r18, r17
|
||||
push r16
|
||||
; read destination address
|
||||
rcall uartBitbang_ReceiveByte ; read byte (R16, R17, R20, R21, R22)
|
||||
pop r17 ; pop from R16 to R17
|
||||
brcc uartBitbang_ReceivePacketIntoBuffer_ioError
|
||||
#ifndef COM_ACCEPT_ALL_DEST ; accept every destination address
|
||||
; compare destination address (accept "FF" and own address)
|
||||
cp r16, r17
|
||||
breq uartBitbang_ReceivePacketIntoBuffer_acceptAddr
|
||||
cpi r16, 0xff
|
||||
breq uartBitbang_ReceivePacketIntoBuffer_acceptAddr
|
||||
clr r16
|
||||
rjmp uartBitbang_ReceivePacketIntoBuffer_error ; clc/ret
|
||||
#endif
|
||||
uartBitbang_ReceivePacketIntoBuffer_acceptAddr:
|
||||
st X+, r16 ; store dest address, lock buffer
|
||||
; read msg length
|
||||
rcall uartBitbang_ReceiveByte ; read packet length (R16, R17, R20, R21, R22)
|
||||
brcc uartBitbang_ReceivePacketIntoBuffer_ioError
|
||||
st X+, r16
|
||||
cp r16, r18 ; (COM2_BUFFER_SIZE-3)
|
||||
brcc uartBitbang_ReceivePacketIntoBuffer_contentError ; packet too long
|
||||
inc r16 ; account for checksum byte
|
||||
mov r17, r16
|
||||
uartBitbang_ReceivePacketIntoBuffer_loop:
|
||||
push r17
|
||||
rcall uartBitbang_ReceiveByte ; read byte (R16, R17, R20, R21, R22)
|
||||
pop r17
|
||||
brcc uartBitbang_ReceivePacketIntoBuffer_ioError
|
||||
st X+, r16
|
||||
dec r17
|
||||
brne uartBitbang_ReceivePacketIntoBuffer_loop
|
||||
sec
|
||||
ret
|
||||
uartBitbang_ReceivePacketIntoBuffer_ioError:
|
||||
ldi r16, NET_IFACE_OFFS_ERR_IO_LOW
|
||||
rjmp uartBitbang_ReceivePacketIntoBuffer_error
|
||||
uartBitbang_ReceivePacketIntoBuffer_contentError:
|
||||
ldi r16, NET_IFACE_OFFS_ERR_CONTENT_LOW
|
||||
uartBitbang_ReceivePacketIntoBuffer_error:
|
||||
clc
|
||||
ret
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
; ---------------------------------------------------------------------------
|
||||
; @routine uartBitbang_SendPacket
|
||||
;
|
||||
; Send packet over wire, handle ATTN line.
|
||||
;
|
||||
; @param X ptr to buffer to send
|
||||
; @return CFLAGS set if okay, cleared otherwise (index of error variable in R16)
|
||||
; @return R16 index of error variable (if CFLAGS cleared)
|
||||
; @clobbers R16, R22 (R17, R21, X)
|
||||
|
||||
uartBitbang_SendPacket:
|
||||
rcall uartBitbang_AcquireBus
|
||||
brcc uartBitbang_SendPacket_lineBusyError
|
||||
|
||||
rcall uartBitbang_WaitForOneBitLength ; wait for one bit duration (R22)
|
||||
rcall uartBitbang_WaitForOneBitLength ; wait for one bit duration (R22)
|
||||
|
||||
adiw xh:xl, COM2_MSG_OFFS_MSGLEN
|
||||
ld r17, X
|
||||
sbiw xh:xl, COM2_MSG_OFFS_MSGLEN
|
||||
inc r17 ; account for dest addr
|
||||
inc r17 ; account for msglen byte
|
||||
inc r17 ; account for crc byte
|
||||
|
||||
uartBitbang_SendPacket_loop:
|
||||
ld r16, X+
|
||||
rcall uartBitbang_SendByte ; send byte (R16, R21, R22)
|
||||
brcc uartBitbang_SendPacket_releaseBusRet
|
||||
dec r17
|
||||
brne uartBitbang_SendPacket_loop
|
||||
sec
|
||||
uartBitbang_SendPacket_releaseBusRet:
|
||||
cbi COM_ATTN_DDR, COM_ATTN_PIN ; release ATTN line (by setting direction to IN)
|
||||
brcc uartBitbang_SendPacket_ioError
|
||||
; packet successfully sent
|
||||
ret
|
||||
uartBitbang_SendPacket_ioError:
|
||||
ldi r16, NET_IFACE_OFFS_ERR_COLLISIONS_LOW
|
||||
ret
|
||||
uartBitbang_SendPacket_lineBusyError:
|
||||
ldi r16, NET_IFACE_OFFS_ERR_BUSY_LOW
|
||||
ret
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
; ---------------------------------------------------------------------------
|
||||
; @routine uartBitbang_AcquireBus
|
||||
;
|
||||
; Reserve bus if free (otherwise return error)
|
||||
; Expects interrupts to be disabled.
|
||||
;
|
||||
; @return CFLAG set if okay (bus acquired), cleared on error
|
||||
; @clobbers: none
|
||||
|
||||
uartBitbang_AcquireBus:
|
||||
; check for ATTN line: busy?
|
||||
cbi COM_ATTN_DDR, COM_ATTN_PIN ; set ATTN as input
|
||||
cbi COM_ATTN_OUTPUT, COM_ATTN_PIN ; disable pullup on ATTN
|
||||
nop ; needed to sample current input
|
||||
sbis COM_ATTN_INPUT, COM_ATTN_PIN ; ATTN low?
|
||||
rjmp uartBitbang_AcquireBus_busy ; jump if it is
|
||||
sbi COM_ATTN_DDR, COM_ATTN_PIN ; set ATTN as output
|
||||
cbi COM_ATTN_OUTPUT, COM_ATTN_PIN ; set ATTN low
|
||||
sec
|
||||
ret
|
||||
uartBitbang_AcquireBus_busy:
|
||||
clc
|
||||
ret
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
; ---------------------------------------------------------------------------
|
||||
; @routine uartBitbang_WaitForOneBitLength
|
||||
;
|
||||
; wait for one bit length (minus cycles for call and ret).
|
||||
;
|
||||
; @clobbers r22
|
||||
|
||||
uartBitbang_WaitForOneBitLength:
|
||||
Utils_WaitNanoSecs COM_BIT_LENGTH, 7, r22 ; wait for one bit duration (minus RCALL/RET)
|
||||
ret
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
|
||||
10
avr/modules/uart_bitbang2/main.asm
Normal file
10
avr/modules/uart_bitbang2/main.asm
Normal file
@@ -0,0 +1,10 @@
|
||||
; ***************************************************************************
|
||||
; copyright : (C) 2025 by Martin Preuss
|
||||
; email : martin@libchipcard.de
|
||||
;
|
||||
; ***************************************************************************
|
||||
; * This file is part of the project "AqHome". *
|
||||
; * Please see toplevel file COPYING of that project for license details. *
|
||||
; ***************************************************************************
|
||||
|
||||
|
||||
Reference in New Issue
Block a user