1490 lines
49 KiB
PHP
Executable File
1490 lines
49 KiB
PHP
Executable File
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
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;***** Created: 2011-02-09 12:03 ******* Source: AT90USB1286.xml *********
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;*************************************************************************
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;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
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;*
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;* Number : AVR000
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;* File Name : "usb1286def.inc"
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;* Title : Register/Bit Definitions for the AT90USB1286
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;* Date : 2011-02-09
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;* Version : 2.35
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;* Support E-mail : avr@atmel.com
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;* Target MCU : AT90USB1286
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;*
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;* DESCRIPTION
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;* When including this file in the assembly program file, all I/O register
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;* names and I/O register bit names appearing in the data book can be used.
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;* In addition, the six registers forming the three data pointers X, Y and
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;* Z have been assigned names XL - ZH. Highest RAM address for Internal
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;* SRAM is also defined
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;*
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;* The Register names are represented by their hexadecimal address.
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;*
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;* The Register Bit names are represented by their bit number (0-7).
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;*
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;* Please observe the difference in using the bit names with instructions
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;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
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;* (skip if bit in register set/cleared). The following example illustrates
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;* this:
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;*
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;* in r16,PORTB ;read PORTB latch
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;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
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;* out PORTB,r16 ;output to PORTB
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;*
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;* in r16,TIFR ;read the Timer Interrupt Flag Register
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;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
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;* rjmp TOV0_is_set ;jump if set
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;* ... ;otherwise do something else
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;*************************************************************************
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#ifndef _USB1286DEF_INC_
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#define _USB1286DEF_INC_
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#pragma partinc 0
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; ***** SPECIFY DEVICE ***************************************************
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.device AT90USB1286
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#pragma AVRPART ADMIN PART_NAME AT90USB1286
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.equ SIGNATURE_000 = 0x1e
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.equ SIGNATURE_001 = 0x97
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.equ SIGNATURE_002 = 0x82
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#pragma AVRPART CORE CORE_VERSION V3
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; ***** I/O REGISTER DEFINITIONS *****************************************
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; NOTE:
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; Definitions marked "MEMORY MAPPED"are extended I/O ports
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; and cannot be used with IN/OUT instructions
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.equ PLLCSR = 0x29
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.equ TESTPADSTATUS = 0xfd ; MEMORY MAPPED
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.equ TESTPADPULL = 0xfe ; MEMORY MAPPED
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.equ TESTPADCTRL = 0xff ; MEMORY MAPPED
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.equ UPERRX = 0xf5 ; MEMORY MAPPED
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.equ UEINT = 0xf4 ; MEMORY MAPPED
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.equ UPINT = 0xf8 ; MEMORY MAPPED
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.equ UEBCHX = 0xf3 ; MEMORY MAPPED
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.equ UPBCHX = 0xf7 ; MEMORY MAPPED
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.equ UEBCLX = 0xf2 ; MEMORY MAPPED
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.equ UPBCLX = 0xf6 ; MEMORY MAPPED
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.equ UEDATX = 0xf1 ; MEMORY MAPPED
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.equ UPDATX = 0xaf ; MEMORY MAPPED
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.equ UEIENX = 0xf0 ; MEMORY MAPPED
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.equ UPIENX = 0xae ; MEMORY MAPPED
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.equ UESTA1X = 0xef ; MEMORY MAPPED
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.equ UPCFG2X = 0xad ; MEMORY MAPPED
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.equ UESTA0X = 0xee ; MEMORY MAPPED
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.equ UPSTAX = 0xac ; MEMORY MAPPED
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.equ UECFG1X = 0xed ; MEMORY MAPPED
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.equ UPCFG1X = 0xab ; MEMORY MAPPED
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.equ UECFG0X = 0xec ; MEMORY MAPPED
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.equ UPCFG0X = 0xaa ; MEMORY MAPPED
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.equ UECONX = 0xeb ; MEMORY MAPPED
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.equ UPCONX = 0xa9 ; MEMORY MAPPED
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.equ UERST = 0xea ; MEMORY MAPPED
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.equ UPRST = 0xa8 ; MEMORY MAPPED
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.equ UENUM = 0xe9 ; MEMORY MAPPED
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.equ UPNUM = 0xa7 ; MEMORY MAPPED
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.equ UEINTX = 0xe8 ; MEMORY MAPPED
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.equ UPINTX = 0xa6 ; MEMORY MAPPED
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.equ UDTST = 0xe7 ; MEMORY MAPPED
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.equ UPINRQX = 0xa5 ; MEMORY MAPPED
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.equ UDMFN = 0xe6 ; MEMORY MAPPED
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.equ UHFLEN = 0xa4 ; MEMORY MAPPED
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.equ UDFNUMH = 0xe5 ; MEMORY MAPPED
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.equ UHFNUMH = 0xa3 ; MEMORY MAPPED
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.equ UDFNUML = 0xe4 ; MEMORY MAPPED
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.equ UHFNUML = 0xa2 ; MEMORY MAPPED
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.equ UDADDR = 0xe3 ; MEMORY MAPPED
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.equ UHADDR = 0xa1 ; MEMORY MAPPED
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.equ UDIEN = 0xe2 ; MEMORY MAPPED
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.equ UHIEN = 0xa0 ; MEMORY MAPPED
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.equ UDINT = 0xe1 ; MEMORY MAPPED
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.equ UHINT = 0x9f ; MEMORY MAPPED
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.equ UDCON = 0xe0 ; MEMORY MAPPED
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.equ UHCON = 0x9e ; MEMORY MAPPED
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.equ OTGINT = 0xdf ; MEMORY MAPPED
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.equ OTGIEN = 0xde ; MEMORY MAPPED
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.equ OTGCON = 0xdd ; MEMORY MAPPED
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.equ OTGTCON = 0xf9 ; MEMORY MAPPED
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.equ USBINT = 0xda ; MEMORY MAPPED
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.equ USBSTA = 0xd9 ; MEMORY MAPPED
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.equ USBCON = 0xd8 ; MEMORY MAPPED
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.equ UHWCON = 0xd7 ; MEMORY MAPPED
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.equ UDR1 = 0xce ; MEMORY MAPPED
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.equ UBRR1L = 0xcc ; MEMORY MAPPED
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.equ UBRR1H = 0xcd ; MEMORY MAPPED
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.equ UCSR1C = 0xca ; MEMORY MAPPED
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.equ UCSR1B = 0xc9 ; MEMORY MAPPED
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.equ UCSR1A = 0xc8 ; MEMORY MAPPED
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.equ TWAMR = 0xbd ; MEMORY MAPPED
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.equ TWCR = 0xbc ; MEMORY MAPPED
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.equ TWDR = 0xbb ; MEMORY MAPPED
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.equ TWAR = 0xba ; MEMORY MAPPED
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.equ TWSR = 0xb9 ; MEMORY MAPPED
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.equ TWBR = 0xb8 ; MEMORY MAPPED
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.equ ASSR = 0xb6 ; MEMORY MAPPED
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.equ OCR2B = 0xb4 ; MEMORY MAPPED
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.equ OCR2A = 0xb3 ; MEMORY MAPPED
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.equ TCNT2 = 0xb2 ; MEMORY MAPPED
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.equ TCCR2B = 0xb1 ; MEMORY MAPPED
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.equ TCCR2A = 0xb0 ; MEMORY MAPPED
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.equ OCR3CL = 0x9c ; MEMORY MAPPED
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.equ OCR3CH = 0x9d ; MEMORY MAPPED
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.equ OCR3BL = 0x9a ; MEMORY MAPPED
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.equ OCR3BH = 0x9b ; MEMORY MAPPED
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.equ OCR3AL = 0x98 ; MEMORY MAPPED
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.equ OCR3AH = 0x99 ; MEMORY MAPPED
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.equ ICR3L = 0x96 ; MEMORY MAPPED
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.equ ICR3H = 0x97 ; MEMORY MAPPED
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.equ TCNT3L = 0x94 ; MEMORY MAPPED
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.equ TCNT3H = 0x95 ; MEMORY MAPPED
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.equ TCCR3C = 0x92 ; MEMORY MAPPED
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.equ TCCR3B = 0x91 ; MEMORY MAPPED
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.equ TCCR3A = 0x90 ; MEMORY MAPPED
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.equ OCR1CL = 0x8c ; MEMORY MAPPED
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.equ OCR1CH = 0x8d ; MEMORY MAPPED
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.equ OCR1BL = 0x8a ; MEMORY MAPPED
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.equ OCR1BH = 0x8b ; MEMORY MAPPED
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.equ OCR1AL = 0x88 ; MEMORY MAPPED
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.equ OCR1AH = 0x89 ; MEMORY MAPPED
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.equ ICR1L = 0x86 ; MEMORY MAPPED
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.equ ICR1H = 0x87 ; MEMORY MAPPED
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.equ TCNT1L = 0x84 ; MEMORY MAPPED
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.equ TCNT1H = 0x85 ; MEMORY MAPPED
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.equ TCCR1C = 0x82 ; MEMORY MAPPED
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.equ TCCR1B = 0x81 ; MEMORY MAPPED
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.equ TCCR1A = 0x80 ; MEMORY MAPPED
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.equ DIDR1 = 0x7f ; MEMORY MAPPED
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.equ DIDR0 = 0x7e ; MEMORY MAPPED
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.equ DIDR2 = 0x7d ; MEMORY MAPPED
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.equ ADMUX = 0x7c ; MEMORY MAPPED
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.equ ADCSRB = 0x7b ; MEMORY MAPPED
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.equ ADCSRA = 0x7a ; MEMORY MAPPED
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.equ ADCH = 0x79 ; MEMORY MAPPED
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.equ ADCL = 0x78 ; MEMORY MAPPED
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.equ XMCRB = 0x75 ; MEMORY MAPPED
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.equ XMCRA = 0x74 ; MEMORY MAPPED
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.equ TIMSK5 = 0x73 ; MEMORY MAPPED
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.equ TIMSK4 = 0x72 ; MEMORY MAPPED
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.equ TIMSK3 = 0x71 ; MEMORY MAPPED
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.equ TIMSK2 = 0x70 ; MEMORY MAPPED
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.equ TIMSK1 = 0x6f ; MEMORY MAPPED
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.equ TIMSK0 = 0x6e ; MEMORY MAPPED
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.equ PCMSK2 = 0x6d ; MEMORY MAPPED
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.equ PCMSK1 = 0x6c ; MEMORY MAPPED
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.equ PCMSK0 = 0x6b ; MEMORY MAPPED
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.equ EICRB = 0x6a ; MEMORY MAPPED
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.equ EICRA = 0x69 ; MEMORY MAPPED
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.equ PCICR = 0x68 ; MEMORY MAPPED
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.equ OSCCAL = 0x66 ; MEMORY MAPPED
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.equ PRR1 = 0x65 ; MEMORY MAPPED
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.equ PRR0 = 0x64 ; MEMORY MAPPED
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.equ CLKPR = 0x61 ; MEMORY MAPPED
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.equ WDTCSR = 0x60 ; MEMORY MAPPED
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.equ SREG = 0x3f
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.equ SPL = 0x3d
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.equ SPH = 0x3e
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.equ EIND = 0x3c
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.equ RAMPZ = 0x3b
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.equ SPMCSR = 0x37
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.equ MCUCR = 0x35
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.equ MCUSR = 0x34
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.equ SMCR = 0x33
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.equ OCDR = 0x31
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.equ ACSR = 0x30
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.equ SPDR = 0x2e
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.equ SPSR = 0x2d
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.equ SPCR = 0x2c
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.equ GPIOR2 = 0x2b
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.equ GPIOR1 = 0x2a
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.equ OCR0B = 0x28
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.equ OCR0A = 0x27
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.equ TCNT0 = 0x26
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.equ TCCR0B = 0x25
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.equ TCCR0A = 0x24
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.equ GTCCR = 0x23
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.equ EEARH = 0x22
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.equ EEARL = 0x21
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.equ EEDR = 0x20
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.equ EECR = 0x1f
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.equ GPIOR0 = 0x1e
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.equ EIMSK = 0x1d
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.equ EIFR = 0x1c
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.equ PCIFR = 0x1b
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.equ TIFR5 = 0x1a
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.equ TIFR4 = 0x19
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.equ TIFR3 = 0x18
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.equ TIFR2 = 0x17
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.equ TIFR1 = 0x16
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.equ TIFR0 = 0x15
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.equ PORTF = 0x11
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.equ DDRF = 0x10
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.equ PINF = 0x0f
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.equ PORTE = 0x0e
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.equ DDRE = 0x0d
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.equ PINE = 0x0c
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.equ PORTD = 0x0b
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.equ DDRD = 0x0a
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.equ PIND = 0x09
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.equ PORTC = 0x08
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.equ DDRC = 0x07
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.equ PINC = 0x06
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.equ PORTB = 0x05
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.equ DDRB = 0x04
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.equ PINB = 0x03
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.equ PORTA = 0x02
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.equ DDRA = 0x01
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.equ PINA = 0x00
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; ***** BIT DEFINITIONS **************************************************
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; ***** WATCHDOG *********************
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; WDTCSR - Watchdog Timer Control Register
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.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
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.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
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.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
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.equ WDE = 3 ; Watch Dog Enable
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.equ WDCE = 4 ; Watchdog Change Enable
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.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3
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.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable
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.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag
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; ***** PORTA ************************
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; PORTA - Port A Data Register
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.equ PORTA0 = 0 ; Port A Data Register bit 0
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.equ PA0 = 0 ; For compatibility
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.equ PORTA1 = 1 ; Port A Data Register bit 1
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.equ PA1 = 1 ; For compatibility
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.equ PORTA2 = 2 ; Port A Data Register bit 2
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.equ PA2 = 2 ; For compatibility
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.equ PORTA3 = 3 ; Port A Data Register bit 3
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.equ PA3 = 3 ; For compatibility
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.equ PORTA4 = 4 ; Port A Data Register bit 4
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.equ PA4 = 4 ; For compatibility
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.equ PORTA5 = 5 ; Port A Data Register bit 5
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.equ PA5 = 5 ; For compatibility
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.equ PORTA6 = 6 ; Port A Data Register bit 6
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.equ PA6 = 6 ; For compatibility
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.equ PORTA7 = 7 ; Port A Data Register bit 7
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.equ PA7 = 7 ; For compatibility
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; DDRA - Port A Data Direction Register
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.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
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.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
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.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
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.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3
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.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4
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.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5
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.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6
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.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7
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; PINA - Port A Input Pins
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.equ PINA0 = 0 ; Input Pins, Port A bit 0
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.equ PINA1 = 1 ; Input Pins, Port A bit 1
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.equ PINA2 = 2 ; Input Pins, Port A bit 2
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.equ PINA3 = 3 ; Input Pins, Port A bit 3
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.equ PINA4 = 4 ; Input Pins, Port A bit 4
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.equ PINA5 = 5 ; Input Pins, Port A bit 5
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.equ PINA6 = 6 ; Input Pins, Port A bit 6
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.equ PINA7 = 7 ; Input Pins, Port A bit 7
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; ***** PORTB ************************
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; PORTB - Port B Data Register
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.equ PORTB0 = 0 ; Port B Data Register bit 0
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.equ PB0 = 0 ; For compatibility
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.equ PORTB1 = 1 ; Port B Data Register bit 1
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.equ PB1 = 1 ; For compatibility
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.equ PORTB2 = 2 ; Port B Data Register bit 2
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.equ PB2 = 2 ; For compatibility
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.equ PORTB3 = 3 ; Port B Data Register bit 3
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.equ PB3 = 3 ; For compatibility
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.equ PORTB4 = 4 ; Port B Data Register bit 4
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.equ PB4 = 4 ; For compatibility
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.equ PORTB5 = 5 ; Port B Data Register bit 5
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.equ PB5 = 5 ; For compatibility
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.equ PORTB6 = 6 ; Port B Data Register bit 6
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.equ PB6 = 6 ; For compatibility
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.equ PORTB7 = 7 ; Port B Data Register bit 7
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.equ PB7 = 7 ; For compatibility
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; DDRB - Port B Data Direction Register
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.equ DDB0 = 0 ; Port B Data Direction Register bit 0
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.equ DDB1 = 1 ; Port B Data Direction Register bit 1
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.equ DDB2 = 2 ; Port B Data Direction Register bit 2
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.equ DDB3 = 3 ; Port B Data Direction Register bit 3
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.equ DDB4 = 4 ; Port B Data Direction Register bit 4
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.equ DDB5 = 5 ; Port B Data Direction Register bit 5
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.equ DDB6 = 6 ; Port B Data Direction Register bit 6
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.equ DDB7 = 7 ; Port B Data Direction Register bit 7
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; PINB - Port B Input Pins
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.equ PINB0 = 0 ; Port B Input Pins bit 0
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.equ PINB1 = 1 ; Port B Input Pins bit 1
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.equ PINB2 = 2 ; Port B Input Pins bit 2
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.equ PINB3 = 3 ; Port B Input Pins bit 3
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.equ PINB4 = 4 ; Port B Input Pins bit 4
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.equ PINB5 = 5 ; Port B Input Pins bit 5
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.equ PINB6 = 6 ; Port B Input Pins bit 6
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.equ PINB7 = 7 ; Port B Input Pins bit 7
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; ***** PORTC ************************
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; PORTC - Port C Data Register
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.equ PORTC0 = 0 ; Port C Data Register bit 0
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.equ PC0 = 0 ; For compatibility
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.equ PORTC1 = 1 ; Port C Data Register bit 1
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.equ PC1 = 1 ; For compatibility
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.equ PORTC2 = 2 ; Port C Data Register bit 2
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.equ PC2 = 2 ; For compatibility
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.equ PORTC3 = 3 ; Port C Data Register bit 3
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.equ PC3 = 3 ; For compatibility
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.equ PORTC4 = 4 ; Port C Data Register bit 4
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.equ PC4 = 4 ; For compatibility
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.equ PORTC5 = 5 ; Port C Data Register bit 5
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.equ PC5 = 5 ; For compatibility
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.equ PORTC6 = 6 ; Port C Data Register bit 6
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.equ PC6 = 6 ; For compatibility
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.equ PORTC7 = 7 ; Port C Data Register bit 7
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.equ PC7 = 7 ; For compatibility
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; DDRC - Port C Data Direction Register
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.equ DDC0 = 0 ; Port C Data Direction Register bit 0
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.equ DDC1 = 1 ; Port C Data Direction Register bit 1
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.equ DDC2 = 2 ; Port C Data Direction Register bit 2
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.equ DDC3 = 3 ; Port C Data Direction Register bit 3
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.equ DDC4 = 4 ; Port C Data Direction Register bit 4
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.equ DDC5 = 5 ; Port C Data Direction Register bit 5
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.equ DDC6 = 6 ; Port C Data Direction Register bit 6
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.equ DDC7 = 7 ; Port C Data Direction Register bit 7
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; PINC - Port C Input Pins
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.equ PINC0 = 0 ; Port C Input Pins bit 0
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.equ PINC1 = 1 ; Port C Input Pins bit 1
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.equ PINC2 = 2 ; Port C Input Pins bit 2
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.equ PINC3 = 3 ; Port C Input Pins bit 3
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.equ PINC4 = 4 ; Port C Input Pins bit 4
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.equ PINC5 = 5 ; Port C Input Pins bit 5
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.equ PINC6 = 6 ; Port C Input Pins bit 6
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.equ PINC7 = 7 ; Port C Input Pins bit 7
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; ***** PORTD ************************
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; PORTD - Port D Data Register
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.equ PORTD0 = 0 ; Port D Data Register bit 0
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.equ PD0 = 0 ; For compatibility
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.equ PORTD1 = 1 ; Port D Data Register bit 1
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.equ PD1 = 1 ; For compatibility
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.equ PORTD2 = 2 ; Port D Data Register bit 2
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.equ PD2 = 2 ; For compatibility
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.equ PORTD3 = 3 ; Port D Data Register bit 3
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.equ PD3 = 3 ; For compatibility
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.equ PORTD4 = 4 ; Port D Data Register bit 4
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.equ PD4 = 4 ; For compatibility
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.equ PORTD5 = 5 ; Port D Data Register bit 5
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.equ PD5 = 5 ; For compatibility
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.equ PORTD6 = 6 ; Port D Data Register bit 6
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.equ PD6 = 6 ; For compatibility
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.equ PORTD7 = 7 ; Port D Data Register bit 7
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.equ PD7 = 7 ; For compatibility
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; DDRD - Port D Data Direction Register
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.equ DDD0 = 0 ; Port D Data Direction Register bit 0
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.equ DDD1 = 1 ; Port D Data Direction Register bit 1
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.equ DDD2 = 2 ; Port D Data Direction Register bit 2
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.equ DDD3 = 3 ; Port D Data Direction Register bit 3
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.equ DDD4 = 4 ; Port D Data Direction Register bit 4
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.equ DDD5 = 5 ; Port D Data Direction Register bit 5
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.equ DDD6 = 6 ; Port D Data Direction Register bit 6
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.equ DDD7 = 7 ; Port D Data Direction Register bit 7
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; PIND - Port D Input Pins
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.equ PIND0 = 0 ; Port D Input Pins bit 0
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.equ PIND1 = 1 ; Port D Input Pins bit 1
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.equ PIND2 = 2 ; Port D Input Pins bit 2
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.equ PIND3 = 3 ; Port D Input Pins bit 3
|
|
.equ PIND4 = 4 ; Port D Input Pins bit 4
|
|
.equ PIND5 = 5 ; Port D Input Pins bit 5
|
|
.equ PIND6 = 6 ; Port D Input Pins bit 6
|
|
.equ PIND7 = 7 ; Port D Input Pins bit 7
|
|
|
|
|
|
; ***** PORTE ************************
|
|
; PORTE - Data Register, Port E
|
|
.equ PORTE0 = 0 ;
|
|
.equ PE0 = 0 ; For compatibility
|
|
.equ PORTE1 = 1 ;
|
|
.equ PE1 = 1 ; For compatibility
|
|
.equ PORTE2 = 2 ;
|
|
.equ PE2 = 2 ; For compatibility
|
|
.equ PORTE3 = 3 ;
|
|
.equ PE3 = 3 ; For compatibility
|
|
.equ PORTE4 = 4 ;
|
|
.equ PE4 = 4 ; For compatibility
|
|
.equ PORTE5 = 5 ;
|
|
.equ PE5 = 5 ; For compatibility
|
|
.equ PORTE6 = 6 ;
|
|
.equ PE6 = 6 ; For compatibility
|
|
.equ PORTE7 = 7 ;
|
|
.equ PE7 = 7 ; For compatibility
|
|
|
|
; DDRE - Data Direction Register, Port E
|
|
.equ DDE0 = 0 ;
|
|
.equ DDE1 = 1 ;
|
|
.equ DDE2 = 2 ;
|
|
.equ DDE3 = 3 ;
|
|
.equ DDE4 = 4 ;
|
|
.equ DDE5 = 5 ;
|
|
.equ DDE6 = 6 ;
|
|
.equ DDE7 = 7 ;
|
|
|
|
; PINE - Input Pins, Port E
|
|
.equ PINE0 = 0 ;
|
|
.equ PINE1 = 1 ;
|
|
.equ PINE2 = 2 ;
|
|
.equ PINE3 = 3 ;
|
|
.equ PINE4 = 4 ;
|
|
.equ PINE5 = 5 ;
|
|
.equ PINE6 = 6 ;
|
|
.equ PINE7 = 7 ;
|
|
|
|
|
|
; ***** PORTF ************************
|
|
; PORTF - Data Register, Port F
|
|
.equ PORTF0 = 0 ;
|
|
.equ PF0 = 0 ; For compatibility
|
|
.equ PORTF1 = 1 ;
|
|
.equ PF1 = 1 ; For compatibility
|
|
.equ PORTF2 = 2 ;
|
|
.equ PF2 = 2 ; For compatibility
|
|
.equ PORTF3 = 3 ;
|
|
.equ PF3 = 3 ; For compatibility
|
|
.equ PORTF4 = 4 ;
|
|
.equ PF4 = 4 ; For compatibility
|
|
.equ PORTF5 = 5 ;
|
|
.equ PF5 = 5 ; For compatibility
|
|
.equ PORTF6 = 6 ;
|
|
.equ PF6 = 6 ; For compatibility
|
|
.equ PORTF7 = 7 ;
|
|
.equ PF7 = 7 ; For compatibility
|
|
|
|
; DDRF - Data Direction Register, Port F
|
|
.equ DDF0 = 0 ;
|
|
.equ DDF1 = 1 ;
|
|
.equ DDF2 = 2 ;
|
|
.equ DDF3 = 3 ;
|
|
.equ DDF4 = 4 ;
|
|
.equ DDF5 = 5 ;
|
|
.equ DDF6 = 6 ;
|
|
.equ DDF7 = 7 ;
|
|
|
|
; PINF - Input Pins, Port F
|
|
.equ PINF0 = 0 ;
|
|
.equ PINF1 = 1 ;
|
|
.equ PINF2 = 2 ;
|
|
.equ PINF3 = 3 ;
|
|
.equ PINF4 = 4 ;
|
|
.equ PINF5 = 5 ;
|
|
.equ PINF6 = 6 ;
|
|
.equ PINF7 = 7 ;
|
|
|
|
|
|
; ***** CPU **************************
|
|
; SREG - Status Register
|
|
.equ SREG_C = 0 ; Carry Flag
|
|
.equ SREG_Z = 1 ; Zero Flag
|
|
.equ SREG_N = 2 ; Negative Flag
|
|
.equ SREG_V = 3 ; Two's Complement Overflow Flag
|
|
.equ SREG_S = 4 ; Sign Bit
|
|
.equ SREG_H = 5 ; Half Carry Flag
|
|
.equ SREG_T = 6 ; Bit Copy Storage
|
|
.equ SREG_I = 7 ; Global Interrupt Enable
|
|
|
|
; MCUCR - MCU Control Register
|
|
.equ IVCE = 0 ; Interrupt Vector Change Enable
|
|
.equ IVSEL = 1 ; Interrupt Vector Select
|
|
.equ PUD = 4 ; Pull-up disable
|
|
.equ JTD = 7 ; JTAG Interface Disable
|
|
|
|
; MCUSR - MCU Status Register
|
|
.equ PORF = 0 ; Power-on reset flag
|
|
.equ EXTRF = 1 ; External Reset Flag
|
|
.equ BORF = 2 ; Brown-out Reset Flag
|
|
.equ WDRF = 3 ; Watchdog Reset Flag
|
|
.equ JTRF = 4 ; JTAG Reset Flag
|
|
|
|
; XMCRA - External Memory Control Register A
|
|
.equ SRW00 = 0 ; Wait state select bit lower page
|
|
.equ SRW01 = 1 ; Wait state select bit lower page
|
|
.equ SRW10 = 2 ; Wait state select bit upper page
|
|
.equ SRW11 = 3 ; Wait state select bit upper page
|
|
.equ SRL0 = 4 ; Wait state page limit
|
|
.equ SRL1 = 5 ; Wait state page limit
|
|
.equ SRL2 = 6 ; Wait state page limit
|
|
.equ SRE = 7 ; External SRAM Enable
|
|
|
|
; XMCRB - External Memory Control Register B
|
|
.equ XMM0 = 0 ; External Memory High Mask
|
|
.equ XMM1 = 1 ; External Memory High Mask
|
|
.equ XMM2 = 2 ; External Memory High Mask
|
|
.equ XMBK = 7 ; External Memory Bus Keeper Enable
|
|
|
|
; OSCCAL - Oscillator Calibration Value
|
|
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0
|
|
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1
|
|
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2
|
|
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3
|
|
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4
|
|
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5
|
|
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6
|
|
.equ CAL7 = 7 ; Oscillator Calibration Value Bit7
|
|
|
|
; CLKPR -
|
|
.equ CLKPS0 = 0 ;
|
|
.equ CLKPS1 = 1 ;
|
|
.equ CLKPS2 = 2 ;
|
|
.equ CLKPS3 = 3 ;
|
|
.equ CLKPCE = 7 ;
|
|
|
|
; SMCR - Sleep Mode Control Register
|
|
.equ SE = 0 ; Sleep Enable
|
|
.equ SM0 = 1 ; Sleep Mode Select bit 0
|
|
.equ SM1 = 2 ; Sleep Mode Select bit 1
|
|
.equ SM2 = 3 ; Sleep Mode Select bit 2
|
|
|
|
; RAMPZ - RAM Page Z Select Register
|
|
.equ RAMPZ0 = 0 ; RAM Page Z Select Register Bit 0
|
|
|
|
; EIND - Extended Indirect Register
|
|
.equ EIND0 = 0 ; Bit 0
|
|
|
|
; GPIOR2 - General Purpose IO Register 2
|
|
.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0
|
|
.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1
|
|
.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2
|
|
.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3
|
|
.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4
|
|
.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5
|
|
.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6
|
|
.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7
|
|
|
|
; GPIOR1 - General Purpose IO Register 1
|
|
.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0
|
|
.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1
|
|
.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2
|
|
.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3
|
|
.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4
|
|
.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5
|
|
.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6
|
|
.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7
|
|
|
|
; GPIOR0 - General Purpose IO Register 0
|
|
.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0
|
|
.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1
|
|
.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2
|
|
.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3
|
|
.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4
|
|
.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5
|
|
.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6
|
|
.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7
|
|
|
|
; PRR1 - Power Reduction Register1
|
|
.equ PRUSART1 = 0 ; Power Reduction USART1
|
|
.equ PRTIM3 = 3 ; Power Reduction Timer/Counter3
|
|
.equ PRUSB = 7 ; Power Reduction USB
|
|
|
|
; PRR0 - Power Reduction Register0
|
|
.equ PRADC = 0 ; Power Reduction ADC
|
|
.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface
|
|
.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1
|
|
.equ PRTIM0 = 5 ; Power Reduction Timer/Counter0
|
|
.equ PRTIM2 = 6 ; Power Reduction Timer/Counter2
|
|
.equ PRTWI = 7 ; Power Reduction TWI
|
|
|
|
|
|
; ***** TWI **************************
|
|
; TWAMR - TWI (Slave) Address Mask Register
|
|
.equ TWAM0 = 1 ;
|
|
.equ TWAMR0 = TWAM0 ; For compatibility
|
|
.equ TWAM1 = 2 ;
|
|
.equ TWAMR1 = TWAM1 ; For compatibility
|
|
.equ TWAM2 = 3 ;
|
|
.equ TWAMR2 = TWAM2 ; For compatibility
|
|
.equ TWAM3 = 4 ;
|
|
.equ TWAMR3 = TWAM3 ; For compatibility
|
|
.equ TWAM4 = 5 ;
|
|
.equ TWAMR4 = TWAM4 ; For compatibility
|
|
.equ TWAM5 = 6 ;
|
|
.equ TWAMR5 = TWAM5 ; For compatibility
|
|
.equ TWAM6 = 7 ;
|
|
.equ TWAMR6 = TWAM6 ; For compatibility
|
|
|
|
; TWBR - TWI Bit Rate register
|
|
.equ TWBR0 = 0 ;
|
|
.equ TWBR1 = 1 ;
|
|
.equ TWBR2 = 2 ;
|
|
.equ TWBR3 = 3 ;
|
|
.equ TWBR4 = 4 ;
|
|
.equ TWBR5 = 5 ;
|
|
.equ TWBR6 = 6 ;
|
|
.equ TWBR7 = 7 ;
|
|
|
|
; TWCR - TWI Control Register
|
|
.equ TWIE = 0 ; TWI Interrupt Enable
|
|
.equ TWEN = 2 ; TWI Enable Bit
|
|
.equ TWWC = 3 ; TWI Write Collition Flag
|
|
.equ TWSTO = 4 ; TWI Stop Condition Bit
|
|
.equ TWSTA = 5 ; TWI Start Condition Bit
|
|
.equ TWEA = 6 ; TWI Enable Acknowledge Bit
|
|
.equ TWINT = 7 ; TWI Interrupt Flag
|
|
|
|
; TWSR - TWI Status Register
|
|
.equ TWPS0 = 0 ; TWI Prescaler
|
|
.equ TWPS1 = 1 ; TWI Prescaler
|
|
.equ TWS3 = 3 ; TWI Status
|
|
.equ TWS4 = 4 ; TWI Status
|
|
.equ TWS5 = 5 ; TWI Status
|
|
.equ TWS6 = 6 ; TWI Status
|
|
.equ TWS7 = 7 ; TWI Status
|
|
|
|
; TWDR - TWI Data register
|
|
.equ TWD0 = 0 ; TWI Data Register Bit 0
|
|
.equ TWD1 = 1 ; TWI Data Register Bit 1
|
|
.equ TWD2 = 2 ; TWI Data Register Bit 2
|
|
.equ TWD3 = 3 ; TWI Data Register Bit 3
|
|
.equ TWD4 = 4 ; TWI Data Register Bit 4
|
|
.equ TWD5 = 5 ; TWI Data Register Bit 5
|
|
.equ TWD6 = 6 ; TWI Data Register Bit 6
|
|
.equ TWD7 = 7 ; TWI Data Register Bit 7
|
|
|
|
; TWAR - TWI (Slave) Address register
|
|
.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit
|
|
.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0
|
|
.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1
|
|
.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2
|
|
.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3
|
|
.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4
|
|
.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5
|
|
.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6
|
|
|
|
|
|
; ***** SPI **************************
|
|
; SPDR - SPI Data Register
|
|
.equ SPDR0 = 0 ; SPI Data Register bit 0
|
|
.equ SPDR1 = 1 ; SPI Data Register bit 1
|
|
.equ SPDR2 = 2 ; SPI Data Register bit 2
|
|
.equ SPDR3 = 3 ; SPI Data Register bit 3
|
|
.equ SPDR4 = 4 ; SPI Data Register bit 4
|
|
.equ SPDR5 = 5 ; SPI Data Register bit 5
|
|
.equ SPDR6 = 6 ; SPI Data Register bit 6
|
|
.equ SPDR7 = 7 ; SPI Data Register bit 7
|
|
|
|
; SPSR - SPI Status Register
|
|
.equ SPI2X = 0 ; Double SPI Speed Bit
|
|
.equ WCOL = 6 ; Write Collision Flag
|
|
.equ SPIF = 7 ; SPI Interrupt Flag
|
|
|
|
; SPCR - SPI Control Register
|
|
.equ SPR0 = 0 ; SPI Clock Rate Select 0
|
|
.equ SPR1 = 1 ; SPI Clock Rate Select 1
|
|
.equ CPHA = 2 ; Clock Phase
|
|
.equ CPOL = 3 ; Clock polarity
|
|
.equ MSTR = 4 ; Master/Slave Select
|
|
.equ DORD = 5 ; Data Order
|
|
.equ SPE = 6 ; SPI Enable
|
|
.equ SPIE = 7 ; SPI Interrupt Enable
|
|
|
|
|
|
; ***** USART1 ***********************
|
|
; UDR1 - USART I/O Data Register
|
|
.equ UDR1_0 = 0 ; USART I/O Data Register bit 0
|
|
.equ UDR1_1 = 1 ; USART I/O Data Register bit 1
|
|
.equ UDR1_2 = 2 ; USART I/O Data Register bit 2
|
|
.equ UDR1_3 = 3 ; USART I/O Data Register bit 3
|
|
.equ UDR1_4 = 4 ; USART I/O Data Register bit 4
|
|
.equ UDR1_5 = 5 ; USART I/O Data Register bit 5
|
|
.equ UDR1_6 = 6 ; USART I/O Data Register bit 6
|
|
.equ UDR1_7 = 7 ; USART I/O Data Register bit 7
|
|
|
|
; UCSR1A - USART Control and Status Register A
|
|
.equ MPCM1 = 0 ; Multi-processor Communication Mode
|
|
.equ U2X1 = 1 ; Double the USART transmission speed
|
|
.equ UPE1 = 2 ; Parity Error
|
|
.equ DOR1 = 3 ; Data overRun
|
|
.equ FE1 = 4 ; Framing Error
|
|
.equ UDRE1 = 5 ; USART Data Register Empty
|
|
.equ TXC1 = 6 ; USART Transmitt Complete
|
|
.equ RXC1 = 7 ; USART Receive Complete
|
|
|
|
; UCSR1B - USART Control and Status Register B
|
|
.equ TXB81 = 0 ; Transmit Data Bit 8
|
|
.equ RXB81 = 1 ; Receive Data Bit 8
|
|
.equ UCSZ12 = 2 ; Character Size
|
|
.equ TXEN1 = 3 ; Transmitter Enable
|
|
.equ RXEN1 = 4 ; Receiver Enable
|
|
.equ UDRIE1 = 5 ; USART Data register Empty Interrupt Enable
|
|
.equ TXCIE1 = 6 ; TX Complete Interrupt Enable
|
|
.equ RXCIE1 = 7 ; RX Complete Interrupt Enable
|
|
|
|
; UCSR1C - USART Control and Status Register C
|
|
.equ UCPOL1 = 0 ; Clock Polarity
|
|
.equ UCSZ10 = 1 ; Character Size
|
|
.equ UCPHA1 = UCSZ10 ; For compatibility
|
|
.equ UCSZ11 = 2 ; Character Size
|
|
.equ UDORD1 = UCSZ11 ; For compatibility
|
|
.equ USBS1 = 3 ; Stop Bit Select
|
|
.equ UPM10 = 4 ; Parity Mode Bit 0
|
|
.equ UPM11 = 5 ; Parity Mode Bit 1
|
|
.equ UMSEL10 = 6 ; USART Mode Select
|
|
.equ UMSEL11 = 7 ; USART Mode Select
|
|
|
|
; UBRR1H - USART Baud Rate Register High Byte
|
|
.equ UBRR_8 = 0 ; USART Baud Rate Register bit 8
|
|
.equ UBRR_9 = 1 ; USART Baud Rate Register bit 9
|
|
.equ UBRR_10 = 2 ; USART Baud Rate Register bit 10
|
|
.equ UBRR_11 = 3 ; USART Baud Rate Register bit 11
|
|
|
|
; UBRR1L - USART Baud Rate Register Low Byte
|
|
.equ UBRR_0 = 0 ; USART Baud Rate Register bit 0
|
|
.equ UBRR_1 = 1 ; USART Baud Rate Register bit 1
|
|
.equ UBRR_2 = 2 ; USART Baud Rate Register bit 2
|
|
.equ UBRR_3 = 3 ; USART Baud Rate Register bit 3
|
|
.equ UBRR_4 = 4 ; USART Baud Rate Register bit 4
|
|
.equ UBRR_5 = 5 ; USART Baud Rate Register bit 5
|
|
.equ UBRR_6 = 6 ; USART Baud Rate Register bit 6
|
|
.equ UBRR_7 = 7 ; USART Baud Rate Register bit 7
|
|
|
|
|
|
; ***** USB_DEVICE *******************
|
|
; UDCON -
|
|
.equ DETACH = 0 ;
|
|
.equ RMWKUP = 1 ;
|
|
.equ LSM = 2 ;
|
|
|
|
; UDINT -
|
|
.equ SUSPI = 0 ;
|
|
.equ SOFI = 2 ;
|
|
.equ EORSTI = 3 ;
|
|
.equ WAKEUPI = 4 ;
|
|
.equ EORSMI = 5 ;
|
|
.equ UPRSMI = 6 ;
|
|
|
|
; UDIEN -
|
|
.equ SUSPE = 0 ;
|
|
.equ SOFE = 2 ;
|
|
.equ EORSTE = 3 ;
|
|
.equ WAKEUPE = 4 ;
|
|
.equ EORSME = 5 ;
|
|
.equ UPRSME = 6 ;
|
|
|
|
; UDADDR -
|
|
.equ UADD0 = 0 ;
|
|
.equ UADD1 = 1 ;
|
|
.equ UADD2 = 2 ;
|
|
.equ UADD3 = 3 ;
|
|
.equ UADD4 = 4 ;
|
|
.equ UADD5 = 5 ;
|
|
.equ UADD6 = 6 ;
|
|
.equ ADDEN = 7 ;
|
|
|
|
; UDFNUML -
|
|
.equ UDFNUML_0 = 0 ;
|
|
.equ UDFNUML_1 = 1 ;
|
|
.equ UDFNUML_2 = 2 ;
|
|
.equ UDFNUML_3 = 3 ;
|
|
.equ UDFNUML_4 = 4 ;
|
|
.equ UDFNUML_5 = 5 ;
|
|
.equ UDFNUML_6 = 6 ;
|
|
.equ UDFNUML_7 = 7 ;
|
|
|
|
; UDFNUMH -
|
|
.equ UDFNUMH_0 = 0 ;
|
|
.equ UDFNUMH_1 = 1 ;
|
|
.equ UDFNUMH_2 = 2 ;
|
|
|
|
; UDMFN -
|
|
.equ FNCERR = 4 ;
|
|
|
|
; UEINTX -
|
|
.equ TXINI = 0 ;
|
|
.equ STALLEDI = 1 ;
|
|
.equ RXOUTI = 2 ;
|
|
.equ RXSTPI = 3 ;
|
|
.equ NAKOUTI = 4 ;
|
|
.equ RWAL = 5 ;
|
|
.equ NAKINI = 6 ;
|
|
.equ FIFOCON = 7 ;
|
|
|
|
; UENUM -
|
|
.equ UENUM_0 = 0 ;
|
|
.equ UENUM_1 = 1 ;
|
|
.equ UENUM_2 = 2 ;
|
|
|
|
; UERST -
|
|
.equ EPRST0 = 0 ;
|
|
.equ EPRST1 = 1 ;
|
|
.equ EPRST2 = 2 ;
|
|
.equ EPRST3 = 3 ;
|
|
.equ EPRST4 = 4 ;
|
|
.equ EPRST5 = 5 ;
|
|
.equ EPRST6 = 6 ;
|
|
|
|
; UECONX -
|
|
.equ EPEN = 0 ;
|
|
.equ RSTDT = 3 ;
|
|
.equ STALLRQC = 4 ;
|
|
.equ STALLRQ = 5 ;
|
|
|
|
; UECFG0X -
|
|
.equ EPDIR = 0 ;
|
|
.equ EPTYPE0 = 6 ;
|
|
.equ EPTYPE1 = 7 ;
|
|
|
|
; UECFG1X -
|
|
.equ ALLOC = 1 ;
|
|
.equ EPBK0 = 2 ;
|
|
.equ EPBK1 = 3 ;
|
|
.equ EPSIZE0 = 4 ;
|
|
.equ EPSIZE1 = 5 ;
|
|
.equ EPSIZE2 = 6 ;
|
|
|
|
; UESTA0X -
|
|
.equ NBUSYBK0 = 0 ;
|
|
.equ NBUSYBK1 = 1 ;
|
|
.equ DTSEQ0 = 2 ;
|
|
.equ DTSEQ1 = 3 ;
|
|
.equ UNDERFI = 5 ;
|
|
.equ OVERFI = 6 ;
|
|
.equ CFGOK = 7 ;
|
|
|
|
; UESTA1X -
|
|
.equ CURRBK0 = 0 ;
|
|
.equ CURRBK1 = 1 ;
|
|
.equ CTRLDIR = 2 ;
|
|
|
|
; UEIENX -
|
|
.equ TXINE = 0 ;
|
|
.equ STALLEDE = 1 ;
|
|
.equ RXOUTE = 2 ;
|
|
.equ RXSTPE = 3 ;
|
|
.equ NAKOUTE = 4 ;
|
|
.equ NAKINE = 6 ;
|
|
.equ FLERRE = 7 ;
|
|
|
|
; UEDATX -
|
|
.equ UEDATX_0 = 0 ;
|
|
.equ UEDATX_1 = 1 ;
|
|
.equ UEDATX_2 = 2 ;
|
|
.equ UEDATX_3 = 3 ;
|
|
.equ UEDATX_4 = 4 ;
|
|
.equ UEDATX_5 = 5 ;
|
|
.equ UEDATX_6 = 6 ;
|
|
.equ UEDATX_7 = 7 ;
|
|
|
|
; UEBCLX -
|
|
.equ UEBCLX_0 = 0 ;
|
|
.equ UEBCLX_1 = 1 ;
|
|
.equ UEBCLX_2 = 2 ;
|
|
.equ UEBCLX_3 = 3 ;
|
|
.equ UEBCLX_4 = 4 ;
|
|
.equ UEBCLX_5 = 5 ;
|
|
.equ UEBCLX_6 = 6 ;
|
|
.equ UEBCLX_7 = 7 ;
|
|
|
|
; UEBCHX -
|
|
.equ UEBCHX_0 = 0 ;
|
|
.equ UEBCHX_1 = 1 ;
|
|
.equ UEBCHX_2 = 2 ;
|
|
|
|
; UEINT -
|
|
.equ EPINT0 = 0 ;
|
|
.equ EPINT1 = 1 ;
|
|
.equ EPINT2 = 2 ;
|
|
.equ EPINT3 = 3 ;
|
|
.equ EPINT4 = 4 ;
|
|
.equ EPINT5 = 5 ;
|
|
.equ EPINT6 = 6 ;
|
|
|
|
|
|
; ***** BOOT_LOAD ********************
|
|
; SPMCSR - Store Program Memory Control Register
|
|
.equ SPMEN = 0 ; Store Program Memory Enable
|
|
.equ PGERS = 1 ; Page Erase
|
|
.equ PGWRT = 2 ; Page Write
|
|
.equ BLBSET = 3 ; Boot Lock Bit Set
|
|
.equ RWWSRE = 4 ; Read While Write section read enable
|
|
.equ SIGRD = 5 ; Signature Row Read
|
|
.equ RWWSB = 6 ; Read While Write Section Busy
|
|
.equ SPMIE = 7 ; SPM Interrupt Enable
|
|
|
|
|
|
; ***** EEPROM ***********************
|
|
; EEARH - EEPROM Address Register Low Byte
|
|
.equ EEAR8 = 0 ; EEPROM Read/Write Access Bit 8
|
|
.equ EEAR9 = 1 ; EEPROM Read/Write Access Bit 9
|
|
.equ EEAR10 = 2 ; EEPROM Read/Write Access Bit 10
|
|
.equ EEAR11 = 3 ; EEPROM Read/Write Access Bit 11
|
|
|
|
; EEARL - EEPROM Address Register Low Byte
|
|
.equ EEAR0 = 0 ; EEPROM Read/Write Access Bit 0
|
|
.equ EEAR1 = 1 ; EEPROM Read/Write Access Bit 1
|
|
.equ EEAR2 = 2 ; EEPROM Read/Write Access Bit 2
|
|
.equ EEAR3 = 3 ; EEPROM Read/Write Access Bit 3
|
|
.equ EEAR4 = 4 ; EEPROM Read/Write Access Bit 4
|
|
.equ EEAR5 = 5 ; EEPROM Read/Write Access Bit 5
|
|
.equ EEAR6 = 6 ; EEPROM Read/Write Access Bit 6
|
|
.equ EEAR7 = 7 ; EEPROM Read/Write Access Bit 7
|
|
|
|
; EEDR - EEPROM Data Register
|
|
.equ EEDR0 = 0 ; EEPROM Data Register bit 0
|
|
.equ EEDR1 = 1 ; EEPROM Data Register bit 1
|
|
.equ EEDR2 = 2 ; EEPROM Data Register bit 2
|
|
.equ EEDR3 = 3 ; EEPROM Data Register bit 3
|
|
.equ EEDR4 = 4 ; EEPROM Data Register bit 4
|
|
.equ EEDR5 = 5 ; EEPROM Data Register bit 5
|
|
.equ EEDR6 = 6 ; EEPROM Data Register bit 6
|
|
.equ EEDR7 = 7 ; EEPROM Data Register bit 7
|
|
|
|
; EECR - EEPROM Control Register
|
|
.equ EERE = 0 ; EEPROM Read Enable
|
|
.equ EEPE = 1 ; EEPROM Write Enable
|
|
.equ EEMPE = 2 ; EEPROM Master Write Enable
|
|
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable
|
|
.equ EEPM0 = 4 ; EEPROM Programming Mode Bit 0
|
|
.equ EEPM1 = 5 ; EEPROM Programming Mode Bit 1
|
|
|
|
|
|
; ***** TIMER_COUNTER_0 **************
|
|
; TIMSK0 - Timer/Counter0 Interrupt Mask Register
|
|
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
|
|
.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable
|
|
.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable
|
|
|
|
; TIFR0 - Timer/Counter0 Interrupt Flag register
|
|
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
|
|
.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0A
|
|
.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B
|
|
|
|
; TCCR0A - Timer/Counter Control Register A
|
|
.equ WGM00 = 0 ; Waveform Generation Mode
|
|
.equ WGM01 = 1 ; Waveform Generation Mode
|
|
.equ COM0B0 = 4 ; Compare Output Mode, Fast PWm
|
|
.equ COM0B1 = 5 ; Compare Output Mode, Fast PWm
|
|
.equ COM0A0 = 6 ; Compare Output Mode, Phase Correct PWM Mode
|
|
.equ COM0A1 = 7 ; Compare Output Mode, Phase Correct PWM Mode
|
|
|
|
; TCCR0B - Timer/Counter Control Register B
|
|
.equ CS00 = 0 ; Clock Select
|
|
.equ CS01 = 1 ; Clock Select
|
|
.equ CS02 = 2 ; Clock Select
|
|
.equ WGM02 = 3 ;
|
|
.equ FOC0B = 6 ; Force Output Compare B
|
|
.equ FOC0A = 7 ; Force Output Compare A
|
|
|
|
; TCNT0 - Timer/Counter0
|
|
.equ TCNT0_0 = 0 ;
|
|
.equ TCNT0_1 = 1 ;
|
|
.equ TCNT0_2 = 2 ;
|
|
.equ TCNT0_3 = 3 ;
|
|
.equ TCNT0_4 = 4 ;
|
|
.equ TCNT0_5 = 5 ;
|
|
.equ TCNT0_6 = 6 ;
|
|
.equ TCNT0_7 = 7 ;
|
|
|
|
; OCR0A - Timer/Counter0 Output Compare Register
|
|
.equ OCR0A_0 = 0 ;
|
|
.equ OCR0A_1 = 1 ;
|
|
.equ OCR0A_2 = 2 ;
|
|
.equ OCR0A_3 = 3 ;
|
|
.equ OCR0A_4 = 4 ;
|
|
.equ OCR0A_5 = 5 ;
|
|
.equ OCR0A_6 = 6 ;
|
|
.equ OCR0A_7 = 7 ;
|
|
|
|
; OCR0B - Timer/Counter0 Output Compare Register
|
|
.equ OCR0B_0 = 0 ;
|
|
.equ OCR0B_1 = 1 ;
|
|
.equ OCR0B_2 = 2 ;
|
|
.equ OCR0B_3 = 3 ;
|
|
.equ OCR0B_4 = 4 ;
|
|
.equ OCR0B_5 = 5 ;
|
|
.equ OCR0B_6 = 6 ;
|
|
.equ OCR0B_7 = 7 ;
|
|
|
|
; GTCCR - General Timer/Counter Control Register
|
|
.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0
|
|
.equ PSR10 = PSRSYNC ; For compatibility
|
|
.equ TSM = 7 ; Timer/Counter Synchronization Mode
|
|
|
|
|
|
; ***** TIMER_COUNTER_2 **************
|
|
; TIMSK2 - Timer/Counter Interrupt Mask register
|
|
.equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable
|
|
.equ TOIE2A = TOIE2 ; For compatibility
|
|
.equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match A Interrupt Enable
|
|
.equ OCIE2B = 2 ; Timer/Counter2 Output Compare Match B Interrupt Enable
|
|
|
|
; TIFR2 - Timer/Counter Interrupt Flag Register
|
|
.equ TOV2 = 0 ; Timer/Counter2 Overflow Flag
|
|
.equ OCF2A = 1 ; Output Compare Flag 2A
|
|
.equ OCF2B = 2 ; Output Compare Flag 2B
|
|
|
|
; TCCR2A - Timer/Counter2 Control Register A
|
|
.equ WGM20 = 0 ; Waveform Genration Mode
|
|
.equ WGM21 = 1 ; Waveform Genration Mode
|
|
.equ COM2B0 = 4 ; Compare Output Mode bit 0
|
|
.equ COM2B1 = 5 ; Compare Output Mode bit 1
|
|
.equ COM2A0 = 6 ; Compare Output Mode bit 1
|
|
.equ COM2A1 = 7 ; Compare Output Mode bit 1
|
|
|
|
; TCCR2B - Timer/Counter2 Control Register B
|
|
.equ CS20 = 0 ; Clock Select bit 0
|
|
.equ CS21 = 1 ; Clock Select bit 1
|
|
.equ CS22 = 2 ; Clock Select bit 2
|
|
.equ WGM22 = 3 ; Waveform Generation Mode
|
|
.equ FOC2B = 6 ; Force Output Compare B
|
|
.equ FOC2A = 7 ; Force Output Compare A
|
|
|
|
; TCNT2 - Timer/Counter2
|
|
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0
|
|
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1
|
|
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2
|
|
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3
|
|
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4
|
|
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5
|
|
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6
|
|
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7
|
|
|
|
; OCR2A - Timer/Counter2 Output Compare Register A
|
|
.equ OCR2A_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0
|
|
.equ OCR2A_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1
|
|
.equ OCR2A_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2
|
|
.equ OCR2A_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3
|
|
.equ OCR2A_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4
|
|
.equ OCR2A_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5
|
|
.equ OCR2A_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6
|
|
.equ OCR2A_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7
|
|
|
|
; OCR2B - Timer/Counter2 Output Compare Register B
|
|
.equ OCR2B_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0
|
|
.equ OCR2B_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1
|
|
.equ OCR2B_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2
|
|
.equ OCR2B_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3
|
|
.equ OCR2B_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4
|
|
.equ OCR2B_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5
|
|
.equ OCR2B_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6
|
|
.equ OCR2B_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7
|
|
|
|
; ASSR - Asynchronous Status Register
|
|
.equ TCR2BUB = 0 ; Timer/Counter Control Register2 Update Busy
|
|
.equ TCR2AUB = 1 ; Timer/Counter Control Register2 Update Busy
|
|
.equ OCR2BUB = 2 ; Output Compare Register 2 Update Busy
|
|
.equ OCR2AUB = 3 ; Output Compare Register2 Update Busy
|
|
.equ TCN2UB = 4 ; Timer/Counter2 Update Busy
|
|
.equ AS2 = 5 ; Asynchronous Timer/Counter2
|
|
.equ EXCLK = 6 ; Enable External Clock Input
|
|
|
|
; GTCCR - General Timer Counter Control register
|
|
.equ PSRASY = 1 ; Prescaler Reset Timer/Counter2
|
|
.equ PSR2 = PSRASY ; For compatibility
|
|
;.equ TSM = 7 ; Timer/Counter Synchronization Mode
|
|
|
|
|
|
; ***** TIMER_COUNTER_3 **************
|
|
; TIMSK3 - Timer/Counter3 Interrupt Mask Register
|
|
.equ TOIE3 = 0 ; Timer/Counter3 Overflow Interrupt Enable
|
|
.equ OCIE3A = 1 ; Timer/Counter3 Output Compare A Match Interrupt Enable
|
|
.equ OCIE3B = 2 ; Timer/Counter3 Output Compare B Match Interrupt Enable
|
|
.equ OCIE3C = 3 ; Timer/Counter3 Output Compare C Match Interrupt Enable
|
|
.equ ICIE3 = 5 ; Timer/Counter3 Input Capture Interrupt Enable
|
|
|
|
; TIFR3 - Timer/Counter3 Interrupt Flag register
|
|
.equ TOV3 = 0 ; Timer/Counter3 Overflow Flag
|
|
.equ OCF3A = 1 ; Output Compare Flag 3A
|
|
.equ OCF3B = 2 ; Output Compare Flag 3B
|
|
.equ OCF3C = 3 ; Output Compare Flag 3C
|
|
.equ ICF3 = 5 ; Input Capture Flag 3
|
|
|
|
; TCCR3A - Timer/Counter3 Control Register A
|
|
.equ WGM30 = 0 ; Waveform Generation Mode
|
|
.equ WGM31 = 1 ; Waveform Generation Mode
|
|
.equ COM3C0 = 2 ; Compare Output Mode 3C, bit 0
|
|
.equ COM3C1 = 3 ; Compare Output Mode 3C, bit 1
|
|
.equ COM3B0 = 4 ; Compare Output Mode 3B, bit 0
|
|
.equ COM3B1 = 5 ; Compare Output Mode 3B, bit 1
|
|
.equ COM3A0 = 6 ; Compare Output Mode 3A, bit 0
|
|
.equ COM3A1 = 7 ; Compare Output Mode 1A, bit 1
|
|
|
|
; TCCR3B - Timer/Counter3 Control Register B
|
|
.equ CS30 = 0 ; Prescaler source of Timer/Counter 3
|
|
.equ CS31 = 1 ; Prescaler source of Timer/Counter 3
|
|
.equ CS32 = 2 ; Prescaler source of Timer/Counter 3
|
|
.equ WGM32 = 3 ; Waveform Generation Mode
|
|
.equ WGM33 = 4 ; Waveform Generation Mode
|
|
.equ ICES3 = 6 ; Input Capture 3 Edge Select
|
|
.equ ICNC3 = 7 ; Input Capture 3 Noise Canceler
|
|
|
|
; TCCR3C - Timer/Counter 3 Control Register C
|
|
.equ FOC3C = 5 ; Force Output Compare 3C
|
|
.equ FOC3B = 6 ; Force Output Compare 3B
|
|
.equ FOC3A = 7 ; Force Output Compare 3A
|
|
|
|
|
|
; ***** TIMER_COUNTER_1 **************
|
|
; TIMSK1 - Timer/Counter1 Interrupt Mask Register
|
|
.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable
|
|
.equ OCIE1A = 1 ; Timer/Counter1 Output Compare A Match Interrupt Enable
|
|
.equ OCIE1B = 2 ; Timer/Counter1 Output Compare B Match Interrupt Enable
|
|
.equ OCIE1C = 3 ; Timer/Counter1 Output Compare C Match Interrupt Enable
|
|
.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable
|
|
|
|
; TIFR1 - Timer/Counter1 Interrupt Flag register
|
|
.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag
|
|
.equ OCF1A = 1 ; Output Compare Flag 1A
|
|
.equ OCF1B = 2 ; Output Compare Flag 1B
|
|
.equ OCF1C = 3 ; Output Compare Flag 1C
|
|
.equ ICF1 = 5 ; Input Capture Flag 1
|
|
|
|
; TCCR1A - Timer/Counter1 Control Register A
|
|
.equ WGM10 = 0 ; Waveform Generation Mode
|
|
.equ WGM11 = 1 ; Waveform Generation Mode
|
|
.equ COM1C0 = 2 ; Compare Output Mode 1C, bit 0
|
|
.equ COM1C1 = 3 ; Compare Output Mode 1C, bit 1
|
|
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0
|
|
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
|
|
.equ COM1A0 = 6 ; Compare Output Mode 1A, bit 0
|
|
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
|
|
|
|
; TCCR1B - Timer/Counter1 Control Register B
|
|
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1
|
|
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1
|
|
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1
|
|
.equ WGM12 = 3 ; Waveform Generation Mode
|
|
.equ WGM13 = 4 ; Waveform Generation Mode
|
|
.equ ICES1 = 6 ; Input Capture 1 Edge Select
|
|
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
|
|
|
|
; TCCR1C - Timer/Counter 1 Control Register C
|
|
.equ FOC1C = 5 ; Force Output Compare 1C
|
|
.equ FOC1B = 6 ; Force Output Compare 1B
|
|
.equ FOC1A = 7 ; Force Output Compare 1A
|
|
|
|
|
|
; ***** JTAG *************************
|
|
; OCDR - On-Chip Debug Related Register in I/O Memory
|
|
.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0
|
|
.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1
|
|
.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2
|
|
.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3
|
|
.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4
|
|
.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5
|
|
.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6
|
|
.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7
|
|
.equ IDRD = OCDR7 ; For compatibility
|
|
|
|
; MCUCR - MCU Control Register
|
|
;.equ JTD = 7 ; JTAG Interface Disable
|
|
|
|
; MCUSR - MCU Status Register
|
|
;.equ JTRF = 4 ; JTAG Reset Flag
|
|
|
|
|
|
; ***** EXTERNAL_INTERRUPT ***********
|
|
; EICRA - External Interrupt Control Register A
|
|
.equ ISC00 = 0 ; External Interrupt Sense Control Bit
|
|
.equ ISC01 = 1 ; External Interrupt Sense Control Bit
|
|
.equ ISC10 = 2 ; External Interrupt Sense Control Bit
|
|
.equ ISC11 = 3 ; External Interrupt Sense Control Bit
|
|
.equ ISC20 = 4 ; External Interrupt Sense Control Bit
|
|
.equ ISC21 = 5 ; External Interrupt Sense Control Bit
|
|
.equ ISC30 = 6 ; External Interrupt Sense Control Bit
|
|
.equ ISC31 = 7 ; External Interrupt Sense Control Bit
|
|
|
|
; EICRB - External Interrupt Control Register B
|
|
.equ ISC40 = 0 ; External Interrupt 7-4 Sense Control Bit
|
|
.equ ISC41 = 1 ; External Interrupt 7-4 Sense Control Bit
|
|
.equ ISC50 = 2 ; External Interrupt 7-4 Sense Control Bit
|
|
.equ ISC51 = 3 ; External Interrupt 7-4 Sense Control Bit
|
|
.equ ISC60 = 4 ; External Interrupt 7-4 Sense Control Bit
|
|
.equ ISC61 = 5 ; External Interrupt 7-4 Sense Control Bit
|
|
.equ ISC70 = 6 ; External Interrupt 7-4 Sense Control Bit
|
|
.equ ISC71 = 7 ; External Interrupt 7-4 Sense Control Bit
|
|
|
|
; EIMSK - External Interrupt Mask Register
|
|
.equ INT0 = 0 ; External Interrupt Request 0 Enable
|
|
.equ INT1 = 1 ; External Interrupt Request 1 Enable
|
|
.equ INT2 = 2 ; External Interrupt Request 2 Enable
|
|
.equ INT3 = 3 ; External Interrupt Request 3 Enable
|
|
.equ INT4 = 4 ; External Interrupt Request 4 Enable
|
|
.equ INT5 = 5 ; External Interrupt Request 5 Enable
|
|
.equ INT6 = 6 ; External Interrupt Request 6 Enable
|
|
.equ INT7 = 7 ; External Interrupt Request 7 Enable
|
|
|
|
; EIFR - External Interrupt Flag Register
|
|
.equ INTF0 = 0 ; External Interrupt Flag 0
|
|
.equ INTF1 = 1 ; External Interrupt Flag 1
|
|
.equ INTF2 = 2 ; External Interrupt Flag 2
|
|
.equ INTF3 = 3 ; External Interrupt Flag 3
|
|
.equ INTF4 = 4 ; External Interrupt Flag 4
|
|
.equ INTF5 = 5 ; External Interrupt Flag 5
|
|
.equ INTF6 = 6 ; External Interrupt Flag 6
|
|
.equ INTF7 = 7 ; External Interrupt Flag 7
|
|
|
|
; PCICR - Pin Change Interrupt Control Register
|
|
.equ PCIE0 = 0 ; Pin Change Interrupt Enable 0
|
|
|
|
; PCIFR - Pin Change Interrupt Flag Register
|
|
.equ PCIF0 = 0 ; Pin Change Interrupt Flag 0
|
|
|
|
; PCMSK0 - Pin Change Mask Register 0
|
|
.equ PCINT0 = 0 ; Pin Change Enable Mask 0
|
|
.equ PCINT1 = 1 ; Pin Change Enable Mask 1
|
|
.equ PCINT2 = 2 ; Pin Change Enable Mask 2
|
|
.equ PCINT3 = 3 ; Pin Change Enable Mask 3
|
|
.equ PCINT4 = 4 ; Pin Change Enable Mask 4
|
|
.equ PCINT5 = 5 ; Pin Change Enable Mask 5
|
|
.equ PCINT6 = 6 ; Pin Change Enable Mask 6
|
|
.equ PCINT7 = 7 ; Pin Change Enable Mask 7
|
|
|
|
|
|
; ***** AD_CONVERTER *****************
|
|
; ADMUX - The ADC multiplexer Selection Register
|
|
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
|
|
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
|
|
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits
|
|
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits
|
|
.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits
|
|
.equ ADLAR = 5 ; Left Adjust Result
|
|
.equ REFS0 = 6 ; Reference Selection Bit 0
|
|
.equ REFS1 = 7 ; Reference Selection Bit 1
|
|
|
|
; ADCSRA - The ADC Control and Status register
|
|
.equ ADPS0 = 0 ; ADC Prescaler Select Bits
|
|
.equ ADPS1 = 1 ; ADC Prescaler Select Bits
|
|
.equ ADPS2 = 2 ; ADC Prescaler Select Bits
|
|
.equ ADIE = 3 ; ADC Interrupt Enable
|
|
.equ ADIF = 4 ; ADC Interrupt Flag
|
|
.equ ADATE = 5 ; ADC Auto Trigger Enable
|
|
.equ ADSC = 6 ; ADC Start Conversion
|
|
.equ ADEN = 7 ; ADC Enable
|
|
|
|
; ADCH - ADC Data Register High Byte
|
|
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0
|
|
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1
|
|
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2
|
|
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3
|
|
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4
|
|
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5
|
|
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6
|
|
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7
|
|
|
|
; ADCL - ADC Data Register Low Byte
|
|
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0
|
|
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1
|
|
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2
|
|
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3
|
|
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4
|
|
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5
|
|
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6
|
|
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7
|
|
|
|
; ADCSRB - ADC Control and Status Register B
|
|
.equ ADTS0 = 0 ; ADC Auto Trigger Source 0
|
|
.equ ADTS1 = 1 ; ADC Auto Trigger Source 1
|
|
.equ ADTS2 = 2 ; ADC Auto Trigger Source 2
|
|
.equ ADHSM = 7 ; ADC High Speed Mode
|
|
|
|
; DIDR0 - Digital Input Disable Register 1
|
|
.equ ADC0D = 0 ; ADC0 Digital input Disable
|
|
.equ ADC1D = 1 ; ADC1 Digital input Disable
|
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.equ ADC2D = 2 ; ADC2 Digital input Disable
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.equ ADC3D = 3 ; ADC3 Digital input Disable
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.equ ADC4D = 4 ; ADC4 Digital input Disable
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.equ ADC5D = 5 ; ADC5 Digital input Disable
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.equ ADC6D = 6 ; ADC6 Digital input Disable
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.equ ADC7D = 7 ; ADC7 Digital input Disable
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; ***** ANALOG_COMPARATOR ************
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; ADCSRB - ADC Control and Status Register B
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.equ ACME = 6 ; Analog Comparator Multiplexer Enable
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; ACSR - Analog Comparator Control And Status Register
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.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
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.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
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.equ ACIC = 2 ; Analog Comparator Input Capture Enable
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.equ ACIE = 3 ; Analog Comparator Interrupt Enable
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.equ ACI = 4 ; Analog Comparator Interrupt Flag
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.equ ACO = 5 ; Analog Compare Output
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.equ ACBG = 6 ; Analog Comparator Bandgap Select
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.equ ACD = 7 ; Analog Comparator Disable
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; DIDR1 -
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.equ AIN0D = 0 ; AIN0 Digital Input Disable
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.equ AIN1D = 1 ; AIN1 Digital Input Disable
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; ***** PLL **************************
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; PLLCSR - PLL Status and Control register
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.equ PLOCK = 0 ; PLL Lock Status Bit
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.equ PLLE = 1 ; PLL Enable Bit
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.equ PLLP0 = 2 ; PLL prescaler Bit 0
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.equ PLLP1 = 3 ; PLL prescaler Bit 1
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.equ PLLP2 = 4 ; PLL prescaler Bit 2
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; ***** USB_GLOBAL *******************
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; UHWCON - USB Hardware Configuration Register
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.equ UVREGE = 0 ;
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.equ UVCONE = 4 ;
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.equ UIDE = 6 ;
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.equ UIMOD = 7 ;
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; USBCON - USB General Control Register
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.equ VBUSTE = 0 ;
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.equ IDTE = 1 ;
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.equ OTGPADE = 4 ;
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.equ FRZCLK = 5 ;
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.equ HOST = 6 ;
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.equ USBE = 7 ;
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; USBSTA -
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.equ VBUS = 0 ;
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.equ ID = 1 ;
|
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.equ SPEED = 3 ;
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|
|
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; USBINT -
|
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.equ VBUSTI = 0 ;
|
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.equ IDTI = 1 ;
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|
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|
|
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; ***** LOCKSBITS ********************************************************
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.equ LB1 = 0 ; Lock bit
|
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.equ LB2 = 1 ; Lock bit
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.equ BLB01 = 2 ; Boot Lock bit
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.equ BLB02 = 3 ; Boot Lock bit
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.equ BLB11 = 4 ; Boot lock bit
|
|
.equ BLB12 = 5 ; Boot lock bit
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|
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|
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; ***** FUSES ************************************************************
|
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; LOW fuse bits
|
|
.equ CKSEL0 = 0 ; Select Clock Source
|
|
.equ CKSEL1 = 1 ; Select Clock Source
|
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.equ CKSEL2 = 2 ; Select Clock Source
|
|
.equ CKSEL3 = 3 ; Select Clock Source
|
|
.equ SUT0 = 4 ; Select start-up time
|
|
.equ SUT1 = 5 ; Select start-up time
|
|
.equ CKOUT = 6 ; Oscillator options
|
|
.equ CKDIV8 = 7 ; Divide clock by 8
|
|
|
|
; HIGH fuse bits
|
|
.equ BOOTRST = 0 ; Select Reset Vector
|
|
.equ BOOTSZ0 = 1 ; Select Boot Size
|
|
.equ BOOTSZ1 = 2 ; Select Boot Size
|
|
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase
|
|
.equ WDTON = 4 ; Watchdog timer always on
|
|
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading
|
|
.equ JTAGEN = 6 ; Enable JTAG
|
|
.equ OCDEN = 7 ; Enable OCD
|
|
|
|
; EXTENDED fuse bits
|
|
.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level
|
|
.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level
|
|
.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level
|
|
.equ HWBE = 3 ; Hardware Boot Enable
|
|
|
|
|
|
|
|
; ***** CPU REGISTER DEFINITIONS *****************************************
|
|
.def XH = r27
|
|
.def XL = r26
|
|
.def YH = r29
|
|
.def YL = r28
|
|
.def ZH = r31
|
|
.def ZL = r30
|
|
|
|
|
|
|
|
; ***** DATA MEMORY DECLARATIONS *****************************************
|
|
.equ FLASHEND = 0xffff ; Note: Word address
|
|
.equ IOEND = 0x00ff
|
|
.equ SRAM_START = 0x0100
|
|
.equ SRAM_SIZE = 8192
|
|
.equ RAMEND = 0x20ff
|
|
.equ XRAMEND = 0xffff
|
|
.equ E2END = 0x0fff
|
|
.equ EEPROMEND = 0x0fff
|
|
.equ EEADRBITS = 12
|
|
#pragma AVRPART MEMORY PROG_FLASH 131072
|
|
#pragma AVRPART MEMORY EEPROM 4096
|
|
#pragma AVRPART MEMORY INT_SRAM SIZE 8192
|
|
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100
|
|
|
|
|
|
|
|
; ***** BOOTLOADER DECLARATIONS ******************************************
|
|
.equ NRWW_START_ADDR = 0xf000
|
|
.equ NRWW_STOP_ADDR = 0xffff
|
|
.equ RWW_START_ADDR = 0x0
|
|
.equ RWW_STOP_ADDR = 0xefff
|
|
.equ PAGESIZE = 128
|
|
.equ FIRSTBOOTSTART = 0xfe00
|
|
.equ SECONDBOOTSTART = 0xfc00
|
|
.equ THIRDBOOTSTART = 0xf800
|
|
.equ FOURTHBOOTSTART = 0xf000
|
|
.equ SMALLBOOTSTART = FIRSTBOOTSTART
|
|
.equ LARGEBOOTSTART = FOURTHBOOTSTART
|
|
|
|
|
|
|
|
; ***** INTERRUPT VECTORS ************************************************
|
|
.equ INT0addr = 0x0002 ; External Interrupt Request 0
|
|
.equ INT1addr = 0x0004 ; External Interrupt Request 1
|
|
.equ INT2addr = 0x0006 ; External Interrupt Request 2
|
|
.equ INT3addr = 0x0008 ; External Interrupt Request 3
|
|
.equ INT4addr = 0x000a ; External Interrupt Request 4
|
|
.equ INT5addr = 0x000c ; External Interrupt Request 5
|
|
.equ INT6addr = 0x000e ; External Interrupt Request 6
|
|
.equ INT7addr = 0x0010 ; External Interrupt Request 7
|
|
.equ PCI0addr = 0x0012 ; Pin Change Interrupt Request 0
|
|
.equ USB_GENaddr = 0x0014 ; USB General Interrupt Request
|
|
.equ USB_COMaddr = 0x0016 ; USB Endpoint/Pipe Interrupt Communication Request
|
|
.equ WDTaddr = 0x0018 ; Watchdog Time-out Interrupt
|
|
.equ OC2Aaddr = 0x001a ; Timer/Counter2 Compare Match A
|
|
.equ OC2Baddr = 0x001c ; Timer/Counter2 Compare Match B
|
|
.equ OVF2addr = 0x001e ; Timer/Counter2 Overflow
|
|
.equ ICP1addr = 0x0020 ; Timer/Counter1 Capture Event
|
|
.equ OC1Aaddr = 0x0022 ; Timer/Counter1 Compare Match A
|
|
.equ OC1Baddr = 0x0024 ; Timer/Counter1 Compare Match B
|
|
.equ OC1Caddr = 0x0026 ; Timer/Counter1 Compare Match C
|
|
.equ OVF1addr = 0x0028 ; Timer/Counter1 Overflow
|
|
.equ OC0Aaddr = 0x002a ; Timer/Counter0 Compare Match A
|
|
.equ OC0Baddr = 0x002c ; Timer/Counter0 Compare Match B
|
|
.equ OVF0addr = 0x002e ; Timer/Counter0 Overflow
|
|
.equ SPIaddr = 0x0030 ; SPI Serial Transfer Complete
|
|
.equ URXC1addr = 0x0032 ; USART1, Rx Complete
|
|
.equ UDRE1addr = 0x0034 ; USART1 Data register Empty
|
|
.equ UTXC1addr = 0x0036 ; USART1, Tx Complete
|
|
.equ ACIaddr = 0x0038 ; Analog Comparator
|
|
.equ ADCCaddr = 0x003a ; ADC Conversion Complete
|
|
.equ ERDYaddr = 0x003c ; EEPROM Ready
|
|
.equ ICP3addr = 0x003e ; Timer/Counter3 Capture Event
|
|
.equ OC3Aaddr = 0x0040 ; Timer/Counter3 Compare Match A
|
|
.equ OC3Baddr = 0x0042 ; Timer/Counter3 Compare Match B
|
|
.equ OC3Caddr = 0x0044 ; Timer/Counter3 Compare Match C
|
|
.equ OVF3addr = 0x0046 ; Timer/Counter3 Overflow
|
|
.equ TWIaddr = 0x0048 ; 2-wire Serial Interface
|
|
.equ SPMRaddr = 0x004a ; Store Program Memory Read
|
|
|
|
.equ INT_VECTORS_SIZE = 76 ; size in words
|
|
|
|
#endif /* _USB1286DEF_INC_ */
|
|
|
|
; ***** END OF FILE ******************************************************
|