10e4aa8f85
UBRRH and UCSRC share the same io register location, bit URSEL needs to be set in order to access UCSRC!!
501 lines
13 KiB
NASM
501 lines
13 KiB
NASM
; ***************************************************************************
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; copyright : (C) 2025 by Martin Preuss
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; email : martin@libchipcard.de
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;
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; ***************************************************************************
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; * This file is part of the project "AqHome". *
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; * Please see toplevel file COPYING of that project for license details. *
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; ***************************************************************************
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; ***************************************************************************
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; code
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.cseg
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; ---------------------------------------------------------------------------
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; @routine ioRawInit
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; Send a message
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;
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; @clobbers r16, r17
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ioRawInit:
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; set baudrate
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.if clock == 8000000
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ldi r16, 25 ; (19.2Kb/s at 8MHz)
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ldi r17, 0
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.endif
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.if clock == 1000000
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ldi r16, 3 ; (19.2Kb/s at 1MHz)
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ldi r17, 0
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.endif
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M_IO_WRITE UART_REG_UBRRH, r17
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M_IO_WRITE UART_REG_UBRRL, r16
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; set character format (asynchronous USART, 8-bit, one stop bit, no parity)
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.ifdef URSEL
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ldi r16, (1<<URSEL) | (1<<UART_BIT_USBS) | (3<<UART_BIT_UCSZ0)
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.else
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ldi r16, (1<<UART_BIT_USBS)|(3<<UART_BIT_UCSZ0)
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.endif
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; ldi r16, (1<<UART_BIT_UCSZ0) | (1<<UART_BIT_UCSZ1)
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M_IO_WRITE UART_REG_UCSRC, r16
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cbi COM_ATTN_DDR, COM_ATTN_PIN ; set ATTN port as input
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.ifdef COM_ATTN_PUE
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lds r16, COM_ATTN_PUE
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cbr r16, COM_ATTN_PIN ; disable pullup on ATTN
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sts COM_ATTN_PUE, r16
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.else
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cbi COM_ATTN_OUTPUT, COM_ATTN_PIN ; disable internal pullup for ATTN
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.endif
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ret
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;@end
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; ---------------------------------------------------------------------------
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; @routine ioRawSendMsg
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; Send a message
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;
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; @clobbers r16, r17, X
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ioRawSendMsg:
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ldi xl, LOW(flashSendBuffer)
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ldi xh, HIGH(flashSendBuffer)
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rcall ioRawSendMsgWithAttn
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brcc ioRawSendMsg
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine ioRawSendMsgWithAttn
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;
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; @param X buffer to send
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; @return CFLAG: set if okay (packet sent), cleared on error
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; @clobbers r16, r17 (X)
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ioRawSendMsgWithAttn:
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ioRawSendMsgWithAttn_loop:
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ldi r16, 0xff ; expect ATTN high
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ldi r17, 10
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rcall ioWaitForAttnState100ms ; wait for up to 1s
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brcs ioRawSendMsgWithAttn_attnHigh
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ret
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ioRawSendMsgWithAttn_attnHigh:
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rcall ioRawAcquireBus ; (none)
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brcc ioRawSendMsgWithAttn_loop
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rcall ioRawWaitForOneBitLength ; wait for one bit duration (R22)
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rcall ioRawWaitForOneBitLength ; wait for one bit duration (R22)
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rcall ioRawSendMsgHandleTransceiver ; (r16, r17, X)
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cbi COM_ATTN_DDR, COM_ATTN_PIN ; release ATTN line (by setting direction to IN)
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine ioRawSendMsgHandleTransceiver
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; Enable transceiver, send packet, disable transceiver.
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;
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; @param X buffer to send
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; @return CFLAG: set if okay (packet sent), cleared on error
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; @clobbers r16 (r17, X)
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ioRawSendMsgHandleTransceiver:
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; enable transceiver
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M_IO_READ r16, UART_REG_UCSRB
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sbr r16,(1<<UART_BIT_TXEN) ; enable transmit
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M_IO_WRITE UART_REG_UCSRB, r16
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rcall ioRawSendMsgDirect
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; disable transceiver
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M_IO_READ r16, UART_REG_UCSRB
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cbr r16,(1<<UART_BIT_TXEN) ; disable transmit
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M_IO_WRITE UART_REG_UCSRB, r16
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine ioRawSendMsgDirect
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; Send packet.
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;
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; @param X buffer to send
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; @return CFLAG: set if okay (packet sent), cleared on error
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; @clobbers r16, r17, X
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ioRawSendMsgDirect:
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adiw xh:xl, 1
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ld r17, X ; read msg size
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sbiw xh:xl, 1
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ldi r16, 3 ; add DEST, LEN, CRC bytes
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add r17, r16
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ioRawSendMsgDirect_loop:
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; wait until transceiver ready
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M_IO_READ r16, UART_REG_UCSRA
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sbrs r16, UART_BIT_UDRE
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rjmp ioRawSendMsgDirect_loop
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; clear TXC flag by sending a 1
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sbr r16, (1<<UART_BIT_TXC)
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M_IO_WRITE UART_REG_UCSRA, r16
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; write byte to uart data register
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ld r16, X+
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M_IO_WRITE UART_REG_UDR, r16
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dec r17
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brne ioRawSendMsgDirect_loop
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; wait until all data send (i.e. send buffer empty and all bits shifted out)
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ioRawSendMsgDirect_loopComplete:
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M_IO_READ r16, UART_REG_UCSRA
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sbrs r16, UART_BIT_TXC
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rjmp ioRawSendMsgDirect_loopComplete
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sec
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine ioRawWaitForValidMsg
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; Wait for valid incoming msg
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;
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; @return CFLAG set if okay (packet received), cleared on error
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; @clobbers: r16, r17, r18 (r19, r22, X)
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ioRawWaitForValidMsg:
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ldi r16, 0xff ; expect ATTN high
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ldi r17, 100
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rcall ioWaitForAttnState100ms ; wait for up to 10s
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brcc ioRawWaitForValidMsg_end ; ATTN not high, exit
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ldi r16, 0 ; expect ATTN low
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ldi r17, 100
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rcall ioWaitForAttnState100ms ; wait for up to 10s
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brcs ioRawWaitForValidMsg_attnLow
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ret
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ioRawWaitForValidMsg_attnLow:
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ldi xl, LOW(flashRecvBuffer)
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ldi xh, HIGH(flashRecvBuffer)
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ldi r18, FLASH_RECVBUFFER_MAXLEN-3 ; maximum accepted msglen byte
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ldi r20, 10 ; 10 secs
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rcall ioRecvMsgHandleReceiver ; (r16, r17, r18, r19, r20, r22)
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brcs ioRawWaitForValidMsg_packetReceived
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; wait until ATTN is high (up to 10s)
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ldi r16, 0xff ; expect ATTN high
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ldi r17, 100
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rcall ioWaitForAttnState100ms ; wait for up to 10s
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clc
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ret
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ioRawWaitForValidMsg_packetReceived:
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ldi r16, 0xff ; expect ATTN high
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ldi r17, 100
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rcall ioWaitForAttnState100ms ; wait for up to 10s
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brcc ioRawWaitForValidMsg_end
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ldi xl, LOW(flashRecvBuffer)
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ldi xh, HIGH(flashRecvBuffer)
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rcall NETMSG_CheckMessageInBuffer
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ioRawWaitForValidMsg_end:
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine ioRecvMsgHandleReceiver
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;
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; Turn receiver on, receive message, turn receiver off.
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; @return CFLAG set if okay, cleared on error
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; @param r18 max accepted msglen size (buffersize-3)
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; @param R20 max number of secs to wait for incoming message
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; @param X buffer to receive to
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; @clobbers r16 (r17, r18, r19, r20, r22)
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ioRecvMsgHandleReceiver:
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; enable receiver
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M_IO_READ r16, UART_REG_UCSRB
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sbr r16,(1<<UART_BIT_RXEN) ; enable receive
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M_IO_WRITE UART_REG_UCSRB, r16
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rcall ioRecvMsg
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M_IO_READ r16, UART_REG_UCSRB
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cbr r16,(1<<UART_BIT_RXEN) ; disable receive
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M_IO_WRITE UART_REG_UCSRB, r16
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine ioRecvMsg
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;
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; Wait for next message, if received check validity.
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; On error skip the currently received message.
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;
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; @return CFLAG set if okay, cleared on error
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; @param r18 max accepted msglen size (buffersize-3)
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; @param R20 max number of secs to wait for incoming message
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; @param X buffer to receive to
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; @clobbers (r16, r17, r18, r19, r20, r22)
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ioRecvMsg:
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rcall ioRawRecvMsg ; (r16, r17, r18, r19, r20, r22)
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brcc ioRecvMsg_error
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push xl
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push xh
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rcall NETMSG_CheckMessageInBuffer ; (R16, R17, R18, R19, R20, X)
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pop xh
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pop xl
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brcs ioRecvMsg_end
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ioRecvMsg_error:
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rcall ioRecvSkipMessage ; skip remainder of the message
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clc
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ioRecvMsg_end:
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine ioRecvSkipMessage
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;
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; skip all receiption data until a data pause of about 10ms
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;
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; @clobbers r16
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ioRecvSkipMessage:
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ioRecvSkipMessage_loop:
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rcall ioRecvFlush ; (r16)
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; wait for a data pause of 10ms
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rcall ioRawRecvByteWithin10ms ; (r20, r22)
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brcs ioRecvSkipMessage_loop
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine ioRecvFlush
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;
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; flush receiption buffer.
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;
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; @clobbers r16
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ioRecvFlush:
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M_IO_READ r16, UART_REG_UCSRA ; read status
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sbrs r16, UART_BIT_RXC
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ret
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M_IO_READ r16, UART_REG_UDR ; read data byte
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rjmp ioRecvFlush
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; @end
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; ---------------------------------------------------------------------------
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; @routine ioRawRecvMsg
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;
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; @return CFLAG set if okay, cleared on error
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; @param r18 max accepted msglen size (buffersize-3)
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; @param R20 max number of secs to wait for incoming message
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; @param X buffer to receive to
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; @clobbers r16, r17, r19 (r18, r20, r22)
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ioRawRecvMsg:
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M_IO_READ r19, UART_REG_UCSRA
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cbr r19, (1<<UART_BIT_FE) | (1<<UART_BIT_DOR) | (1<<UART_BIT_UPE)
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M_IO_WRITE UART_REG_UCSRA, r19 ; clear errors
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; wait for begin of message
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rcall ioRawWaitForDataSeconds ; (r20, r22)
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brcc ioRawRecvMsg_end
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clr r19 ; bytecounter
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; read first two bytes
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ldi r17, 2 ; 2 bytes: address byte, msg len
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add r19, r17
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rcall ioRawRecvBytes ; (r16, r17, r18, r22)
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brcc ioRawRecvMsg_error
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cp r16, r20 ; check size
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brcc ioRawRecvMsg_error
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inc r16 ; account for checksum byte
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; read remaining bytes including checksum byte
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mov r17, r16
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add r19, r17
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rcall ioRawRecvBytes ; (r16, r17, r18, r22)
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brcc ioRawRecvMsg_error
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sub xl, r19 ; let X point back to begin of message
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sbc xh, r19
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add xh, r19
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sec
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ret
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ioRawRecvMsg_error:
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clc
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ioRawRecvMsg_end:
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine ioRawRecvBytes
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;
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; @return CFLAG set if okay (data available), cleared on error
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; @return r16 last byte received
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; @param r17 number of bytes to read
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; @param x buffer to receive to
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; @clobbers r16, r17 (r20, r22)
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ioRawRecvBytes:
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rcall ioRawRecvByteWithin10ms ; (r20, r22)
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brcc ioRawRecvBytes_end
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st X+, r16
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dec r17
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brne ioRawRecvBytes
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sec
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ioRawRecvBytes_end:
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine ioRawRecvByteWithin10ms
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;
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; Wait up to 10ms for incoming byte and read it.
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;
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; @return CFLAG set if okay (data available), cleared on error
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; @return r16 byte received (if CFLAG set)
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; @clobbers: r20, r22
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ioRawRecvByteWithin10ms:
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rcall ioRawWaitForData10ms ; (R20, R22)
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brcc ioRawRecvByteWithin10ms_end
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M_IO_READ r16, UART_REG_UCSRA ; check for errors
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andi r16, (1<<UART_BIT_FE) | (1<<UART_BIT_DOR) | (1<<UART_BIT_UPE)
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brne ioRawRecvByteWithin10ms_error
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M_IO_READ r16, UART_REG_UDR ; read data byte
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sec
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ret
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ioRawRecvByteWithin10ms_error:
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clc
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ioRawRecvByteWithin10ms_end:
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine ioRawWaitForDataSeconds
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;
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; Wait for incoming data for max 1s
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;
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; @return CFLAG set if okay (data available), cleared on error
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; @param r20 maximum number of seconds to wait
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; @clobbers: r20, r22
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ioRawWaitForDataSeconds:
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ioRawWaitForDataSeconds_loop:
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push r20
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rcall ioRawWaitForData1s ; (r20, r22)
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pop r20
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brcs ioRawWaitForDataSeconds_gotit
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sbi LED_PIN, LED_PINNUM ; toggle
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dec r20
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brne ioRawWaitForDataSeconds_loop
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clc
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ioRawWaitForDataSeconds_gotit:
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine ioRawWaitForData1s
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;
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; Wait for incoming data for max 1s
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;
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; @return CFLAG set if okay (data available), cleared on error
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; @clobbers: r20, r22
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ioRawWaitForData1s:
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ldi r20, 100
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ioRawWaitForData1s_loop:
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push r20
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rcall ioRawWaitForData10ms ; (R20, R22)
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pop r20
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brcs ioRawWaitForData1s_gotit
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dec r20
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brne ioRawWaitForData1s_loop
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clc
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ioRawWaitForData1s_gotit:
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine ioRawWaitForData10ms
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;
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; Wait for incoming data for max 10 milliseconds.
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;
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; @return CFLAG set if okay (data available), cleared on error
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; @clobbers: r20, r22
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ioRawWaitForData10ms:
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.if clock == 8000000
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ldi r20, 80
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.endif
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.if clock == 1000000
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ldi r20, 10
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.endif
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ioRawWaitForData10ms_loop:
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push r20
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rcall ioRawWaitForData1000Cycles ; (r20, r22)
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pop r20
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brcs ioRawWaitForData10ms_gotit
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dec r20
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brne ioRawWaitForData10ms_loop
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clc
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ioRawWaitForData10ms_gotit:
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine ioRawWaitForData1000Cycles
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;
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; Wait for incoming data for max 1000 clock cycles
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; (about 1ms at 1MHz, 0.125 at 8MHz)
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;
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; @return CFLAG set if okay (packet received), cleared on error
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; @clobbers: r20, r22
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ioRawWaitForData1000Cycles:
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ldi r20, 140 ; 1
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ioRawWaitForData_loop:
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M_IO_READ r22, UART_REG_UCSRA ; 2
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sbrc r22, UART_BIT_RXC ; 2/3
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rjmp ioRawWaitForData_gotit ; 2
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dec r20 ; 1
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brne ioRawWaitForData_loop ; 1/2 -> 7 per loop, max about 1000
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clc ; 1
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ret ; 4
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ioRawWaitForData_gotit:
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sec ; 1
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ret ; 4
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; @end
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