303 lines
9.7 KiB
C++
Executable File
303 lines
9.7 KiB
C++
Executable File
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
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;***** Created: 2011-02-09 12:03 ******* Source: AT86RF401.xml ***********
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;*************************************************************************
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;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
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;*
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;* Number : AVR000
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;* File Name : "AT86RF401def.inc"
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;* Title : Register/Bit Definitions for the AT86RF401
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;* Date : 2011-02-09
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;* Version : 2.35
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;* Support E-mail : avr@atmel.com
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;* Target MCU : AT86RF401
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;*
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;* DESCRIPTION
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;* When including this file in the assembly program file, all I/O register
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;* names and I/O register bit names appearing in the data book can be used.
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;* In addition, the six registers forming the three data pointers X, Y and
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;* Z have been assigned names XL - ZH. Highest RAM address for Internal
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;* SRAM is also defined
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;*
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;* The Register names are represented by their hexadecimal address.
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;*
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;* The Register Bit names are represented by their bit number (0-7).
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;*
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;* Please observe the difference in using the bit names with instructions
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;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
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;* (skip if bit in register set/cleared). The following example illustrates
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;* this:
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;*
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;* in r16,PORTB ;read PORTB latch
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;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
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;* out PORTB,r16 ;output to PORTB
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;*
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;* in r16,TIFR ;read the Timer Interrupt Flag Register
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;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
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;* rjmp TOV0_is_set ;jump if set
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;* ... ;otherwise do something else
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;*************************************************************************
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#ifndef _AT86RF401DEF_INC_
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#define _AT86RF401DEF_INC_
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#pragma partinc 0
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; ***** SPECIFY DEVICE ***************************************************
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.device AT86RF401
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#pragma AVRPART ADMIN PART_NAME AT86RF401
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.equ SIGNATURE_000 = 0x1e
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.equ SIGNATURE_001 = 0x91
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.equ SIGNATURE_002 = 0x81
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#pragma AVRPART CORE CORE_VERSION V2
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#pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z+
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#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED sleep
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; ***** I/O REGISTER DEFINITIONS *****************************************
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; NOTE:
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; Definitions marked "MEMORY MAPPED"are extended I/O ports
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; and cannot be used with IN/OUT instructions
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.equ SREG = 0x3f
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.equ SPL = 0x3d
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.equ SPH = 0x3e
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.equ BL_CONFIG = 0x35
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.equ B_DET = 0x34
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.equ AVR_CONFIG = 0x33
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.equ IO_DATIN = 0x32
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.equ IO_DATOUT = 0x31
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.equ IO_ENAB = 0x30
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.equ WDTCR = 0x22
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.equ BTCR = 0x21
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.equ BTCNT = 0x20
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.equ DEEAR = 0x1e
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.equ DEEDR = 0x1d
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.equ DEECR = 0x1c
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.equ LOCKDET2 = 0x17
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.equ VCOTUNE = 0x16
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.equ PWR_ATTEN = 0x14
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.equ TX_CNTL = 0x12
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.equ LOCKDET1 = 0x10
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; ***** BIT DEFINITIONS **************************************************
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; ***** RF_CONTROL *******************
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; LOCKDET1 - Lock Detector Configuration Register 1
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.equ CS0 = 0 ; Cycle Slip Counter bit 0
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.equ CS1 = 1 ; Cycle Slip Counter bit 1
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.equ BOD = 2 ; Black Out Disable
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.equ ENKO = 3 ; Enable Key On Bit
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.equ UPOK = 4 ; Unlock Conuter Control
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; LOCKDET2 - Lock Detector Configuration register 2
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.equ LC0 = 0 ; Lock Count bit 0
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.equ LC1 = 1 ; Lock Count bit 1
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.equ LC2 = 2 ; Lock Count bit 2
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.equ ULC0 = 3 ; Unlock Count bit 0
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.equ ULC1 = 4 ; Unlock Count bit 1
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.equ ULC2 = 5 ; Unlock Count bit 2
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.equ LAT = 6 ; Lock Always True
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.equ EUD = 7 ; Enable Unlock Detect
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; TX_CNTL - Transmit Control Register
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.equ LOC = 2 ; PLL Lock
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.equ TXK = 4 ; Transmitter Key
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.equ TXE = 5 ; Transmitter Enable
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.equ FSK = 6 ; FSK Mode
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; PWR_ATTEN - Power Attenuation Control Register
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.equ PCF0 = 0 ; Power Control Fine bit 0
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.equ PCF1 = 1 ; Power Control Fine bit 1
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.equ PCF2 = 2 ; Power Control Fine bit 2
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.equ PCC0 = 3 ; Power Control Coarse bit 0
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.equ PCC1 = 4 ; Power Control Coarse bit 1
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.equ PCC2 = 5 ; Power Control Coarse bit 2
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; VCOTUNE - VCO Tuning Register
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.equ VCOTUNE0 = 0 ; VCO Tuning Register bit 0
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.equ VCOTUNE1 = 1 ; VCO Tuning Register bit 1
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.equ VCOTUNE2 = 2 ; VCO Tuning Register bit 2
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.equ VCOTUNE3 = 3 ; VCO Tuning Register bit 3
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.equ VCOTUNE4 = 4 ; VCO Tuning Register bit 4
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.equ VCOVDET0 = 6 ; VCO Voltage Detector bit 0
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.equ VCOVDET1 = 7 ; VCO Voltage Detector bit 1
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; ***** EEPROM ***********************
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; DEEAR - EERPOM Address Register
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.equ BA0 = 0 ; EEPROM Byte Address bit 0
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.equ BA1 = 1 ; EEPROM Byte Address bit 1
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.equ BA2 = 2 ; EEPROM Byte Address bit 2
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.equ PA3 = 3 ; EEPROM Page Address bit 3
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.equ PA4 = 4 ; EEPROM Page Address bit 4
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.equ PA5 = 5 ; EEPROM Page Address bit 5
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.equ PA6 = 6 ; EEPROM Page Address bit 6
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; DEEDR - EEPROM Data Register
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.equ ED0 = 0 ; EEPROM Data Register bit 0
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.equ ED1 = 1 ; EEPROM Data Register bit 1
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.equ ED2 = 2 ; EEPROM Data Register bit 2
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.equ ED3 = 3 ; EEPROM Data Register bit 3
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.equ ED4 = 4 ; EEPROM Data Register bit 4
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.equ ED5 = 5 ; EEPROM Data Register bit 5
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.equ ED6 = 6 ; EEPROM Data Register bit 6
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.equ ED7 = 7 ; EEPROM Data Register bit 7
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; DEECR - EEPROM Control Register
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.equ EER = 0 ; EEPROM Read Bit
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.equ EEL = 1 ; EEPROM Load Bit
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.equ EEU = 2 ; EEPROM Unlock Bit
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.equ BSY = 3 ; EERPOM Busy Bit
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; ***** WATCHDOG *********************
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; WDTCR - Watchdog Timer Control Register
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.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
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.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
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.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
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.equ WDE = 3 ; Watch Dog Enable
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.equ WDTOE = 4 ; RW
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.equ WDDE = WDTOE ; For compatibility
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; ***** TIMER_COUNTER_0 **************
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; BTCNT - Timer Count register
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.equ C0 = 0 ; Timer Count Register bit 7
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.equ C1 = 1 ; Timer Count Register bit 7
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.equ C2 = 2 ; Timer Count Register bit 7
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.equ C3 = 3 ; Timer Count Register bit 7
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.equ C4 = 4 ; Timer Count Register bit 7
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.equ C5 = 5 ; Timer Count Register bit 7
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.equ C6 = 6 ; Timer Count Register bit 7
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.equ C7 = 7 ; Timer Count Register bit 7
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; BTCR - Bit Timer Counter Control Register
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.equ F0 = 0 ; Flag 0
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.equ DATA = 1 ; Data Bit
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.equ F2 = 2 ; Flag 2
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.equ IE = 3 ; Interrupt Enable
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.equ M0 = 4 ; Bit Timer Mode bit 0
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.equ M1 = 5 ; Bit Timer Mode bit 1
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.equ C8 = 6 ; Timer Count Register bit 8
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.equ C9 = 7 ; Timer Count Register bit 9
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; ***** PORT *************************
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; IO_ENAB - I/O Enable Register
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.equ IOE0 = 0 ; I/O Enable bit 0
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.equ IOE1 = 1 ; I/O Enable bit 1
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.equ IOE2 = 2 ; I/O Enable bit 2
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.equ IOE3 = 3 ; I/O Enable bit 3
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.equ IOE4 = 4 ; I/O Enable bit 4
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.equ IOE5 = 5 ; I/O Enable bit 5
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; IO_DATOUT - I/O Data Out Register
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.equ IOO0 = 0 ; I/O Data Out Register bit 0
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.equ IOO1 = 1 ; I/O Data Out Register bit 1
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.equ IOO2 = 2 ; I/O Data Out Register bit 2
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.equ IOO3 = 3 ; I/O Data Out Register bit 3
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.equ IOO4 = 4 ; I/O Data Out Register bit 4
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.equ IOO5 = 5 ; I/O Data Out Register bit 5
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; IO_DATIN - I/O Data In register
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.equ IOI0 = 0 ; I/O Data In Register bit 0
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.equ IOI1 = 1 ; I/O Data In Register bit 1
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.equ IOI2 = 2 ; I/O Data In Register bit 2
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.equ IOI3 = 3 ; I/O Data In Register bit 3
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.equ IOI4 = 4 ; I/O Data In Register bit 4
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.equ IOI5 = 5 ; I/O Data In Register bit 5
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; ***** CPU **************************
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; SREG - Status Register
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.equ SREG_C = 0 ; Carry Flag
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.equ SREG_Z = 1 ; Zero Flag
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.equ SREG_N = 2 ; Negative Flag
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.equ SREG_V = 3 ; Two's Complement Overflow Flag
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.equ SREG_S = 4 ; Sign Bit
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.equ SREG_H = 5 ; Half Carry Flag
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.equ SREG_T = 6 ; Bit Copy Storage
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.equ SREG_I = 7 ; Global Interrupt Enable
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; AVR_CONFIG - AVR Configuration Register
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.equ BBM = 0 ; Button Boot Mode
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.equ SLEEP = 1 ; Sleep Bit
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.equ BLI = 2 ; Battery Low Indicator
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.equ BD = 3 ; Battery Dead
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.equ TM = 4 ; Test Mode
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.equ ACS0 = 5 ; AVR System Clock Select bit 0
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.equ ACS1 = 6 ; AVR System Clock Select bit 1
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; B_DET - Button Detect Register
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.equ BD0 = 0 ; Button Detect bit 0
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.equ BD1 = 1 ; Button Detect bit 1
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.equ BD2 = 2 ; Button Detect bit 2
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.equ BD3 = 3 ; Button Detect bit 3
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.equ BD4 = 4 ; Button Detect bit 4
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.equ BD5 = 5 ; Button Detect bit 5
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; BL_CONFIG - Battery Low Configuration Register
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.equ BL0 = 0 ; Battery Low Detection Level bit 0
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.equ BL1 = 1 ; Battery Low Detection Level bit 1
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.equ BL2 = 2 ; Battery Low Detection Level bit 2
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.equ BL3 = 3 ; Battery Low Detection Level bit 3
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.equ BL4 = 4 ; Battery Low Detection Level bit 4
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.equ BL5 = 5 ; Battery Low Detection Level bit 5
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.equ BLV = 6 ; Battery Low Valid
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.equ BL = 7 ; Battery Low
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; ***** LOCKSBITS ********************************************************
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.equ LB1 = 0 ; Lockbit
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.equ LB2 = 1 ; Lockbit
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; ***** FUSES ************************************************************
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; LOW fuse bits
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; ***** CPU REGISTER DEFINITIONS *****************************************
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.def XH = r27
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.def XL = r26
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.def YH = r29
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.def YL = r28
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.def ZH = r31
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.def ZL = r30
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; ***** DATA MEMORY DECLARATIONS *****************************************
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.equ FLASHEND = 0x03ff ; Note: Word address
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.equ IOEND = 0x003f
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.equ SRAM_START = 0x0060
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.equ SRAM_SIZE = 128
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.equ RAMEND = 0x00df
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.equ XRAMEND = 0x0000
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.equ E2END = 0x007f
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.equ EEPROMEND = 0x007f
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.equ EEADRBITS = 7
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#pragma AVRPART MEMORY PROG_FLASH 2048
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#pragma AVRPART MEMORY EEPROM 128
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#pragma AVRPART MEMORY INT_SRAM SIZE 128
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#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
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; ***** INTERRUPT VECTORS ************************************************
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.equ TXDONEaddr = 0x0002 ; Transmission Done, Bit Timer Flag 2 Interrupt
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.equ TXEMPTYaddr = 0x0004 ; Transmit Buffer Empty, Bit Itmer Flag 0 Interrupt
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.equ INT_VECTORS_SIZE = 6 ; size in words
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#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
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#endif /* _AT86RF401DEF_INC_ */
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; ***** END OF FILE ******************************************************
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