169 lines
3.7 KiB
NASM
169 lines
3.7 KiB
NASM
; ***************************************************************************
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; copyright : (C) 2025 by Martin Preuss
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; email : martin@libchipcard.de
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;
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; ***************************************************************************
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; * This file is part of the project "AqHome". *
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; * Please see toplevel file COPYING of that project for license details. *
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; ***************************************************************************
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.dseg
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; uartHw_TtyOn1Interface: .byte UART_HW_IFACE_SIZE
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.cseg
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; ---------------------------------------------------------------------------
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; @routine UART_HW_TtyOn1_Init @global
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;
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
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; @clobbers R16, R17, X
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UART_HW_TtyOn1_Init:
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rcall UART_HW_InitInterface
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; set baudrate
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.if clock == 8000000
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ldi r16, 25 ; (19.2Kb/s at 8MHz)
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ldi r17, 0
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.endif
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.if clock == 1000000
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ldi r16, 3 ; (19.2Kb/s at 1MHz)
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ldi r17, 0
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.endif
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out UBRR1H, r17
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out UBRR1L, r16
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; set character format
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ldi r16, (1<<USBS1)|(3<<UCSZ10)
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out UCSR1C, r16
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_HW_TtyOn1_StartRx @global
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;
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; @clobbers none
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UART_HW_TtyOn1_StartRx:
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; enable RX complete interrupt
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sbi UCSR1B, RXCIE1
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; enable receive
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sbi UCSR1B, RXEN1
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_HW_TtyOn1_StopRx @global
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;
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; @clobbers none
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UART_HW_TtyOn1_StopRx:
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; disable RX complete interrupt
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cbi UCSR1B, RXCIE1
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; disable receive
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cbi UCSR1B, RXEN1
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_HW_TtyOn1_StartTx @global
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;
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
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; @clobbers none
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UART_HW_TtyOn1_StartTx:
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; enable TX data register empty interrupt
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sbi UCSR1B, UDRIE1
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; enable transmit
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sbi UCSR1B, TXEN1
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_HW_TtyOn1_StopTx @global
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;
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
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; @clobbers none
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UART_HW_TtyOn1_StopTx:
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; enable TX data register empty interrupt
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cbi UCSR1B, UDRIE1
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; enable transmit
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cbi UCSR1B, TXEN1
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_HW_TtyOn1_RxCharIsr @global
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;
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
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; @clobbers R16 (R17, R18, X)
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UART_HW_TtyOn1_RxCharIsr:
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sbis UCSR1A, RXC1
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rjmp UART_HW_TtyOn1_RxCharIsr_end ; no data
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in r16, UDR1
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rcall UART_HW_InterfaceAddReadByte ; (R17, R18, X)
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UART_HW_TtyOn1_RxCharIsr_end:
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_HW_TtyOn1_TxCharIsr @global
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;
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
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; @clobbers R16, X
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UART_HW_TtyOn1_TxCharIsr:
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sbis UCSR1A,UDRE1
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rjmp UART_HW_TtyOn1_TxCharIsr_end ; not ready
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ldd r16, Y+UART_HW_IFACE_OFFS_WRITEBUFFERNUM
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cpi r16, 0xff
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breq UART_HW_TtyOn1_TxCharIsr_end ; no current write buffer
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ldd r16, Y+UART_HW_IFACE_OFFS_WRITEBUFFERLEFT
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tst r16
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breq UART_HW_TtyOn1_TxCharIsr_end ; nothing to send
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dec r16
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std Y+UART_HW_IFACE_OFFS_WRITEBUFFERLEFT, r16
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ldd xl, Y+UART_HW_IFACE_OFFS_WRITEBUFFERPTR
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ldd xh, Y+UART_HW_IFACE_OFFS_WRITEBUFFERPTR+1
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ld r16, X+
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std Y+UART_HW_IFACE_OFFS_WRITEBUFFERPTR, xl
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std Y+UART_HW_IFACE_OFFS_WRITEBUFFERPTR+1, xh
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out UDR1, r16
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UART_HW_TtyOn1_TxCharIsr_end:
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ret
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; @end
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