18d34450e7
- sending and receiving now basically works again, but too often the read buffer is in use when trying to receive a message.
286 lines
6.1 KiB
NASM
286 lines
6.1 KiB
NASM
; ***************************************************************************
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; copyright : (C) 2023 by Martin Preuss
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; email : martin@libchipcard.de
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;
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; ***************************************************************************
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; * This file is part of the project "AqHome". *
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; * Please see toplevel file COPYING of that project for license details. *
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; ***************************************************************************
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; ***************************************************************************
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; defs
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.equ TIMER_FLAGS_IF_ADDR = 1
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; ***************************************************************************
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; data
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.dseg
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timerModuleData:
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timerModuleTickCounter: .byte 1
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timerTicksSinceLastRun: .byte 2
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timerModuleCounterSecs: .byte 4
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timerInterrupts: .byte 2
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timerModuleData_end:
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; ***************************************************************************
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; code
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.cseg
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TIMER_BEGIN:
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; ---------------------------------------------------------------------------
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; Timer_Init
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;
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; IN:
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; - nothing
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; OUT:
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; - nothing
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; USED: r16, r17, x
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Timer_Init: ; setup timer for IRQ every 100ms
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; reset data in SDRAM
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ldi xh, HIGH(timerModuleData)
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ldi xl, LOW(timerModuleData)
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ldi r16, 0
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ldi r17, (timerModuleData_end-timerModuleData)
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rcall Utils_FillSram
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; CTC mode (WGM2:0=2, OCR0A=value, OCF0A Flag =1, -> IRQ_OC0A
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; CMP-A interrupt about every 100ms
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ldi r16, (1<<CS02) | (1<<CS00) ; Prescaler 1024
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out TCCR0B, r16
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ldi r16, (1<<WGM01) ; CTC mode
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out TCCR0A, r16
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ldi r16, 98-1 ; (1,000,000/1024)/10 = 97.65625
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out OCR0A, r16
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ldi r16, (1<<OCF0A) ; clear pending interrupts
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out TIFR0, r16
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ldi r16, (1<<OCIE0A)
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out TIMSK0, r16
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rcall timerInitTimers
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ret
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; ---------------------------------------------------------------------------
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; Timer_Fini
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;
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; IN:
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; - nothing
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; OUT:
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; - nothing
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; USED:
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Timer_Fini:
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ret
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; ---------------------------------------------------------------------------
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; Timer_Run
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;
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; IN:
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; - nothing
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; OUT:
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; - CFLAG: set if something done, cleared otherwise
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; USED: r15, r16, r24, r25 (more depending on called routines)
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Timer_Run:
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in r15, SREG
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cli
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lds r24, timerTicksSinceLastRun
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lds r25, timerTicksSinceLastRun+1
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clr r16 ; replace with 0 for next IRQ
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sts timerTicksSinceLastRun, r16
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sts timerTicksSinceLastRun+1, r16
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out SREG, r15 ; restore global IRQ flag
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sbiw r25:r24, 0
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clc ; flag "nothing done"
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breq Timer_Run_End
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Timer_Run_loop: ; for every occurred 100ms irq
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push r24
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push r25
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rcall onEvery100ms
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pop r25
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pop r24
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lds r16, timerModuleTickCounter
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inc r16
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cpi r16, 10
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brcc Timer_Run_SecondElapsed
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sts timerModuleTickCounter, r16
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rjmp Timer_Run_loop_end
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Timer_Run_SecondElapsed:
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clr r16
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sts timerModuleTickCounter, r16
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push r24
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push r25
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rcall timerRunTimers
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pop r25
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pop r24
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Timer_Run_loop_end:
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sbiw r25:r24, 1
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brne Timer_Run_loop
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sec
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Timer_Run_End:
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ret
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timerInitTimers:
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ldi zl, LOW(timerList*2)
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ldi zh, HIGH(timerList*2)
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clr r16 ; run var for pos in time table
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clr r17 ; 0 for adc
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timerInitTimers_loop:
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rcall timerReadTableEntry
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mov r18, xl
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or r18, xh
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breq timerInitTimers_end
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mov r18, r20
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or r18, r21
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breq timerInitTimers_writeInitial
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add r20, r16 ; add counter pos in table so that not all timers elapse at the same time
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adc r21, r17
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timerInitTimers_writeInitial:
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st X+, r20
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st X, r21
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inc r16
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inc r16
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rjmp timerInitTimers_loop
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timerInitTimers_end:
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ret
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timerRunTimers:
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ldi xl, LOW(timerModuleCounterSecs)
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ldi xh, HIGH(timerModuleCounterSecs)
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rcall Utils_IncrementCounter32
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ldi zl, LOW(timerList*2)
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ldi zh, HIGH(timerList*2)
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timerRunTimers_loop:
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rcall timerReadTableEntry
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mov r16, xl
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or r16, xh
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breq timerRunTimers_end
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mov r16, r22
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andi r16, TIMER_FLAGS_IF_ADDR
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breq timerRunTimers_l1 ; no need to check address
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lds r16, com2Address ; check address
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tst r16
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breq timerRunTimers_loop ; no address, ignore counter
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timerRunTimers_l1:
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ld r24, X+
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ld r25, X
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sbiw r25:r24, 1
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brcs timerRunTimers_loop ; overflow, so already was zero, ignore entry
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breq timerRunTimers_reachedZero ; reached zero
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st X, r25
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st -X, r24
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rjmp timerRunTimers_loop
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timerRunTimers_reachedZero:
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st X, r21 ; reset initial value
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st -X, r20
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push zl
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push zh
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rcall timerCallR19R18
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pop zh
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pop zl
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rjmp timerRunTimers_loop
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timerRunTimers_end:
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ret
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; ---------------------------------------------------------------------------
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; read time table entry.
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;
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; IN:
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; - Z : pointer to time list entry (suitable for LPM)
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; OUT:
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; - r19:r18: handler routine
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; - X : SRAM address for counter
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; - r21:r20: initial value
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; - r22 : flags
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; - r23 : reserved
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timerReadTableEntry:
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lpm xl, Z+ ; SRAM address of counter
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lpm xh, Z+
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lpm r18, Z+ ; routine (low)
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lpm r19, Z+ ; routine (high)
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lpm r22, Z+ ; flags
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lpm r23, Z+ ; reserved
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lpm r20, Z+ ; initial value
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lpm r21, Z+
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ret
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timerCallR19R18:
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push r18
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push r19
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ret
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; ---------------------------------------------------------------------------
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; OC0A interrupt handler
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;
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; Called every 100 milliseconds, increments timerTicksSinceLastRun. The rest is done outside ISR
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; in Timer_Run.
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timerIrqOC0A:
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push r15
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in r15, SREG
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push r24
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push r25
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lds r24, timerTicksSinceLastRun
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lds r25, timerTicksSinceLastRun+1
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adiw r25:r24, 1
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sts timerTicksSinceLastRun, r24
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sts timerTicksSinceLastRun+1, r25
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lds r24, timerInterrupts
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lds r25, timerInterrupts+1
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adiw r25:r24, 1
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sts timerInterrupts, r24
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sts timerInterrupts+1, r25
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pop r25
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pop r24
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out SREG, r15
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pop r15
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reti
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TIMER_END:
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.equ MODULE_SIZE_TIMER = TIMER_END-TIMER_BEGIN
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