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a07513692085eee7f8cf29f90f8ed824a4e5ac9e
aqhomecontrol/avr/include/ATxmega192D3def.inc
Martin Preuss 16be96ada9 Initial import.
2023-01-16 23:12:09 +01:00

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;*************************************************************************
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
;*
;* Number : AVR000
;* File Name : ATxmega192D3def.inc
;* Title : Register/Bit Definitions for the ATxmega192D3
;* Date : Jan 01 2008
;* Version : 1.00
;* Support E-mail : avr@atmel.com
;* Target MCU : ATxmega192D3
;*
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register
;* names and I/O register bit names appearing in the data book can be used.
;* In addition, the six registers forming the three data pointers X, Y and
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
;* SRAM is also defined
;*
;*************************************************************************
#ifndef _ATxmega192D3DEF_INC_
#define _ATxmega192D3DEF_INC_
#pragma partinc 0
; ***** SPECIFY DEVICE ***************************************************
.device ATxmega192D3
.equ SIGNATURE_000 = 0x1E
.equ SIGNATURE_001 = 0x97
.equ SIGNATURE_002 = 0x49
#pragma AVRPART ADMIN PART_NAME ATxmega192D3
#pragma AVRPART CORE CORE_VERSION V3X
; ***** ABSOLUTE I/O REGISTER LOCATIONS **********************************
;***************************************************************************
;** GPIO - General Purpose IO Registers
;***************************************************************************
.equ GPIO_GPIOR0 = 0 // General Purpose IO Register 0
.equ GPIO_GPIOR1 = 1 // General Purpose IO Register 1
.equ GPIO_GPIOR2 = 2 // General Purpose IO Register 2
.equ GPIO_GPIOR3 = 3 // General Purpose IO Register 3
;***************************************************************************
;** OCD - On-Chip Debug System
;***************************************************************************
.equ OCD_OCDR0 = 46 // OCD Register 0
.equ OCD_OCDR1 = 47 // OCD Register 1
;***************************************************************************
;** CPU - CPU Registers
;***************************************************************************
.equ CPU_CCP = 52 // Configuration Change Protection
.equ CPU_RAMPD = 56 // Ramp D
.equ CPU_RAMPX = 57 // Ramp X
.equ CPU_RAMPY = 58 // Ramp Y
.equ CPU_RAMPZ = 59 // Ramp Z
.equ CPU_EIND = 60 // Extended Indirect Jump
.equ CPU_SPL = 61 // Stack Pointer Low
.equ CPU_SPH = 62 // Stack Pointer High
.equ CPU_SREG = 63 // Status Register
;***************************************************************************
;** CLK - Clock System
;***************************************************************************
.equ CLK_CTRL = 64 // Control Register
.equ CLK_PSCTRL = 65 // Prescaler Control Register
.equ CLK_LOCK = 66 // Lock register
.equ CLK_RTCCTRL = 67 // RTC Control Register
;***************************************************************************
;** SLEEP - Sleep Controller
;***************************************************************************
.equ SLEEP_CTRL = 72 // Control Register
;***************************************************************************
;** OSC - Oscillator Control
;***************************************************************************
.equ OSC_CTRL = 80 // Control Register
.equ OSC_STATUS = 81 // Status Register
.equ OSC_XOSCCTRL = 82 // External Oscillator Control Register
.equ OSC_XOSCFAIL = 83 // External Oscillator Failure Detection Register
.equ OSC_RC32KCAL = 84 // 32kHz Internal Oscillator Calibration Register
.equ OSC_PLLCTRL = 85 // PLL Control REgister
.equ OSC_DFLLCTRL = 86 // DFLL Control Register
;***************************************************************************
;** DFLLRC32M - DFLL for 32MHz RC Oscillator
;***************************************************************************
.equ DFLLRC32M_CTRL = 96 // Control Register
.equ DFLLRC32M_CALA = 98 // Calibration Register A
.equ DFLLRC32M_CALB = 99 // Calibration Register B
.equ DFLLRC32M_COMP0 = 100 // Oscillator Compare Register 0
.equ DFLLRC32M_COMP1 = 101 // Oscillator Compare Register 1
.equ DFLLRC32M_COMP2 = 102 // Oscillator Compare Register 2
;***************************************************************************
;** DFLLRC2M - DFLL for 2MHz RC Oscillator
;***************************************************************************
.equ DFLLRC2M_CTRL = 104 // Control Register
.equ DFLLRC2M_CALA = 106 // Calibration Register A
.equ DFLLRC2M_CALB = 107 // Calibration Register B
.equ DFLLRC2M_COMP0 = 108 // Oscillator Compare Register 0
.equ DFLLRC2M_COMP1 = 109 // Oscillator Compare Register 1
.equ DFLLRC2M_COMP2 = 110 // Oscillator Compare Register 2
;***************************************************************************
;** PR - Power Reduction
;***************************************************************************
.equ PR_PRGEN = 112 // General Power Reduction
.equ PR_PRPA = 113 // Power Reduction Port A
.equ PR_PRPB = 114 // Power Reduction Port B
.equ PR_PRPC = 115 // Power Reduction Port C
.equ PR_PRPD = 116 // Power Reduction Port D
.equ PR_PRPE = 117 // Power Reduction Port E
.equ PR_PRPF = 118 // Power Reduction Port F
;***************************************************************************
;** RST - Reset Controller
;***************************************************************************
.equ RST_STATUS = 120 // Status Register
.equ RST_CTRL = 121 // Control Register
;***************************************************************************
;** WDT - Watch-Dog Timer
;***************************************************************************
.equ WDT_CTRL = 128 // Control
.equ WDT_WINCTRL = 129 // Windowed Mode Control
.equ WDT_STATUS = 130 // Status
;***************************************************************************
;** MCU - MCU Control
;***************************************************************************
.equ MCU_DEVID0 = 144 // Device ID byte 0
.equ MCU_DEVID1 = 145 // Device ID byte 1
.equ MCU_DEVID2 = 146 // Device ID byte 2
.equ MCU_REVID = 147 // Revision ID
.equ MCU_JTAGUID = 148 // JTAG User ID
.equ MCU_MCUCR = 150 // MCU Control
.equ MCU_EVSYSLOCK = 152 // Event System Lock
.equ MCU_AWEXLOCK = 153 // AWEX Lock
;***************************************************************************
;** PMIC - Programmable Interrupt Controller
;***************************************************************************
.equ PMIC_STATUS = 160 // Status Register
.equ PMIC_INTPRI = 161 // Interrupt Priority
.equ PMIC_CTRL = 162 // Control Register
;***************************************************************************
;** EVSYS - Event System
;***************************************************************************
.equ EVSYS_CH0MUX = 384 // Event Channel 0 Multiplexer
.equ EVSYS_CH1MUX = 385 // Event Channel 1 Multiplexer
.equ EVSYS_CH2MUX = 386 // Event Channel 2 Multiplexer
.equ EVSYS_CH3MUX = 387 // Event Channel 3 Multiplexer
.equ EVSYS_CH0CTRL = 392 // Channel 0 Control Register
.equ EVSYS_CH1CTRL = 393 // Channel 1 Control Register
.equ EVSYS_CH2CTRL = 394 // Channel 2 Control Register
.equ EVSYS_CH3CTRL = 395 // Channel 3 Control Register
.equ EVSYS_STROBE = 400 // Event Strobe
.equ EVSYS_DATA = 401 // Event Data
;***************************************************************************
;** NVM - Non Volatile Memory
;***************************************************************************
.equ NVM_ADDR0 = 448 // Address Register 0
.equ NVM_ADDR1 = 449 // Address Register 1
.equ NVM_ADDR2 = 450 // Address Register 2
.equ NVM_DATA0 = 452 // Data Register 0
.equ NVM_DATA1 = 453 // Data Register 1
.equ NVM_DATA2 = 454 // Data Register 2
.equ NVM_CMD = 458 // Command
.equ NVM_CTRLA = 459 // Control Register A
.equ NVM_CTRLB = 460 // Control Register B
.equ NVM_INTCTRL = 461 // Interrupt Control
.equ NVM_STATUS = 463 // Status
.equ NVM_LOCKBITS = 464 // Lock Bits
;***************************************************************************
;** ACA - Analog Comparator A
;***************************************************************************
.equ ACA_AC0CTRL = 896 // Analog Comparator 0 Control
.equ ACA_AC1CTRL = 897 // Analog Comparator 1 Control
.equ ACA_AC0MUXCTRL = 898 // Analog Comparator 0 MUX Control
.equ ACA_AC1MUXCTRL = 899 // Analog Comparator 1 MUX Control
.equ ACA_CTRLA = 900 // Control Register A
.equ ACA_CTRLB = 901 // Control Register B
.equ ACA_WINCTRL = 902 // Window Mode Control
.equ ACA_STATUS = 903 // Status
;***************************************************************************
;** ADCA - Analog to Digital Converter A
;***************************************************************************
.equ ADCA_CTRLA = 512 // Control Register A
.equ ADCA_CTRLB = 513 // Control Register B
.equ ADCA_REFCTRL = 514 // Reference Control
.equ ADCA_EVCTRL = 515 // Event Control
.equ ADCA_PRESCALER = 516 // Clock Prescaler
.equ ADCA_INTFLAGS = 518 // Interrupt Flags
.equ ADCA_TEMP = 519 // Temporary Register
.equ ADCA_CAL = 524 // Calibration Value
.equ ADCA_CH0RES = 528 // Channel 0 Result
.equ ADCA_CMP = 536 // Compare Value
.equ ADCA_CH0_CTRL = 544 // Control Register
.equ ADCA_CH0_MUXCTRL = 545 // MUX Control
.equ ADCA_CH0_INTCTRL = 546 // Channel Interrupt Control Register
.equ ADCA_CH0_INTFLAGS = 547 // Interrupt Flags
.equ ADCA_CH0_RES = 548 // Channel Result
;***************************************************************************
;** RTC - Real-Time Counter
;***************************************************************************
.equ RTC_CTRL = 1024 // Control Register
.equ RTC_STATUS = 1025 // Status Register
.equ RTC_INTCTRL = 1026 // Interrupt Control Register
.equ RTC_INTFLAGS = 1027 // Interrupt Flags
.equ RTC_TEMP = 1028 // Temporary register
.equ RTC_CNT = 1032 // Count Register
.equ RTC_PER = 1034 // Period Register
.equ RTC_COMP = 1036 // Compare Register
;***************************************************************************
;** TWIC - Two-Wire Interface C
;***************************************************************************
.equ TWIC_CTRL = 1152 // TWI Common Control Register
.equ TWIC_MASTER_CTRLA = 1153 // Control Register A
.equ TWIC_MASTER_CTRLB = 1154 // Control Register B
.equ TWIC_MASTER_CTRLC = 1155 // Control Register C
.equ TWIC_MASTER_STATUS = 1156 // Status Register
.equ TWIC_MASTER_BAUD = 1157 // Baurd Rate Control Register
.equ TWIC_MASTER_ADDR = 1158 // Address Register
.equ TWIC_MASTER_DATA = 1159 // Data Register
.equ TWIC_SLAVE_CTRLA = 1160 // Control Register A
.equ TWIC_SLAVE_CTRLB = 1161 // Control Register B
.equ TWIC_SLAVE_STATUS = 1162 // Status Register
.equ TWIC_SLAVE_ADDR = 1163 // Address Register
.equ TWIC_SLAVE_DATA = 1164 // Data Register
.equ TWIC_SLAVE_ADDRMASK = 1165 // Address Mask Register
;***************************************************************************
;** PORT_CFG - Port Configuration
;***************************************************************************
.equ PORTCFG_MPCMASK = 176 // Multi-pin Configuration Mask
.equ PORTCFG_VPCTRLA = 178 // Virtual Port Control Register A
.equ PORTCFG_VPCTRLB = 179 // Virtual Port Control Register B
.equ PORTCFG_CLKEVOUT = 180 // Clock and Event Out Register
;***************************************************************************
;** VPORT0 - Virtual Port 0
;***************************************************************************
.equ VPORT0_DIR = 16 // I/O Port Data Direction
.equ VPORT0_OUT = 17 // I/O Port Output
.equ VPORT0_IN = 18 // I/O Port Input
.equ VPORT0_INTFLAGS = 19 // Interrupt Flag Register
;***************************************************************************
;** VPORT1 - Virtual Port 1
;***************************************************************************
.equ VPORT1_DIR = 20 // I/O Port Data Direction
.equ VPORT1_OUT = 21 // I/O Port Output
.equ VPORT1_IN = 22 // I/O Port Input
.equ VPORT1_INTFLAGS = 23 // Interrupt Flag Register
;***************************************************************************
;** VPORT2 - Virtual Port 2
;***************************************************************************
.equ VPORT2_DIR = 24 // I/O Port Data Direction
.equ VPORT2_OUT = 25 // I/O Port Output
.equ VPORT2_IN = 26 // I/O Port Input
.equ VPORT2_INTFLAGS = 27 // Interrupt Flag Register
;***************************************************************************
;** VPORT3 - Virtual Port 3
;***************************************************************************
.equ VPORT3_DIR = 28 // I/O Port Data Direction
.equ VPORT3_OUT = 29 // I/O Port Output
.equ VPORT3_IN = 30 // I/O Port Input
.equ VPORT3_INTFLAGS = 31 // Interrupt Flag Register
;***************************************************************************
;** PORTA - Port A
;***************************************************************************
.equ PORTA_DIR = 1536 // I/O Port Data Direction
.equ PORTA_DIRSET = 1537 // I/O Port Data Direction Set
.equ PORTA_DIRCLR = 1538 // I/O Port Data Direction Clear
.equ PORTA_DIRTGL = 1539 // I/O Port Data Direction Toggle
.equ PORTA_OUT = 1540 // I/O Port Output
.equ PORTA_OUTSET = 1541 // I/O Port Output Set
.equ PORTA_OUTCLR = 1542 // I/O Port Output Clear
.equ PORTA_OUTTGL = 1543 // I/O Port Output Toggle
.equ PORTA_IN = 1544 // I/O port Input
.equ PORTA_INTCTRL = 1545 // Interrupt Control Register
.equ PORTA_INT0MASK = 1546 // Port Interrupt 0 Mask
.equ PORTA_INT1MASK = 1547 // Port Interrupt 1 Mask
.equ PORTA_INTFLAGS = 1548 // Interrupt Flag Register
.equ PORTA_PIN0CTRL = 1552 // Pin 0 Control Register
.equ PORTA_PIN1CTRL = 1553 // Pin 1 Control Register
.equ PORTA_PIN2CTRL = 1554 // Pin 2 Control Register
.equ PORTA_PIN3CTRL = 1555 // Pin 3 Control Register
.equ PORTA_PIN4CTRL = 1556 // Pin 4 Control Register
.equ PORTA_PIN5CTRL = 1557 // Pin 5 Control Register
.equ PORTA_PIN6CTRL = 1558 // Pin 6 Control Register
.equ PORTA_PIN7CTRL = 1559 // Pin 7 Control Register
;***************************************************************************
;** PORTB - Port B
;***************************************************************************
.equ PORTB_DIR = 1568 // I/O Port Data Direction
.equ PORTB_DIRSET = 1569 // I/O Port Data Direction Set
.equ PORTB_DIRCLR = 1570 // I/O Port Data Direction Clear
.equ PORTB_DIRTGL = 1571 // I/O Port Data Direction Toggle
.equ PORTB_OUT = 1572 // I/O Port Output
.equ PORTB_OUTSET = 1573 // I/O Port Output Set
.equ PORTB_OUTCLR = 1574 // I/O Port Output Clear
.equ PORTB_OUTTGL = 1575 // I/O Port Output Toggle
.equ PORTB_IN = 1576 // I/O port Input
.equ PORTB_INTCTRL = 1577 // Interrupt Control Register
.equ PORTB_INT0MASK = 1578 // Port Interrupt 0 Mask
.equ PORTB_INT1MASK = 1579 // Port Interrupt 1 Mask
.equ PORTB_INTFLAGS = 1580 // Interrupt Flag Register
.equ PORTB_PIN0CTRL = 1584 // Pin 0 Control Register
.equ PORTB_PIN1CTRL = 1585 // Pin 1 Control Register
.equ PORTB_PIN2CTRL = 1586 // Pin 2 Control Register
.equ PORTB_PIN3CTRL = 1587 // Pin 3 Control Register
.equ PORTB_PIN4CTRL = 1588 // Pin 4 Control Register
.equ PORTB_PIN5CTRL = 1589 // Pin 5 Control Register
.equ PORTB_PIN6CTRL = 1590 // Pin 6 Control Register
.equ PORTB_PIN7CTRL = 1591 // Pin 7 Control Register
;***************************************************************************
;** PORTC - Port C
;***************************************************************************
.equ PORTC_DIR = 1600 // I/O Port Data Direction
.equ PORTC_DIRSET = 1601 // I/O Port Data Direction Set
.equ PORTC_DIRCLR = 1602 // I/O Port Data Direction Clear
.equ PORTC_DIRTGL = 1603 // I/O Port Data Direction Toggle
.equ PORTC_OUT = 1604 // I/O Port Output
.equ PORTC_OUTSET = 1605 // I/O Port Output Set
.equ PORTC_OUTCLR = 1606 // I/O Port Output Clear
.equ PORTC_OUTTGL = 1607 // I/O Port Output Toggle
.equ PORTC_IN = 1608 // I/O port Input
.equ PORTC_INTCTRL = 1609 // Interrupt Control Register
.equ PORTC_INT0MASK = 1610 // Port Interrupt 0 Mask
.equ PORTC_INT1MASK = 1611 // Port Interrupt 1 Mask
.equ PORTC_INTFLAGS = 1612 // Interrupt Flag Register
.equ PORTC_PIN0CTRL = 1616 // Pin 0 Control Register
.equ PORTC_PIN1CTRL = 1617 // Pin 1 Control Register
.equ PORTC_PIN2CTRL = 1618 // Pin 2 Control Register
.equ PORTC_PIN3CTRL = 1619 // Pin 3 Control Register
.equ PORTC_PIN4CTRL = 1620 // Pin 4 Control Register
.equ PORTC_PIN5CTRL = 1621 // Pin 5 Control Register
.equ PORTC_PIN6CTRL = 1622 // Pin 6 Control Register
.equ PORTC_PIN7CTRL = 1623 // Pin 7 Control Register
;***************************************************************************
;** PORTD - Port D
;***************************************************************************
.equ PORTD_DIR = 1632 // I/O Port Data Direction
.equ PORTD_DIRSET = 1633 // I/O Port Data Direction Set
.equ PORTD_DIRCLR = 1634 // I/O Port Data Direction Clear
.equ PORTD_DIRTGL = 1635 // I/O Port Data Direction Toggle
.equ PORTD_OUT = 1636 // I/O Port Output
.equ PORTD_OUTSET = 1637 // I/O Port Output Set
.equ PORTD_OUTCLR = 1638 // I/O Port Output Clear
.equ PORTD_OUTTGL = 1639 // I/O Port Output Toggle
.equ PORTD_IN = 1640 // I/O port Input
.equ PORTD_INTCTRL = 1641 // Interrupt Control Register
.equ PORTD_INT0MASK = 1642 // Port Interrupt 0 Mask
.equ PORTD_INT1MASK = 1643 // Port Interrupt 1 Mask
.equ PORTD_INTFLAGS = 1644 // Interrupt Flag Register
.equ PORTD_PIN0CTRL = 1648 // Pin 0 Control Register
.equ PORTD_PIN1CTRL = 1649 // Pin 1 Control Register
.equ PORTD_PIN2CTRL = 1650 // Pin 2 Control Register
.equ PORTD_PIN3CTRL = 1651 // Pin 3 Control Register
.equ PORTD_PIN4CTRL = 1652 // Pin 4 Control Register
.equ PORTD_PIN5CTRL = 1653 // Pin 5 Control Register
.equ PORTD_PIN6CTRL = 1654 // Pin 6 Control Register
.equ PORTD_PIN7CTRL = 1655 // Pin 7 Control Register
;***************************************************************************
;** PORTE - Port E
;***************************************************************************
.equ PORTE_DIR = 1664 // I/O Port Data Direction
.equ PORTE_DIRSET = 1665 // I/O Port Data Direction Set
.equ PORTE_DIRCLR = 1666 // I/O Port Data Direction Clear
.equ PORTE_DIRTGL = 1667 // I/O Port Data Direction Toggle
.equ PORTE_OUT = 1668 // I/O Port Output
.equ PORTE_OUTSET = 1669 // I/O Port Output Set
.equ PORTE_OUTCLR = 1670 // I/O Port Output Clear
.equ PORTE_OUTTGL = 1671 // I/O Port Output Toggle
.equ PORTE_IN = 1672 // I/O port Input
.equ PORTE_INTCTRL = 1673 // Interrupt Control Register
.equ PORTE_INT0MASK = 1674 // Port Interrupt 0 Mask
.equ PORTE_INT1MASK = 1675 // Port Interrupt 1 Mask
.equ PORTE_INTFLAGS = 1676 // Interrupt Flag Register
.equ PORTE_PIN0CTRL = 1680 // Pin 0 Control Register
.equ PORTE_PIN1CTRL = 1681 // Pin 1 Control Register
.equ PORTE_PIN2CTRL = 1682 // Pin 2 Control Register
.equ PORTE_PIN3CTRL = 1683 // Pin 3 Control Register
.equ PORTE_PIN4CTRL = 1684 // Pin 4 Control Register
.equ PORTE_PIN5CTRL = 1685 // Pin 5 Control Register
.equ PORTE_PIN6CTRL = 1686 // Pin 6 Control Register
.equ PORTE_PIN7CTRL = 1687 // Pin 7 Control Register
;***************************************************************************
;** PORTF - Port F
;***************************************************************************
.equ PORTF_DIR = 1696 // I/O Port Data Direction
.equ PORTF_DIRSET = 1697 // I/O Port Data Direction Set
.equ PORTF_DIRCLR = 1698 // I/O Port Data Direction Clear
.equ PORTF_DIRTGL = 1699 // I/O Port Data Direction Toggle
.equ PORTF_OUT = 1700 // I/O Port Output
.equ PORTF_OUTSET = 1701 // I/O Port Output Set
.equ PORTF_OUTCLR = 1702 // I/O Port Output Clear
.equ PORTF_OUTTGL = 1703 // I/O Port Output Toggle
.equ PORTF_IN = 1704 // I/O port Input
.equ PORTF_INTCTRL = 1705 // Interrupt Control Register
.equ PORTF_INT0MASK = 1706 // Port Interrupt 0 Mask
.equ PORTF_INT1MASK = 1707 // Port Interrupt 1 Mask
.equ PORTF_INTFLAGS = 1708 // Interrupt Flag Register
.equ PORTF_PIN0CTRL = 1712 // Pin 0 Control Register
.equ PORTF_PIN1CTRL = 1713 // Pin 1 Control Register
.equ PORTF_PIN2CTRL = 1714 // Pin 2 Control Register
.equ PORTF_PIN3CTRL = 1715 // Pin 3 Control Register
.equ PORTF_PIN4CTRL = 1716 // Pin 4 Control Register
.equ PORTF_PIN5CTRL = 1717 // Pin 5 Control Register
.equ PORTF_PIN6CTRL = 1718 // Pin 6 Control Register
.equ PORTF_PIN7CTRL = 1719 // Pin 7 Control Register
;***************************************************************************
;** PORTR - Port R
;***************************************************************************
.equ PORTR_DIR = 2016 // I/O Port Data Direction
.equ PORTR_DIRSET = 2017 // I/O Port Data Direction Set
.equ PORTR_DIRCLR = 2018 // I/O Port Data Direction Clear
.equ PORTR_DIRTGL = 2019 // I/O Port Data Direction Toggle
.equ PORTR_OUT = 2020 // I/O Port Output
.equ PORTR_OUTSET = 2021 // I/O Port Output Set
.equ PORTR_OUTCLR = 2022 // I/O Port Output Clear
.equ PORTR_OUTTGL = 2023 // I/O Port Output Toggle
.equ PORTR_IN = 2024 // I/O port Input
.equ PORTR_INTCTRL = 2025 // Interrupt Control Register
.equ PORTR_INT0MASK = 2026 // Port Interrupt 0 Mask
.equ PORTR_INT1MASK = 2027 // Port Interrupt 1 Mask
.equ PORTR_INTFLAGS = 2028 // Interrupt Flag Register
.equ PORTR_PIN0CTRL = 2032 // Pin 0 Control Register
.equ PORTR_PIN1CTRL = 2033 // Pin 1 Control Register
.equ PORTR_PIN2CTRL = 2034 // Pin 2 Control Register
.equ PORTR_PIN3CTRL = 2035 // Pin 3 Control Register
.equ PORTR_PIN4CTRL = 2036 // Pin 4 Control Register
.equ PORTR_PIN5CTRL = 2037 // Pin 5 Control Register
.equ PORTR_PIN6CTRL = 2038 // Pin 6 Control Register
.equ PORTR_PIN7CTRL = 2039 // Pin 7 Control Register
;***************************************************************************
;** TCC0 - Timer/Counter C0
;***************************************************************************
.equ TCC0_CTRLA = 2048 // Control Register A
.equ TCC0_CTRLB = 2049 // Control Register B
.equ TCC0_CTRLC = 2050 // Control register C
.equ TCC0_CTRLD = 2051 // Control Register D
.equ TCC0_CTRLE = 2052 // Control Register E
.equ TCC0_INTCTRLA = 2054 // Interrupt Control Register A
.equ TCC0_INTCTRLB = 2055 // Interrupt Control Register B
.equ TCC0_CTRLFCLR = 2056 // Control Register F Clear
.equ TCC0_CTRLFSET = 2057 // Control Register F Set
.equ TCC0_CTRLGCLR = 2058 // Control Register G Clear
.equ TCC0_CTRLGSET = 2059 // Control Register G Set
.equ TCC0_INTFLAGS = 2060 // Interrupt Flag Register
.equ TCC0_TEMP = 2063 // Temporary Register For 16-bit Access
.equ TCC0_CNT = 2080 // Count
.equ TCC0_PER = 2086 // Period
.equ TCC0_CCA = 2088 // Compare or Capture A
.equ TCC0_CCB = 2090 // Compare or Capture B
.equ TCC0_CCC = 2092 // Compare or Capture C
.equ TCC0_CCD = 2094 // Compare or Capture D
.equ TCC0_PERBUF = 2102 // Period Buffer
.equ TCC0_CCABUF = 2104 // Compare Or Capture A Buffer
.equ TCC0_CCBBUF = 2106 // Compare Or Capture B Buffer
.equ TCC0_CCCBUF = 2108 // Compare Or Capture C Buffer
.equ TCC0_CCDBUF = 2110 // Compare Or Capture D Buffer
;***************************************************************************
;** TCC1 - Timer/Counter C1
;***************************************************************************
.equ TCC1_CTRLA = 2112 // Control Register A
.equ TCC1_CTRLB = 2113 // Control Register B
.equ TCC1_CTRLC = 2114 // Control register C
.equ TCC1_CTRLD = 2115 // Control Register D
.equ TCC1_CTRLE = 2116 // Control Register E
.equ TCC1_INTCTRLA = 2118 // Interrupt Control Register A
.equ TCC1_INTCTRLB = 2119 // Interrupt Control Register B
.equ TCC1_CTRLFCLR = 2120 // Control Register F Clear
.equ TCC1_CTRLFSET = 2121 // Control Register F Set
.equ TCC1_CTRLGCLR = 2122 // Control Register G Clear
.equ TCC1_CTRLGSET = 2123 // Control Register G Set
.equ TCC1_INTFLAGS = 2124 // Interrupt Flag Register
.equ TCC1_TEMP = 2127 // Temporary Register For 16-bit Access
.equ TCC1_CNT = 2144 // Count
.equ TCC1_PER = 2150 // Period
.equ TCC1_CCA = 2152 // Compare or Capture A
.equ TCC1_CCB = 2154 // Compare or Capture B
.equ TCC1_PERBUF = 2166 // Period Buffer
.equ TCC1_CCABUF = 2168 // Compare Or Capture A Buffer
.equ TCC1_CCBBUF = 2170 // Compare Or Capture B Buffer
;***************************************************************************
;** AWEXC - Advanced Waveform Extension C
;***************************************************************************
.equ AWEXC_CTRL = 2176 // Control Register
.equ AWEXC_FDEMASK = 2178 // Fault Detection Event Mask
.equ AWEXC_FDCTRL = 2179 // Fault Detection Control Register
.equ AWEXC_STATUS = 2180 // Status Register
.equ AWEXC_DTBOTH = 2182 // Dead Time Both Sides
.equ AWEXC_DTBOTHBUF = 2183 // Dead Time Both Sides Buffer
.equ AWEXC_DTLS = 2184 // Dead Time Low Side
.equ AWEXC_DTHS = 2185 // Dead Time High Side
.equ AWEXC_DTLSBUF = 2186 // Dead Time Low Side Buffer
.equ AWEXC_DTHSBUF = 2187 // Dead Time High Side Buffer
.equ AWEXC_OUTOVEN = 2188 // Output Override Enable
;***************************************************************************
;** HIRESC - High-Resolution Extension C
;***************************************************************************
.equ HIRESC_CTRLA = 2192 // Control Register
;***************************************************************************
;** USARTC0 - Universal Asynchronous Receiver-Transmitter C0
;***************************************************************************
.equ USARTC0_DATA = 2208 // Data Register
.equ USARTC0_STATUS = 2209 // Status Register
.equ USARTC0_CTRLA = 2211 // Control Register A
.equ USARTC0_CTRLB = 2212 // Control Register B
.equ USARTC0_CTRLC = 2213 // Control Register C
.equ USARTC0_BAUDCTRLA = 2214 // Baud Rate Control Register A
.equ USARTC0_BAUDCTRLB = 2215 // Baud Rate Control Register B
;***************************************************************************
;** SPIC - Serial Peripheral Interface C
;***************************************************************************
.equ SPIC_CTRL = 2240 // Control Register
.equ SPIC_INTCTRL = 2241 // Interrupt Control Register
.equ SPIC_STATUS = 2242 // Status Register
.equ SPIC_DATA = 2243 // Data Register
;***************************************************************************
;** TCD0 - Timer/Counter D0
;***************************************************************************
.equ TCD0_CTRLA = 2304 // Control Register A
.equ TCD0_CTRLB = 2305 // Control Register B
.equ TCD0_CTRLC = 2306 // Control register C
.equ TCD0_CTRLD = 2307 // Control Register D
.equ TCD0_CTRLE = 2308 // Control Register E
.equ TCD0_INTCTRLA = 2310 // Interrupt Control Register A
.equ TCD0_INTCTRLB = 2311 // Interrupt Control Register B
.equ TCD0_CTRLFCLR = 2312 // Control Register F Clear
.equ TCD0_CTRLFSET = 2313 // Control Register F Set
.equ TCD0_CTRLGCLR = 2314 // Control Register G Clear
.equ TCD0_CTRLGSET = 2315 // Control Register G Set
.equ TCD0_INTFLAGS = 2316 // Interrupt Flag Register
.equ TCD0_TEMP = 2319 // Temporary Register For 16-bit Access
.equ TCD0_CNT = 2336 // Count
.equ TCD0_PER = 2342 // Period
.equ TCD0_CCA = 2344 // Compare or Capture A
.equ TCD0_CCB = 2346 // Compare or Capture B
.equ TCD0_CCC = 2348 // Compare or Capture C
.equ TCD0_CCD = 2350 // Compare or Capture D
.equ TCD0_PERBUF = 2358 // Period Buffer
.equ TCD0_CCABUF = 2360 // Compare Or Capture A Buffer
.equ TCD0_CCBBUF = 2362 // Compare Or Capture B Buffer
.equ TCD0_CCCBUF = 2364 // Compare Or Capture C Buffer
.equ TCD0_CCDBUF = 2366 // Compare Or Capture D Buffer
;***************************************************************************
;** USARTD0 - Universal Asynchronous Receiver-Transmitter D0
;***************************************************************************
.equ USARTD0_DATA = 2464 // Data Register
.equ USARTD0_STATUS = 2465 // Status Register
.equ USARTD0_CTRLA = 2467 // Control Register A
.equ USARTD0_CTRLB = 2468 // Control Register B
.equ USARTD0_CTRLC = 2469 // Control Register C
.equ USARTD0_BAUDCTRLA = 2470 // Baud Rate Control Register A
.equ USARTD0_BAUDCTRLB = 2471 // Baud Rate Control Register B
;***************************************************************************
;** SPID - Serial Peripheral Interface D
;***************************************************************************
.equ SPID_CTRL = 2496 // Control Register
.equ SPID_INTCTRL = 2497 // Interrupt Control Register
.equ SPID_STATUS = 2498 // Status Register
.equ SPID_DATA = 2499 // Data Register
;***************************************************************************
;** TCE0 - Timer/Counter E0
;***************************************************************************
.equ TCE0_CTRLA = 2560 // Control Register A
.equ TCE0_CTRLB = 2561 // Control Register B
.equ TCE0_CTRLC = 2562 // Control register C
.equ TCE0_CTRLD = 2563 // Control Register D
.equ TCE0_CTRLE = 2564 // Control Register E
.equ TCE0_INTCTRLA = 2566 // Interrupt Control Register A
.equ TCE0_INTCTRLB = 2567 // Interrupt Control Register B
.equ TCE0_CTRLFCLR = 2568 // Control Register F Clear
.equ TCE0_CTRLFSET = 2569 // Control Register F Set
.equ TCE0_CTRLGCLR = 2570 // Control Register G Clear
.equ TCE0_CTRLGSET = 2571 // Control Register G Set
.equ TCE0_INTFLAGS = 2572 // Interrupt Flag Register
.equ TCE0_TEMP = 2575 // Temporary Register For 16-bit Access
.equ TCE0_CNT = 2592 // Count
.equ TCE0_PER = 2598 // Period
.equ TCE0_CCA = 2600 // Compare or Capture A
.equ TCE0_CCB = 2602 // Compare or Capture B
.equ TCE0_CCC = 2604 // Compare or Capture C
.equ TCE0_CCD = 2606 // Compare or Capture D
.equ TCE0_PERBUF = 2614 // Period Buffer
.equ TCE0_CCABUF = 2616 // Compare Or Capture A Buffer
.equ TCE0_CCBBUF = 2618 // Compare Or Capture B Buffer
.equ TCE0_CCCBUF = 2620 // Compare Or Capture C Buffer
.equ TCE0_CCDBUF = 2622 // Compare Or Capture D Buffer
;***************************************************************************
;** AWEXE - Advanced Waveform Extension E
;***************************************************************************
.equ AWEXE_CTRL = 2688 // Control Register
.equ AWEXE_FDEMASK = 2690 // Fault Detection Event Mask
.equ AWEXE_FDCTRL = 2691 // Fault Detection Control Register
.equ AWEXE_STATUS = 2692 // Status Register
.equ AWEXE_DTBOTH = 2694 // Dead Time Both Sides
.equ AWEXE_DTBOTHBUF = 2695 // Dead Time Both Sides Buffer
.equ AWEXE_DTLS = 2696 // Dead Time Low Side
.equ AWEXE_DTHS = 2697 // Dead Time High Side
.equ AWEXE_DTLSBUF = 2698 // Dead Time Low Side Buffer
.equ AWEXE_DTHSBUF = 2699 // Dead Time High Side Buffer
.equ AWEXE_OUTOVEN = 2700 // Output Override Enable
;***************************************************************************
;** USARTE0 - Universal Asynchronous Receiver-Transmitter E0
;***************************************************************************
.equ USARTE0_DATA = 2720 // Data Register
.equ USARTE0_STATUS = 2721 // Status Register
.equ USARTE0_CTRLA = 2723 // Control Register A
.equ USARTE0_CTRLB = 2724 // Control Register B
.equ USARTE0_CTRLC = 2725 // Control Register C
.equ USARTE0_BAUDCTRLA = 2726 // Baud Rate Control Register A
.equ USARTE0_BAUDCTRLB = 2727 // Baud Rate Control Register B
;***************************************************************************
;** SPIE - Serial Peripheral Interface E
;***************************************************************************
.equ SPIE_CTRL = 2752 // Control Register
.equ SPIE_INTCTRL = 2753 // Interrupt Control Register
.equ SPIE_STATUS = 2754 // Status Register
.equ SPIE_DATA = 2755 // Data Register
;***************************************************************************
;** TCF0 - Timer/Counter F0
;***************************************************************************
.equ TCF0_CTRLA = 2816 // Control Register A
.equ TCF0_CTRLB = 2817 // Control Register B
.equ TCF0_CTRLC = 2818 // Control register C
.equ TCF0_CTRLD = 2819 // Control Register D
.equ TCF0_CTRLE = 2820 // Control Register E
.equ TCF0_INTCTRLA = 2822 // Interrupt Control Register A
.equ TCF0_INTCTRLB = 2823 // Interrupt Control Register B
.equ TCF0_CTRLFCLR = 2824 // Control Register F Clear
.equ TCF0_CTRLFSET = 2825 // Control Register F Set
.equ TCF0_CTRLGCLR = 2826 // Control Register G Clear
.equ TCF0_CTRLGSET = 2827 // Control Register G Set
.equ TCF0_INTFLAGS = 2828 // Interrupt Flag Register
.equ TCF0_TEMP = 2831 // Temporary Register For 16-bit Access
.equ TCF0_CNT = 2848 // Count
.equ TCF0_PER = 2854 // Period
.equ TCF0_CCA = 2856 // Compare or Capture A
.equ TCF0_CCB = 2858 // Compare or Capture B
.equ TCF0_CCC = 2860 // Compare or Capture C
.equ TCF0_CCD = 2862 // Compare or Capture D
.equ TCF0_PERBUF = 2870 // Period Buffer
.equ TCF0_CCABUF = 2872 // Compare Or Capture A Buffer
.equ TCF0_CCBBUF = 2874 // Compare Or Capture B Buffer
.equ TCF0_CCCBUF = 2876 // Compare Or Capture C Buffer
.equ TCF0_CCDBUF = 2878 // Compare Or Capture D Buffer
;***************************************************************************
;** IRCOM - IR Communication Module
;***************************************************************************
.equ IRCOM_CTRL = 2296 // Control Register
.equ IRCOM_TXPLCTRL = 2297 // IrDA Transmitter Pulse Length Control Register
.equ IRCOM_RXPLCTRL = 2298 // IrDA Receiver Pulse Length Control Register
; ***** ALL MODULE BASE ADRESSES *****************************************
.equ GPIO_base = 0x0000 // General Purpose IO Registers
.equ OCD_base = 0x002E // On-Chip Debug System
.equ CPU_base = 0x0030 // CPU Registers
.equ CLK_base = 0x0040 // Clock System
.equ SLEEP_base = 0x0048 // Sleep Controller
.equ OSC_base = 0x0050 // Oscillator Control
.equ DFLLRC32M_base = 0x0060 // DFLL for 32MHz RC Oscillator
.equ DFLLRC2M_base = 0x0068 // DFLL for 2MHz RC Oscillator
.equ PR_base = 0x0070 // Power Reduction
.equ RST_base = 0x0078 // Reset Controller
.equ WDT_base = 0x0080 // Watch-Dog Timer
.equ MCU_base = 0x0090 // MCU Control
.equ PMIC_base = 0x00A0 // Programmable Interrupt Controller
.equ EVSYS_base = 0x0180 // Event System
.equ NVM_base = 0x01C0 // Non Volatile Memory Controller
.equ ACA_base = 0x0380 // Analog Comparator A
.equ ADCA_base = 0x0200 // Analog to Digital Converter A
.equ RTC_base = 0x0400 // Real-Time Counter
.equ TWIC_base = 0x480 // Two-Wire Interface C
.equ PORTCFG_base = 0x00B0 // Port Configuration
.equ VPORT0_base = 0x0010 // Virtual Port 0
.equ VPORT1_base = 0x0014 // Virtual Port 1
.equ VPORT2_base = 0x0018 // Virtual Port 2
.equ VPORT3_base = 0x001C // Virtual Port 3
.equ PORTA_base = 0x0600 // Port A
.equ PORTB_base = 0x0620 // Port B
.equ PORTC_base = 0x0640 // Port C
.equ PORTD_base = 0x0660 // Port D
.equ PORTE_base = 0x0680 // Port E
.equ PORTF_base = 0x06A0 // Port F
.equ PORTR_base = 0x07E0 // Port R
.equ TCC0_base = 0x800 // Timer/Counter C0
.equ TCC1_base = 0x840 // Timer/Counter C1
.equ AWEXC_base = 0x880 // Advanced Waveform Extension C
.equ HIRESC_base = 0x890 // High-Resolution Extension C
.equ USARTC0_base = 0x8A0 // Universal Asynchronous Receiver-Transmitter C0
.equ SPIC_base = 0x8C0 // Serial Peripheral Interface C
.equ TCD0_base = 0x900 // Timer/Counter D0
.equ USARTD0_base = 0x9A0 // Universal Asynchronous Receiver-Transmitter D0
.equ SPID_base = 0x9C0 // Serial Peripheral Interface D
.equ TCE0_base = 0xA00 // Timer/Counter E0
.equ AWEXE_base = 0xA80 // Advanced Waveform Extension E
.equ USARTE0_base = 0xAA0 // Universal Asynchronous Receiver-Transmitter E0
.equ SPIE_base = 0xAC0 // Serial Peripheral Interface E
.equ TCF0_base = 0xB00 // Timer/Counter F0
.equ IRCOM_base = 0x8F8 // IR Communication Module
; ***** IO REGISTER OFFSETS **********************************************
;***************************************************************************
;** GPIO - General Purpose IO
;***************************************************************************/
.equ GPIO_GPIOR0_offset = 0x00 // General Purpose IO Register 0
.equ GPIO_GPIOR1_offset = 0x01 // General Purpose IO Register 1
.equ GPIO_GPIOR2_offset = 0x02 // General Purpose IO Register 2
.equ GPIO_GPIOR3_offset = 0x03 // General Purpose IO Register 3
;***************************************************************************
;** XOCD - On-Chip Debug System
;***************************************************************************/
.equ OCD_OCDR0_offset = 0x00 // OCD Register 0
.equ OCD_OCDR1_offset = 0x01 // OCD Register 1
;***************************************************************************
;** CPU - CPU
;***************************************************************************/
.equ CPU_CCP_offset = 0x04 // Configuration Change Protection
.equ CPU_RAMPD_offset = 0x08 // Ramp D
.equ CPU_RAMPX_offset = 0x09 // Ramp X
.equ CPU_RAMPY_offset = 0x0A // Ramp Y
.equ CPU_RAMPZ_offset = 0x0B // Ramp Z
.equ CPU_EIND_offset = 0x0C // Extended Indirect Jump
.equ CPU_SPL_offset = 0x0D // Stack Pointer Low
.equ CPU_SPH_offset = 0x0E // Stack Pointer High
.equ CPU_SREG_offset = 0x0F // Status Register
;***************************************************************************
;** CLK - Clock System
;***************************************************************************/
.equ CLK_CTRL_offset = 0x00 // Control Register
.equ CLK_PSCTRL_offset = 0x01 // Prescaler Control Register
.equ CLK_LOCK_offset = 0x02 // Lock register
.equ CLK_RTCCTRL_offset = 0x03 // RTC Control Register
.equ PR_PRGEN_offset = 0x00 // General Power Reduction
.equ PR_PRPA_offset = 0x01 // Power Reduction Port A
.equ PR_PRPB_offset = 0x02 // Power Reduction Port B
.equ PR_PRPC_offset = 0x03 // Power Reduction Port C
.equ PR_PRPD_offset = 0x04 // Power Reduction Port D
.equ PR_PRPE_offset = 0x05 // Power Reduction Port E
.equ PR_PRPF_offset = 0x06 // Power Reduction Port F
;***************************************************************************
;** SLEEP - Sleep Controller
;***************************************************************************/
.equ SLEEP_CTRL_offset = 0x00 // Control Register
;***************************************************************************
;** OSC - Oscillator
;***************************************************************************/
.equ OSC_CTRL_offset = 0x00 // Control Register
.equ OSC_STATUS_offset = 0x01 // Status Register
.equ OSC_XOSCCTRL_offset = 0x02 // External Oscillator Control Register
.equ OSC_XOSCFAIL_offset = 0x03 // External Oscillator Failure Detection Register
.equ OSC_RC32KCAL_offset = 0x04 // 32kHz Internal Oscillator Calibration Register
.equ OSC_PLLCTRL_offset = 0x05 // PLL Control REgister
.equ OSC_DFLLCTRL_offset = 0x06 // DFLL Control Register
;***************************************************************************
;** DFLL - DFLL
;***************************************************************************/
.equ DFLL_CTRL_offset = 0x00 // Control Register
.equ DFLL_CALA_offset = 0x02 // Calibration Register A
.equ DFLL_CALB_offset = 0x03 // Calibration Register B
.equ DFLL_COMP0_offset = 0x04 // Oscillator Compare Register 0
.equ DFLL_COMP1_offset = 0x05 // Oscillator Compare Register 1
.equ DFLL_COMP2_offset = 0x06 // Oscillator Compare Register 2
;***************************************************************************
;** RST - Reset
;***************************************************************************/
.equ RST_STATUS_offset = 0x00 // Status Register
.equ RST_CTRL_offset = 0x01 // Control Register
;***************************************************************************
;** WDT - Watch-Dog Timer
;***************************************************************************/
.equ WDT_CTRL_offset = 0x00 // Control
.equ WDT_WINCTRL_offset = 0x01 // Windowed Mode Control
.equ WDT_STATUS_offset = 0x02 // Status
;***************************************************************************
;** MCU - MCU Control
;***************************************************************************/
.equ MCU_DEVID0_offset = 0x00 // Device ID byte 0
.equ MCU_DEVID1_offset = 0x01 // Device ID byte 1
.equ MCU_DEVID2_offset = 0x02 // Device ID byte 2
.equ MCU_REVID_offset = 0x03 // Revision ID
.equ MCU_JTAGUID_offset = 0x04 // JTAG User ID
.equ MCU_MCUCR_offset = 0x06 // MCU Control
.equ MCU_EVSYSLOCK_offset = 0x08 // Event System Lock
.equ MCU_AWEXLOCK_offset = 0x09 // AWEX Lock
;***************************************************************************
;** PMIC - Programmable Multi-level Interrupt Controller
;***************************************************************************/
.equ PMIC_STATUS_offset = 0x00 // Status Register
.equ PMIC_INTPRI_offset = 0x01 // Interrupt Priority
.equ PMIC_CTRL_offset = 0x02 // Control Register
;***************************************************************************
;** EVSYS - Event System
;***************************************************************************/
.equ EVSYS_CH0MUX_offset = 0x00 // Event Channel 0 Multiplexer
.equ EVSYS_CH1MUX_offset = 0x01 // Event Channel 1 Multiplexer
.equ EVSYS_CH2MUX_offset = 0x02 // Event Channel 2 Multiplexer
.equ EVSYS_CH3MUX_offset = 0x03 // Event Channel 3 Multiplexer
.equ EVSYS_CH0CTRL_offset = 0x08 // Channel 0 Control Register
.equ EVSYS_CH1CTRL_offset = 0x09 // Channel 1 Control Register
.equ EVSYS_CH2CTRL_offset = 0x0A // Channel 2 Control Register
.equ EVSYS_CH3CTRL_offset = 0x0B // Channel 3 Control Register
.equ EVSYS_STROBE_offset = 0x10 // Event Strobe
.equ EVSYS_DATA_offset = 0x11 // Event Data
;***************************************************************************
;** NVM - Non Volatile Memory Controller
;***************************************************************************/
.equ NVM_ADDR0_offset = 0x00 // Address Register 0
.equ NVM_ADDR1_offset = 0x01 // Address Register 1
.equ NVM_ADDR2_offset = 0x02 // Address Register 2
.equ NVM_DATA0_offset = 0x04 // Data Register 0
.equ NVM_DATA1_offset = 0x05 // Data Register 1
.equ NVM_DATA2_offset = 0x06 // Data Register 2
.equ NVM_CMD_offset = 0x0A // Command
.equ NVM_CTRLA_offset = 0x0B // Control Register A
.equ NVM_CTRLB_offset = 0x0C // Control Register B
.equ NVM_INTCTRL_offset = 0x0D // Interrupt Control
.equ NVM_STATUS_offset = 0x0F // Status
.equ NVM_LOCKBITS_offset = 0x10 // Lock Bits
.equ NVM_LOCKBITS_LOCKBITS_offset = 0x00 // Lock Bits
.equ NVM_FUSES_FUSEBYTE0_offset = 0x00 // User ID
.equ NVM_FUSES_FUSEBYTE1_offset = 0x01 // Watchdog Configuration
.equ NVM_FUSES_FUSEBYTE2_offset = 0x02 // Reset Configuration
.equ NVM_FUSES_FUSEBYTE4_offset = 0x04 // Start-up Configuration
.equ NVM_FUSES_FUSEBYTE5_offset = 0x05 // EESAVE and BOD Level
.equ NVM_PROD_SIGNATURES_RCOSC2M_offset = 0x00 // RCOSC 2MHz Calibration Value
.equ NVM_PROD_SIGNATURES_RCOSC32K_offset = 0x02 // RCOSC 32kHz Calibration Value
.equ NVM_PROD_SIGNATURES_RCOSC32M_offset = 0x03 // RCOSC 32MHz Calibration Value
.equ NVM_PROD_SIGNATURES_LOTNUM0_offset = 0x08 // Lot Number Byte 0, ASCII
.equ NVM_PROD_SIGNATURES_LOTNUM1_offset = 0x09 // Lot Number Byte 1, ASCII
.equ NVM_PROD_SIGNATURES_LOTNUM2_offset = 0x0A // Lot Number Byte 2, ASCII
.equ NVM_PROD_SIGNATURES_LOTNUM3_offset = 0x0B // Lot Number Byte 3, ASCII
.equ NVM_PROD_SIGNATURES_LOTNUM4_offset = 0x0C // Lot Number Byte 4, ASCII
.equ NVM_PROD_SIGNATURES_LOTNUM5_offset = 0x0D // Lot Number Byte 5, ASCII
.equ NVM_PROD_SIGNATURES_WAFNUM_offset = 0x10 // Wafer Number
.equ NVM_PROD_SIGNATURES_COORDX0_offset = 0x12 // Wafer Coordinate X Byte 0
.equ NVM_PROD_SIGNATURES_COORDX1_offset = 0x13 // Wafer Coordinate X Byte 1
.equ NVM_PROD_SIGNATURES_COORDY0_offset = 0x14 // Wafer Coordinate Y Byte 0
.equ NVM_PROD_SIGNATURES_COORDY1_offset = 0x15 // Wafer Coordinate Y Byte 1
.equ NVM_PROD_SIGNATURES_ADCACAL0_offset = 0x20 // ADCA Calibration Byte 0
.equ NVM_PROD_SIGNATURES_ADCACAL1_offset = 0x21 // ADCA Calibration Byte 1
.equ NVM_PROD_SIGNATURES_ADCBCAL0_offset = 0x24 // ADCB Calibration Byte 0
.equ NVM_PROD_SIGNATURES_ADCBCAL1_offset = 0x25 // ADCB Calibration Byte 1
.equ NVM_PROD_SIGNATURES_TEMPSENSE0_offset = 0x2E // Temperature Sensor Calibration Byte 0
.equ NVM_PROD_SIGNATURES_TEMPSENSE1_offset = 0x2F // Temperature Sensor Calibration Byte 0
;***************************************************************************
;** AC - Analog Comparator
;***************************************************************************/
.equ AC_AC0CTRL_offset = 0x00 // Analog Comparator 0 Control
.equ AC_AC1CTRL_offset = 0x01 // Analog Comparator 1 Control
.equ AC_AC0MUXCTRL_offset = 0x02 // Analog Comparator 0 MUX Control
.equ AC_AC1MUXCTRL_offset = 0x03 // Analog Comparator 1 MUX Control
.equ AC_CTRLA_offset = 0x04 // Control Register A
.equ AC_CTRLB_offset = 0x05 // Control Register B
.equ AC_WINCTRL_offset = 0x06 // Window Mode Control
.equ AC_STATUS_offset = 0x07 // Status
;***************************************************************************
;** ADC - Analog/Digital Converter
;***************************************************************************/
.equ ADC_CTRLA_offset = 0x00 // Control Register A
.equ ADC_CTRLB_offset = 0x01 // Control Register B
.equ ADC_REFCTRL_offset = 0x02 // Reference Control
.equ ADC_EVCTRL_offset = 0x03 // Event Control
.equ ADC_PRESCALER_offset = 0x04 // Clock Prescaler
.equ ADC_INTFLAGS_offset = 0x06 // Interrupt Flags
.equ ADC_TEMP_offset = 0x07 // Temporary Register
.equ ADC_CAL_offset = 0x0C // Calibration Value
.equ ADC_CH0RES_offset = 0x10 // Channel 0 Result
.equ ADC_CMP_offset = 0x18 // Compare Value
.equ ADC_CH0_offset = 0x20 // ADC Channel 0
.equ ADC_CH_CTRL_offset = 0x00 // Control Register
.equ ADC_CH_MUXCTRL_offset = 0x01 // MUX Control
.equ ADC_CH_INTCTRL_offset = 0x02 // Channel Interrupt Control Register
.equ ADC_CH_INTFLAGS_offset = 0x03 // Interrupt Flags
.equ ADC_CH_RES_offset = 0x04 // Channel Result
;***************************************************************************
;** RTC - Real-Time Clounter
;***************************************************************************/
.equ RTC_CTRL_offset = 0x00 // Control Register
.equ RTC_STATUS_offset = 0x01 // Status Register
.equ RTC_INTCTRL_offset = 0x02 // Interrupt Control Register
.equ RTC_INTFLAGS_offset = 0x03 // Interrupt Flags
.equ RTC_TEMP_offset = 0x04 // Temporary register
.equ RTC_CNT_offset = 0x08 // Count Register
.equ RTC_PER_offset = 0x0A // Period Register
.equ RTC_COMP_offset = 0x0C // Compare Register
;***************************************************************************
;** EBI - External Bus Interface
;***************************************************************************/
.equ EBI_CS_CTRLA_offset = 0x00 // Chip Select Control Register A
.equ EBI_CS_CTRLB_offset = 0x01 // Chip Select Control Register B
.equ EBI_CS_BASEADDR_offset = 0x02 // Chip Select Base Address
.equ EBI_CTRL_offset = 0x00 // Control
.equ EBI_SDRAMCTRLA_offset = 0x01 // SDRAM Control Register A
.equ EBI_REFRESH_offset = 0x04 // SDRAM Refresh Period
.equ EBI_INITDLY_offset = 0x06 // SDRAM Initialization Delay
.equ EBI_SDRAMCTRLB_offset = 0x08 // SDRAM Control Register B
.equ EBI_SDRAMCTRLC_offset = 0x09 // SDRAM Control Register C
.equ EBI_CS0_offset = 0x10 // Chip Select 0
.equ EBI_CS1_offset = 0x14 // Chip Select 1
.equ EBI_CS2_offset = 0x18 // Chip Select 2
.equ EBI_CS3_offset = 0x1C // Chip Select 3
;***************************************************************************
;** TWI - Two-Wire Interface
;***************************************************************************/
.equ TWI_MASTER_CTRLA_offset = 0x00 // Control Register A
.equ TWI_MASTER_CTRLB_offset = 0x01 // Control Register B
.equ TWI_MASTER_CTRLC_offset = 0x02 // Control Register C
.equ TWI_MASTER_STATUS_offset = 0x03 // Status Register
.equ TWI_MASTER_BAUD_offset = 0x04 // Baurd Rate Control Register
.equ TWI_MASTER_ADDR_offset = 0x05 // Address Register
.equ TWI_MASTER_DATA_offset = 0x06 // Data Register
.equ TWI_SLAVE_CTRLA_offset = 0x00 // Control Register A
.equ TWI_SLAVE_CTRLB_offset = 0x01 // Control Register B
.equ TWI_SLAVE_STATUS_offset = 0x02 // Status Register
.equ TWI_SLAVE_ADDR_offset = 0x03 // Address Register
.equ TWI_SLAVE_DATA_offset = 0x04 // Data Register
.equ TWI_SLAVE_ADDRMASK_offset = 0x05 // Address Mask Register
.equ TWI_CTRL_offset = 0x00 // TWI Common Control Register
.equ TWI_MASTER_offset = 0x0001 // TWI master module
.equ TWI_SLAVE_offset = 0x0008 // TWI slave module
;***************************************************************************
;** PORT - Port Configuration
;***************************************************************************/
.equ PORTCFG_MPCMASK_offset = 0x00 // Multi-pin Configuration Mask
.equ PORTCFG_VPCTRLA_offset = 0x02 // Virtual Port Control Register A
.equ PORTCFG_VPCTRLB_offset = 0x03 // Virtual Port Control Register B
.equ PORTCFG_CLKEVOUT_offset = 0x04 // Clock and Event Out Register
.equ VPORT_DIR_offset = 0x00 // I/O Port Data Direction
.equ VPORT_OUT_offset = 0x01 // I/O Port Output
.equ VPORT_IN_offset = 0x02 // I/O Port Input
.equ VPORT_INTFLAGS_offset = 0x03 // Interrupt Flag Register
.equ PORT_DIR_offset = 0x00 // I/O Port Data Direction
.equ PORT_DIRSET_offset = 0x01 // I/O Port Data Direction Set
.equ PORT_DIRCLR_offset = 0x02 // I/O Port Data Direction Clear
.equ PORT_DIRTGL_offset = 0x03 // I/O Port Data Direction Toggle
.equ PORT_OUT_offset = 0x04 // I/O Port Output
.equ PORT_OUTSET_offset = 0x05 // I/O Port Output Set
.equ PORT_OUTCLR_offset = 0x06 // I/O Port Output Clear
.equ PORT_OUTTGL_offset = 0x07 // I/O Port Output Toggle
.equ PORT_IN_offset = 0x08 // I/O port Input
.equ PORT_INTCTRL_offset = 0x09 // Interrupt Control Register
.equ PORT_INT0MASK_offset = 0x0A // Port Interrupt 0 Mask
.equ PORT_INT1MASK_offset = 0x0B // Port Interrupt 1 Mask
.equ PORT_INTFLAGS_offset = 0x0C // Interrupt Flag Register
.equ PORT_PIN0CTRL_offset = 0x10 // Pin 0 Control Register
.equ PORT_PIN1CTRL_offset = 0x11 // Pin 1 Control Register
.equ PORT_PIN2CTRL_offset = 0x12 // Pin 2 Control Register
.equ PORT_PIN3CTRL_offset = 0x13 // Pin 3 Control Register
.equ PORT_PIN4CTRL_offset = 0x14 // Pin 4 Control Register
.equ PORT_PIN5CTRL_offset = 0x15 // Pin 5 Control Register
.equ PORT_PIN6CTRL_offset = 0x16 // Pin 6 Control Register
.equ PORT_PIN7CTRL_offset = 0x17 // Pin 7 Control Register
;***************************************************************************
;** TC - 16-bit Timer/Counter With PWM
;***************************************************************************/
.equ TC0_CTRLA_offset = 0x00 // Control Register A
.equ TC0_CTRLB_offset = 0x01 // Control Register B
.equ TC0_CTRLC_offset = 0x02 // Control register C
.equ TC0_CTRLD_offset = 0x03 // Control Register D
.equ TC0_CTRLE_offset = 0x04 // Control Register E
.equ TC0_INTCTRLA_offset = 0x06 // Interrupt Control Register A
.equ TC0_INTCTRLB_offset = 0x07 // Interrupt Control Register B
.equ TC0_CTRLFCLR_offset = 0x08 // Control Register F Clear
.equ TC0_CTRLFSET_offset = 0x09 // Control Register F Set
.equ TC0_CTRLGCLR_offset = 0x0A // Control Register G Clear
.equ TC0_CTRLGSET_offset = 0x0B // Control Register G Set
.equ TC0_INTFLAGS_offset = 0x0C // Interrupt Flag Register
.equ TC0_TEMP_offset = 0x0F // Temporary Register For 16-bit Access
.equ TC0_CNT_offset = 0x20 // Count
.equ TC0_PER_offset = 0x26 // Period
.equ TC0_CCA_offset = 0x28 // Compare or Capture A
.equ TC0_CCB_offset = 0x2A // Compare or Capture B
.equ TC0_CCC_offset = 0x2C // Compare or Capture C
.equ TC0_CCD_offset = 0x2E // Compare or Capture D
.equ TC0_PERBUF_offset = 0x36 // Period Buffer
.equ TC0_CCABUF_offset = 0x38 // Compare Or Capture A Buffer
.equ TC0_CCBBUF_offset = 0x3A // Compare Or Capture B Buffer
.equ TC0_CCCBUF_offset = 0x3C // Compare Or Capture C Buffer
.equ TC0_CCDBUF_offset = 0x3E // Compare Or Capture D Buffer
.equ TC1_CTRLA_offset = 0x00 // Control Register A
.equ TC1_CTRLB_offset = 0x01 // Control Register B
.equ TC1_CTRLC_offset = 0x02 // Control register C
.equ TC1_CTRLD_offset = 0x03 // Control Register D
.equ TC1_CTRLE_offset = 0x04 // Control Register E
.equ TC1_INTCTRLA_offset = 0x06 // Interrupt Control Register A
.equ TC1_INTCTRLB_offset = 0x07 // Interrupt Control Register B
.equ TC1_CTRLFCLR_offset = 0x08 // Control Register F Clear
.equ TC1_CTRLFSET_offset = 0x09 // Control Register F Set
.equ TC1_CTRLGCLR_offset = 0x0A // Control Register G Clear
.equ TC1_CTRLGSET_offset = 0x0B // Control Register G Set
.equ TC1_INTFLAGS_offset = 0x0C // Interrupt Flag Register
.equ TC1_TEMP_offset = 0x0F // Temporary Register For 16-bit Access
.equ TC1_CNT_offset = 0x20 // Count
.equ TC1_PER_offset = 0x26 // Period
.equ TC1_CCA_offset = 0x28 // Compare or Capture A
.equ TC1_CCB_offset = 0x2A // Compare or Capture B
.equ TC1_PERBUF_offset = 0x36 // Period Buffer
.equ TC1_CCABUF_offset = 0x38 // Compare Or Capture A Buffer
.equ TC1_CCBBUF_offset = 0x3A // Compare Or Capture B Buffer
.equ AWEX_CTRL_offset = 0x00 // Control Register
.equ AWEX_FDEMASK_offset = 0x02 // Fault Detection Event Mask
.equ AWEX_FDCTRL_offset = 0x03 // Fault Detection Control Register
.equ AWEX_STATUS_offset = 0x04 // Status Register
.equ AWEX_DTBOTH_offset = 0x06 // Dead Time Both Sides
.equ AWEX_DTBOTHBUF_offset = 0x07 // Dead Time Both Sides Buffer
.equ AWEX_DTLS_offset = 0x08 // Dead Time Low Side
.equ AWEX_DTHS_offset = 0x09 // Dead Time High Side
.equ AWEX_DTLSBUF_offset = 0x0A // Dead Time Low Side Buffer
.equ AWEX_DTHSBUF_offset = 0x0B // Dead Time High Side Buffer
.equ AWEX_OUTOVEN_offset = 0x0C // Output Override Enable
.equ HIRES_CTRLA_offset = 0x00 // Control Register
;***************************************************************************
;** USART - Universal Asynchronous Receiver-Transmitter
;***************************************************************************/
.equ USART_DATA_offset = 0x00 // Data Register
.equ USART_STATUS_offset = 0x01 // Status Register
.equ USART_CTRLA_offset = 0x03 // Control Register A
.equ USART_CTRLB_offset = 0x04 // Control Register B
.equ USART_CTRLC_offset = 0x05 // Control Register C
.equ USART_BAUDCTRLA_offset = 0x06 // Baud Rate Control Register A
.equ USART_BAUDCTRLB_offset = 0x07 // Baud Rate Control Register B
;***************************************************************************
;** SPI - Serial Peripheral Interface
;***************************************************************************/
.equ SPI_CTRL_offset = 0x0 // Control Register
.equ SPI_INTCTRL_offset = 0x01 // Interrupt Control Register
.equ SPI_STATUS_offset = 0x02 // Status Register
.equ SPI_DATA_offset = 0x03 // Data Register
;***************************************************************************
;** IRCOM - IR Communication Module
;***************************************************************************/
.equ IRCOM_CTRL_offset = 0x00 // Control Register
.equ IRCOM_TXPLCTRL_offset = 0x01 // IrDA Transmitter Pulse Length Control Register
.equ IRCOM_RXPLCTRL_offset = 0x02 // IrDA Receiver Pulse Length Control Register
; ***** LOCKBIT REGISTER LOCATIONS ***************************************
;***************************************************************************
;** LOCKBIT - Lockbits
;***************************************************************************
.equ LOCKBIT_LOCKBITS = 0 // Lock Bits
; ***** FUSE REGISTER LOCATIONS ******************************************
;***************************************************************************
;** FUSE - Fuses
;***************************************************************************
.equ FUSE_FUSEBYTE0 = 0 // User ID
.equ FUSE_FUSEBYTE1 = 1 // Watchdog Configuration
.equ FUSE_FUSEBYTE2 = 2 // Reset Configuration
.equ FUSE_FUSEBYTE4 = 4 // Start-up Configuration
.equ FUSE_FUSEBYTE5 = 5 // EESAVE and BOD Level
; ***** BIT AND VALUE DEFINITIONS ****************************************
;***************************************************************************
;** GPIO - General Purpose IO
;***************************************************************************/
;***************************************************************************
;** XOCD - On-Chip Debug System
;***************************************************************************/
; OCD_OCDR1 masks
.equ OCD_OCDRD_bm = 0x01 ; OCDR Dirty bit mask
.equ OCD_OCDRD_bp = 0 ; OCDR Dirty bit position
;***************************************************************************
;** CPU - CPU
;***************************************************************************/
; CPU_CCP masks
.equ CPU_CCP_gm = 0xFF ; CCP signature group mask
.equ CPU_CCP_gp = 0 ; CCP signature group position
.equ CPU_CCP0_bm = (1<<0) ; CCP signature bit 0 mask
.equ CPU_CCP0_bp = 0 ; CCP signature bit 0 position
.equ CPU_CCP1_bm = (1<<1) ; CCP signature bit 1 mask
.equ CPU_CCP1_bp = 1 ; CCP signature bit 1 position
.equ CPU_CCP2_bm = (1<<2) ; CCP signature bit 2 mask
.equ CPU_CCP2_bp = 2 ; CCP signature bit 2 position
.equ CPU_CCP3_bm = (1<<3) ; CCP signature bit 3 mask
.equ CPU_CCP3_bp = 3 ; CCP signature bit 3 position
.equ CPU_CCP4_bm = (1<<4) ; CCP signature bit 4 mask
.equ CPU_CCP4_bp = 4 ; CCP signature bit 4 position
.equ CPU_CCP5_bm = (1<<5) ; CCP signature bit 5 mask
.equ CPU_CCP5_bp = 5 ; CCP signature bit 5 position
.equ CPU_CCP6_bm = (1<<6) ; CCP signature bit 6 mask
.equ CPU_CCP6_bp = 6 ; CCP signature bit 6 position
.equ CPU_CCP7_bm = (1<<7) ; CCP signature bit 7 mask
.equ CPU_CCP7_bp = 7 ; CCP signature bit 7 position
; CPU_SREG masks
.equ CPU_I_bm = 0x80 ; Global Interrupt Enable Flag bit mask
.equ CPU_I_bp = 7 ; Global Interrupt Enable Flag bit position
.equ CPU_T_bm = 0x40 ; Transfer Bit bit mask
.equ CPU_T_bp = 6 ; Transfer Bit bit position
.equ CPU_H_bm = 0x20 ; Half Carry Flag bit mask
.equ CPU_H_bp = 5 ; Half Carry Flag bit position
.equ CPU_S_bm = 0x10 ; N Exclusive Or V Flag bit mask
.equ CPU_S_bp = 4 ; N Exclusive Or V Flag bit position
.equ CPU_V_bm = 0x08 ; Two's Complement Overflow Flag bit mask
.equ CPU_V_bp = 3 ; Two's Complement Overflow Flag bit position
.equ CPU_N_bm = 0x04 ; Negative Flag bit mask
.equ CPU_N_bp = 2 ; Negative Flag bit position
.equ CPU_Z_bm = 0x02 ; Zero Flag bit mask
.equ CPU_Z_bp = 1 ; Zero Flag bit position
.equ CPU_C_bm = 0x01 ; Carry Flag bit mask
.equ CPU_C_bp = 0 ; Carry Flag bit position
; CCP signatures
.equ CCP_SPM_gc = (0x9D<<0) ; SPM Instruction Protection
.equ CCP_IOREG_gc = (0xD8<<0) ; IO Register Protection
;***************************************************************************
;** CLK - Clock System
;***************************************************************************/
; CLK_CTRL masks
.equ CLK_SCLKSEL_gm = 0x07 ; System Clock Selection group mask
.equ CLK_SCLKSEL_gp = 0 ; System Clock Selection group position
.equ CLK_SCLKSEL0_bm = (1<<0) ; System Clock Selection bit 0 mask
.equ CLK_SCLKSEL0_bp = 0 ; System Clock Selection bit 0 position
.equ CLK_SCLKSEL1_bm = (1<<1) ; System Clock Selection bit 1 mask
.equ CLK_SCLKSEL1_bp = 1 ; System Clock Selection bit 1 position
.equ CLK_SCLKSEL2_bm = (1<<2) ; System Clock Selection bit 2 mask
.equ CLK_SCLKSEL2_bp = 2 ; System Clock Selection bit 2 position
; CLK_PSCTRL masks
.equ CLK_PSADIV_gm = 0x7C ; Prescaler A Division Factor group mask
.equ CLK_PSADIV_gp = 2 ; Prescaler A Division Factor group position
.equ CLK_PSADIV0_bm = (1<<2) ; Prescaler A Division Factor bit 0 mask
.equ CLK_PSADIV0_bp = 2 ; Prescaler A Division Factor bit 0 position
.equ CLK_PSADIV1_bm = (1<<3) ; Prescaler A Division Factor bit 1 mask
.equ CLK_PSADIV1_bp = 3 ; Prescaler A Division Factor bit 1 position
.equ CLK_PSADIV2_bm = (1<<4) ; Prescaler A Division Factor bit 2 mask
.equ CLK_PSADIV2_bp = 4 ; Prescaler A Division Factor bit 2 position
.equ CLK_PSADIV3_bm = (1<<5) ; Prescaler A Division Factor bit 3 mask
.equ CLK_PSADIV3_bp = 5 ; Prescaler A Division Factor bit 3 position
.equ CLK_PSADIV4_bm = (1<<6) ; Prescaler A Division Factor bit 4 mask
.equ CLK_PSADIV4_bp = 6 ; Prescaler A Division Factor bit 4 position
.equ CLK_PSBCDIV_gm = 0x03 ; Prescaler B and C Division factor group mask
.equ CLK_PSBCDIV_gp = 0 ; Prescaler B and C Division factor group position
.equ CLK_PSBCDIV0_bm = (1<<0) ; Prescaler B and C Division factor bit 0 mask
.equ CLK_PSBCDIV0_bp = 0 ; Prescaler B and C Division factor bit 0 position
.equ CLK_PSBCDIV1_bm = (1<<1) ; Prescaler B and C Division factor bit 1 mask
.equ CLK_PSBCDIV1_bp = 1 ; Prescaler B and C Division factor bit 1 position
; CLK_LOCK masks
.equ CLK_LOCK_bm = 0x01 ; Clock System Lock bit mask
.equ CLK_LOCK_bp = 0 ; Clock System Lock bit position
; CLK_RTCCTRL masks
.equ CLK_RTCSRC_gm = 0x0E ; RTC Clock Source group mask
.equ CLK_RTCSRC_gp = 1 ; RTC Clock Source group position
.equ CLK_RTCSRC0_bm = (1<<1) ; RTC Clock Source bit 0 mask
.equ CLK_RTCSRC0_bp = 1 ; RTC Clock Source bit 0 position
.equ CLK_RTCSRC1_bm = (1<<2) ; RTC Clock Source bit 1 mask
.equ CLK_RTCSRC1_bp = 2 ; RTC Clock Source bit 1 position
.equ CLK_RTCSRC2_bm = (1<<3) ; RTC Clock Source bit 2 mask
.equ CLK_RTCSRC2_bp = 3 ; RTC Clock Source bit 2 position
.equ CLK_RTCEN_bm = 0x01 ; RTC Clock Source Enable bit mask
.equ CLK_RTCEN_bp = 0 ; RTC Clock Source Enable bit position
; PR_PRGEN masks
.equ PR_AES_bm = 0x10 ; AES bit mask
.equ PR_AES_bp = 4 ; AES bit position
.equ PR_EBI_bm = 0x08 ; External Bus Interface bit mask
.equ PR_EBI_bp = 3 ; External Bus Interface bit position
.equ PR_RTC_bm = 0x04 ; Real-time Counter bit mask
.equ PR_RTC_bp = 2 ; Real-time Counter bit position
.equ PR_EVSYS_bm = 0x02 ; Event System bit mask
.equ PR_EVSYS_bp = 1 ; Event System bit position
.equ PR_DMA_bm = 0x01 ; DMA-Controller bit mask
.equ PR_DMA_bp = 0 ; DMA-Controller bit position
; PR_PRPA masks
.equ PR_DAC_bm = 0x04 ; Port A DAC bit mask
.equ PR_DAC_bp = 2 ; Port A DAC bit position
.equ PR_ADC_bm = 0x02 ; Port A ADC bit mask
.equ PR_ADC_bp = 1 ; Port A ADC bit position
.equ PR_AC_bm = 0x01 ; Port A Analog Comparator bit mask
.equ PR_AC_bp = 0 ; Port A Analog Comparator bit position
; PR_PRPB masks
; Masks for DAC aready defined
; Masks for ADC aready defined
; Masks for AC aready defined
; PR_PRPC masks
.equ PR_TWI_bm = 0x40 ; Port C Two-wire Interface bit mask
.equ PR_TWI_bp = 6 ; Port C Two-wire Interface bit position
.equ PR_USART1_bm = 0x20 ; Port C USART1 bit mask
.equ PR_USART1_bp = 5 ; Port C USART1 bit position
.equ PR_USART0_bm = 0x10 ; Port C USART0 bit mask
.equ PR_USART0_bp = 4 ; Port C USART0 bit position
.equ PR_SPI_bm = 0x08 ; Port C SPI bit mask
.equ PR_SPI_bp = 3 ; Port C SPI bit position
.equ PR_HIRES_bm = 0x04 ; Port C AWEX bit mask
.equ PR_HIRES_bp = 2 ; Port C AWEX bit position
.equ PR_TC1_bm = 0x02 ; Port C Timer/Counter1 bit mask
.equ PR_TC1_bp = 1 ; Port C Timer/Counter1 bit position
.equ PR_TC0_bm = 0x01 ; Port C Timer/Counter0 bit mask
.equ PR_TC0_bp = 0 ; Port C Timer/Counter0 bit position
; PR_PRPD masks
; Masks for TWI aready defined
; Masks for USART1 aready defined
; Masks for USART0 aready defined
; Masks for SPI aready defined
; Masks for HIRES aready defined
; Masks for TC1 aready defined
; Masks for TC0 aready defined
; PR_PRPE masks
; Masks for TWI aready defined
; Masks for USART1 aready defined
; Masks for USART0 aready defined
; Masks for SPI aready defined
; Masks for HIRES aready defined
; Masks for TC1 aready defined
; Masks for TC0 aready defined
; PR_PRPF masks
; Masks for TWI aready defined
; Masks for USART1 aready defined
; Masks for USART0 aready defined
; Masks for SPI aready defined
; Masks for HIRES aready defined
; Masks for TC1 aready defined
; Masks for TC0 aready defined
; System Clock Selection
.equ CLK_SCLKSEL_RC2M_gc = (0x00<<0) ; Internal 2MHz RC Oscillator
.equ CLK_SCLKSEL_RC32M_gc = (0x01<<0) ; Internal 32MHz RC Oscillator
.equ CLK_SCLKSEL_RC32K_gc = (0x02<<0) ; Internal 32kHz RC Oscillator
.equ CLK_SCLKSEL_XOSC_gc = (0x03<<0) ; External Crystal Oscillator or Clock
.equ CLK_SCLKSEL_PLL_gc = (0x04<<0) ; Phase Locked Loop
; Prescaler A Division Factor
.equ CLK_PSADIV_1_gc = (0x00<<2) ; Divide by 1
.equ CLK_PSADIV_2_gc = (0x01<<2) ; Divide by 2
.equ CLK_PSADIV_4_gc = (0x03<<2) ; Divide by 4
.equ CLK_PSADIV_8_gc = (0x05<<2) ; Divide by 8
.equ CLK_PSADIV_16_gc = (0x07<<2) ; Divide by 16
.equ CLK_PSADIV_32_gc = (0x09<<2) ; Divide by 32
.equ CLK_PSADIV_64_gc = (0x0B<<2) ; Divide by 64
.equ CLK_PSADIV_128_gc = (0x0D<<2) ; Divide by 128
.equ CLK_PSADIV_256_gc = (0x0F<<2) ; Divide by 256
.equ CLK_PSADIV_512_gc = (0x11<<2) ; Divide by 512
; Prescaler B and C Division Factor
.equ CLK_PSBCDIV_1_1_gc = (0x00<<0) ; Divide B by 1 and C by 1
.equ CLK_PSBCDIV_1_2_gc = (0x01<<0) ; Divide B by 1 and C by 2
.equ CLK_PSBCDIV_4_1_gc = (0x02<<0) ; Divide B by 4 and C by 1
.equ CLK_PSBCDIV_2_2_gc = (0x03<<0) ; Divide B by 2 and C by 2
; RTC Clock Source
.equ CLK_RTCSRC_ULP_gc = (0x00<<1) ; 1kHz from internal 32kHz ULP
.equ CLK_RTCSRC_TOSC_gc = (0x01<<1) ; 1kHz from 32kHz crystal oscillator on TOSC
.equ CLK_RTCSRC_RCOSC_gc = (0x02<<1) ; 1kHz from internal 32kHz RC oscillator
.equ CLK_RTCSRC_TOSC32_gc = (0x05<<1) ; 32kHz from 32kHz crystal oscillator on TOSC
;***************************************************************************
;** SLEEP - Sleep Controller
;***************************************************************************/
; SLEEP_CTRL masks
.equ SLEEP_SMODE_gm = 0x0E ; Sleep Mode group mask
.equ SLEEP_SMODE_gp = 1 ; Sleep Mode group position
.equ SLEEP_SMODE0_bm = (1<<1) ; Sleep Mode bit 0 mask
.equ SLEEP_SMODE0_bp = 1 ; Sleep Mode bit 0 position
.equ SLEEP_SMODE1_bm = (1<<2) ; Sleep Mode bit 1 mask
.equ SLEEP_SMODE1_bp = 2 ; Sleep Mode bit 1 position
.equ SLEEP_SMODE2_bm = (1<<3) ; Sleep Mode bit 2 mask
.equ SLEEP_SMODE2_bp = 3 ; Sleep Mode bit 2 position
.equ SLEEP_SEN_bm = 0x01 ; Sleep Enable bit mask
.equ SLEEP_SEN_bp = 0 ; Sleep Enable bit position
; Sleep Mode
.equ SLEEP_SMODE_IDLE_gc = (0x00<<1) ; Idle mode
.equ SLEEP_SMODE_PDOWN_gc = (0x02<<1) ; Power-down Mode
.equ SLEEP_SMODE_PSAVE_gc = (0x03<<1) ; Power-save Mode
.equ SLEEP_SMODE_STDBY_gc = (0x06<<1) ; Standby Mode
.equ SLEEP_SMODE_ESTDBY_gc = (0x07<<1) ; Extended Standby Mode
;***************************************************************************
;** OSC - Oscillator
;***************************************************************************/
; OSC_CTRL masks
.equ OSC_PLLEN_bm = 0x10 ; PLL Enable bit mask
.equ OSC_PLLEN_bp = 4 ; PLL Enable bit position
.equ OSC_XOSCEN_bm = 0x08 ; External Oscillator Enable bit mask
.equ OSC_XOSCEN_bp = 3 ; External Oscillator Enable bit position
.equ OSC_RC32KEN_bm = 0x04 ; Internal 32kHz RC Oscillator Enable bit mask
.equ OSC_RC32KEN_bp = 2 ; Internal 32kHz RC Oscillator Enable bit position
.equ OSC_RC32MEN_bm = 0x02 ; Internal 32MHz RC Oscillator Enable bit mask
.equ OSC_RC32MEN_bp = 1 ; Internal 32MHz RC Oscillator Enable bit position
.equ OSC_RC2MEN_bm = 0x01 ; Internal 2MHz RC Oscillator Enable bit mask
.equ OSC_RC2MEN_bp = 0 ; Internal 2MHz RC Oscillator Enable bit position
; OSC_STATUS masks
.equ OSC_PLLRDY_bm = 0x10 ; PLL Ready bit mask
.equ OSC_PLLRDY_bp = 4 ; PLL Ready bit position
.equ OSC_XOSCRDY_bm = 0x08 ; External Oscillator Ready bit mask
.equ OSC_XOSCRDY_bp = 3 ; External Oscillator Ready bit position
.equ OSC_RC32KRDY_bm = 0x04 ; Internal 32kHz RC Oscillator Ready bit mask
.equ OSC_RC32KRDY_bp = 2 ; Internal 32kHz RC Oscillator Ready bit position
.equ OSC_RC32MRDY_bm = 0x02 ; Internal 32MHz RC Oscillator Ready bit mask
.equ OSC_RC32MRDY_bp = 1 ; Internal 32MHz RC Oscillator Ready bit position
.equ OSC_RC2MRDY_bm = 0x01 ; Internal 2MHz RC Oscillator Ready bit mask
.equ OSC_RC2MRDY_bp = 0 ; Internal 2MHz RC Oscillator Ready bit position
; OSC_XOSCCTRL masks
.equ OSC_FRQRANGE_gm = 0xC0 ; Frequency Range group mask
.equ OSC_FRQRANGE_gp = 6 ; Frequency Range group position
.equ OSC_FRQRANGE0_bm = (1<<6) ; Frequency Range bit 0 mask
.equ OSC_FRQRANGE0_bp = 6 ; Frequency Range bit 0 position
.equ OSC_FRQRANGE1_bm = (1<<7) ; Frequency Range bit 1 mask
.equ OSC_FRQRANGE1_bp = 7 ; Frequency Range bit 1 position
.equ OSC_X32KLPM_bm = 0x20 ; 32kHz XTAL OSC Low-power Mode bit mask
.equ OSC_X32KLPM_bp = 5 ; 32kHz XTAL OSC Low-power Mode bit position
.equ OSC_XOSCSEL_gm = 0x0F ; External Oscillator Selection and Startup Time group mask
.equ OSC_XOSCSEL_gp = 0 ; External Oscillator Selection and Startup Time group position
.equ OSC_XOSCSEL0_bm = (1<<0) ; External Oscillator Selection and Startup Time bit 0 mask
.equ OSC_XOSCSEL0_bp = 0 ; External Oscillator Selection and Startup Time bit 0 position
.equ OSC_XOSCSEL1_bm = (1<<1) ; External Oscillator Selection and Startup Time bit 1 mask
.equ OSC_XOSCSEL1_bp = 1 ; External Oscillator Selection and Startup Time bit 1 position
.equ OSC_XOSCSEL2_bm = (1<<2) ; External Oscillator Selection and Startup Time bit 2 mask
.equ OSC_XOSCSEL2_bp = 2 ; External Oscillator Selection and Startup Time bit 2 position
.equ OSC_XOSCSEL3_bm = (1<<3) ; External Oscillator Selection and Startup Time bit 3 mask
.equ OSC_XOSCSEL3_bp = 3 ; External Oscillator Selection and Startup Time bit 3 position
; OSC_XOSCFAIL masks
.equ OSC_XOSCFDIF_bm = 0x02 ; Failure Detection Interrupt Flag bit mask
.equ OSC_XOSCFDIF_bp = 1 ; Failure Detection Interrupt Flag bit position
.equ OSC_XOSCFDEN_bm = 0x01 ; Failure Detection Enable bit mask
.equ OSC_XOSCFDEN_bp = 0 ; Failure Detection Enable bit position
; OSC_PLLCTRL masks
.equ OSC_PLLSRC_gm = 0xC0 ; Clock Source group mask
.equ OSC_PLLSRC_gp = 6 ; Clock Source group position
.equ OSC_PLLSRC0_bm = (1<<6) ; Clock Source bit 0 mask
.equ OSC_PLLSRC0_bp = 6 ; Clock Source bit 0 position
.equ OSC_PLLSRC1_bm = (1<<7) ; Clock Source bit 1 mask
.equ OSC_PLLSRC1_bp = 7 ; Clock Source bit 1 position
.equ OSC_PLLFAC_gm = 0x1F ; Multiplication Factor group mask
.equ OSC_PLLFAC_gp = 0 ; Multiplication Factor group position
.equ OSC_PLLFAC0_bm = (1<<0) ; Multiplication Factor bit 0 mask
.equ OSC_PLLFAC0_bp = 0 ; Multiplication Factor bit 0 position
.equ OSC_PLLFAC1_bm = (1<<1) ; Multiplication Factor bit 1 mask
.equ OSC_PLLFAC1_bp = 1 ; Multiplication Factor bit 1 position
.equ OSC_PLLFAC2_bm = (1<<2) ; Multiplication Factor bit 2 mask
.equ OSC_PLLFAC2_bp = 2 ; Multiplication Factor bit 2 position
.equ OSC_PLLFAC3_bm = (1<<3) ; Multiplication Factor bit 3 mask
.equ OSC_PLLFAC3_bp = 3 ; Multiplication Factor bit 3 position
.equ OSC_PLLFAC4_bm = (1<<4) ; Multiplication Factor bit 4 mask
.equ OSC_PLLFAC4_bp = 4 ; Multiplication Factor bit 4 position
; OSC_DFLLCTRL masks
.equ OSC_RC32MCREF_bm = 0x02 ; 32MHz Calibration Reference bit mask
.equ OSC_RC32MCREF_bp = 1 ; 32MHz Calibration Reference bit position
.equ OSC_RC2MCREF_bm = 0x01 ; 2MHz Calibration Reference bit mask
.equ OSC_RC2MCREF_bp = 0 ; 2MHz Calibration Reference bit position
; Oscillator Frequency Range
.equ OSC_FRQRANGE_04TO2_gc = (0x00<<6) ; 0.4 - 2 MHz
.equ OSC_FRQRANGE_2TO9_gc = (0x01<<6) ; 2 - 9 MHz
.equ OSC_FRQRANGE_9TO12_gc = (0x02<<6) ; 9 - 12 MHz
.equ OSC_FRQRANGE_12TO16_gc = (0x03<<6) ; 12 - 16 MHz
; External Oscillator Selection and Startup Time
.equ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0) ; External Clock - 6 CLK
.equ OSC_XOSCSEL_32KHz_gc = (0x02<<0) ; 32kHz TOSC - 32K CLK
.equ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0) ; 0.4-16MHz XTAL - 256 CLK
.equ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0) ; 0.4-16MHz XTAL - 1K CLK
.equ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0) ; 0.4-16MHz XTAL - 16K CLK
; PLL Clock Source
.equ OSC_PLLSRC_RC2M_gc = (0x00<<6) ; Internal 2MHz RC Oscillator
.equ OSC_PLLSRC_RC32M_gc = (0x02<<6) ; Internal 32MHz RC Oscillator
.equ OSC_PLLSRC_XOSC_gc = (0x03<<6) ; External Oscillator
;***************************************************************************
;** DFLL - DFLL
;***************************************************************************/
; DFLL_CTRL masks
.equ DFLL_ENABLE_bm = 0x01 ; DFLL Enable bit mask
.equ DFLL_ENABLE_bp = 0 ; DFLL Enable bit position
; DFLL_CALA masks
.equ DFLL_CALL_gm = 0x7F ; DFLL Calibration bits [6:0] group mask
.equ DFLL_CALL_gp = 0 ; DFLL Calibration bits [6:0] group position
.equ DFLL_CALL0_bm = (1<<0) ; DFLL Calibration bits [6:0] bit 0 mask
.equ DFLL_CALL0_bp = 0 ; DFLL Calibration bits [6:0] bit 0 position
.equ DFLL_CALL1_bm = (1<<1) ; DFLL Calibration bits [6:0] bit 1 mask
.equ DFLL_CALL1_bp = 1 ; DFLL Calibration bits [6:0] bit 1 position
.equ DFLL_CALL2_bm = (1<<2) ; DFLL Calibration bits [6:0] bit 2 mask
.equ DFLL_CALL2_bp = 2 ; DFLL Calibration bits [6:0] bit 2 position
.equ DFLL_CALL3_bm = (1<<3) ; DFLL Calibration bits [6:0] bit 3 mask
.equ DFLL_CALL3_bp = 3 ; DFLL Calibration bits [6:0] bit 3 position
.equ DFLL_CALL4_bm = (1<<4) ; DFLL Calibration bits [6:0] bit 4 mask
.equ DFLL_CALL4_bp = 4 ; DFLL Calibration bits [6:0] bit 4 position
.equ DFLL_CALL5_bm = (1<<5) ; DFLL Calibration bits [6:0] bit 5 mask
.equ DFLL_CALL5_bp = 5 ; DFLL Calibration bits [6:0] bit 5 position
.equ DFLL_CALL6_bm = (1<<6) ; DFLL Calibration bits [6:0] bit 6 mask
.equ DFLL_CALL6_bp = 6 ; DFLL Calibration bits [6:0] bit 6 position
; DFLL_CALB masks
.equ DFLL_CALH_gm = 0x3F ; DFLL Calibration bits [12:7] group mask
.equ DFLL_CALH_gp = 0 ; DFLL Calibration bits [12:7] group position
.equ DFLL_CALH0_bm = (1<<0) ; DFLL Calibration bits [12:7] bit 0 mask
.equ DFLL_CALH0_bp = 0 ; DFLL Calibration bits [12:7] bit 0 position
.equ DFLL_CALH1_bm = (1<<1) ; DFLL Calibration bits [12:7] bit 1 mask
.equ DFLL_CALH1_bp = 1 ; DFLL Calibration bits [12:7] bit 1 position
.equ DFLL_CALH2_bm = (1<<2) ; DFLL Calibration bits [12:7] bit 2 mask
.equ DFLL_CALH2_bp = 2 ; DFLL Calibration bits [12:7] bit 2 position
.equ DFLL_CALH3_bm = (1<<3) ; DFLL Calibration bits [12:7] bit 3 mask
.equ DFLL_CALH3_bp = 3 ; DFLL Calibration bits [12:7] bit 3 position
.equ DFLL_CALH4_bm = (1<<4) ; DFLL Calibration bits [12:7] bit 4 mask
.equ DFLL_CALH4_bp = 4 ; DFLL Calibration bits [12:7] bit 4 position
.equ DFLL_CALH5_bm = (1<<5) ; DFLL Calibration bits [12:7] bit 5 mask
.equ DFLL_CALH5_bp = 5 ; DFLL Calibration bits [12:7] bit 5 position
;***************************************************************************
;** RST - Reset
;***************************************************************************/
; RST_STATUS masks
.equ RST_SDRF_bm = 0x40 ; Spike Detection Reset Flag bit mask
.equ RST_SDRF_bp = 6 ; Spike Detection Reset Flag bit position
.equ RST_SRF_bm = 0x20 ; Software Reset Flag bit mask
.equ RST_SRF_bp = 5 ; Software Reset Flag bit position
.equ RST_PDIRF_bm = 0x10 ; Programming and Debug Interface Interface Reset Flag bit mask
.equ RST_PDIRF_bp = 4 ; Programming and Debug Interface Interface Reset Flag bit position
.equ RST_WDRF_bm = 0x08 ; Watchdog Reset Flag bit mask
.equ RST_WDRF_bp = 3 ; Watchdog Reset Flag bit position
.equ RST_BORF_bm = 0x04 ; Brown-out Reset Flag bit mask
.equ RST_BORF_bp = 2 ; Brown-out Reset Flag bit position
.equ RST_EXTRF_bm = 0x02 ; External Reset Flag bit mask
.equ RST_EXTRF_bp = 1 ; External Reset Flag bit position
.equ RST_PORF_bm = 0x01 ; Power-on Reset Flag bit mask
.equ RST_PORF_bp = 0 ; Power-on Reset Flag bit position
; RST_CTRL masks
.equ RST_SWRST_bm = 0x01 ; Software Reset bit mask
.equ RST_SWRST_bp = 0 ; Software Reset bit position
;***************************************************************************
;** WDT - Watch-Dog Timer
;***************************************************************************/
; WDT_CTRL masks
.equ WDT_PER_gm = 0x3C ; Period group mask
.equ WDT_PER_gp = 2 ; Period group position
.equ WDT_PER0_bm = (1<<2) ; Period bit 0 mask
.equ WDT_PER0_bp = 2 ; Period bit 0 position
.equ WDT_PER1_bm = (1<<3) ; Period bit 1 mask
.equ WDT_PER1_bp = 3 ; Period bit 1 position
.equ WDT_PER2_bm = (1<<4) ; Period bit 2 mask
.equ WDT_PER2_bp = 4 ; Period bit 2 position
.equ WDT_PER3_bm = (1<<5) ; Period bit 3 mask
.equ WDT_PER3_bp = 5 ; Period bit 3 position
.equ WDT_ENABLE_bm = 0x02 ; Enable bit mask
.equ WDT_ENABLE_bp = 1 ; Enable bit position
.equ WDT_CEN_bm = 0x01 ; Change Enable bit mask
.equ WDT_CEN_bp = 0 ; Change Enable bit position
; WDT_WINCTRL masks
.equ WDT_WPER_gm = 0x3C ; Windowed Mode Period group mask
.equ WDT_WPER_gp = 2 ; Windowed Mode Period group position
.equ WDT_WPER0_bm = (1<<2) ; Windowed Mode Period bit 0 mask
.equ WDT_WPER0_bp = 2 ; Windowed Mode Period bit 0 position
.equ WDT_WPER1_bm = (1<<3) ; Windowed Mode Period bit 1 mask
.equ WDT_WPER1_bp = 3 ; Windowed Mode Period bit 1 position
.equ WDT_WPER2_bm = (1<<4) ; Windowed Mode Period bit 2 mask
.equ WDT_WPER2_bp = 4 ; Windowed Mode Period bit 2 position
.equ WDT_WPER3_bm = (1<<5) ; Windowed Mode Period bit 3 mask
.equ WDT_WPER3_bp = 5 ; Windowed Mode Period bit 3 position
.equ WDT_WEN_bm = 0x02 ; Windowed Mode Enable bit mask
.equ WDT_WEN_bp = 1 ; Windowed Mode Enable bit position
.equ WDT_WCEN_bm = 0x01 ; Windowed Mode Change Enable bit mask
.equ WDT_WCEN_bp = 0 ; Windowed Mode Change Enable bit position
; WDT_STATUS masks
.equ WDT_SYNCBUSY_bm = 0x01 ; Syncronization busy bit mask
.equ WDT_SYNCBUSY_bp = 0 ; Syncronization busy bit position
; Period setting
.equ WDT_PER_8CLK_gc = (0x00<<2) ; 8 cycles (8ms @ 3.3V)
.equ WDT_PER_16CLK_gc = (0x01<<2) ; 16 cycles (16ms @ 3.3V)
.equ WDT_PER_32CLK_gc = (0x02<<2) ; 32 cycles (32ms @ 3.3V)
.equ WDT_PER_64CLK_gc = (0x03<<2) ; 64 cycles (64ms @ 3.3V)
.equ WDT_PER_125CLK_gc = (0x04<<2) ; 125 cycles (0.125s @ 3.3V)
.equ WDT_PER_250CLK_gc = (0x05<<2) ; 250 cycles (0.25s @ 3.3V)
.equ WDT_PER_500CLK_gc = (0x06<<2) ; 500 cycles (0.5s @ 3.3V)
.equ WDT_PER_1KCLK_gc = (0x07<<2) ; 1K cycles (1s @ 3.3V)
.equ WDT_PER_2KCLK_gc = (0x08<<2) ; 2K cycles (2s @ 3.3V)
.equ WDT_PER_4KCLK_gc = (0x09<<2) ; 4K cycles (4s @ 3.3V)
.equ WDT_PER_8KCLK_gc = (0x0A<<2) ; 8K cycles (8s @ 3.3V)
; Closed window period
.equ WDT_WPER_8CLK_gc = (0x00<<2) ; 8 cycles (8ms @ 3.3V)
.equ WDT_WPER_16CLK_gc = (0x01<<2) ; 16 cycles (16ms @ 3.3V)
.equ WDT_WPER_32CLK_gc = (0x02<<2) ; 32 cycles (32ms @ 3.3V)
.equ WDT_WPER_64CLK_gc = (0x03<<2) ; 64 cycles (64ms @ 3.3V)
.equ WDT_WPER_125CLK_gc = (0x04<<2) ; 125 cycles (0.125s @ 3.3V)
.equ WDT_WPER_250CLK_gc = (0x05<<2) ; 250 cycles (0.25s @ 3.3V)
.equ WDT_WPER_500CLK_gc = (0x06<<2) ; 500 cycles (0.5s @ 3.3V)
.equ WDT_WPER_1KCLK_gc = (0x07<<2) ; 1K cycles (1s @ 3.3V)
.equ WDT_WPER_2KCLK_gc = (0x08<<2) ; 2K cycles (2s @ 3.3V)
.equ WDT_WPER_4KCLK_gc = (0x09<<2) ; 4K cycles (4s @ 3.3V)
.equ WDT_WPER_8KCLK_gc = (0x0A<<2) ; 8K cycles (8s @ 3.3V)
;***************************************************************************
;** MCU - MCU Control
;***************************************************************************/
; MCU_MCUCR masks
.equ MCU_JTAGD_bm = 0x01 ; JTAG Disable bit mask
.equ MCU_JTAGD_bp = 0 ; JTAG Disable bit position
; MCU_EVSYSLOCK masks
.equ MCU_EVSYS1LOCK_bm = 0x10 ; Event Channel 4-7 Lock bit mask
.equ MCU_EVSYS1LOCK_bp = 4 ; Event Channel 4-7 Lock bit position
.equ MCU_EVSYS0LOCK_bm = 0x01 ; Event Channel 0-3 Lock bit mask
.equ MCU_EVSYS0LOCK_bp = 0 ; Event Channel 0-3 Lock bit position
; MCU_AWEXLOCK masks
.equ MCU_AWEXELOCK_bm = 0x04 ; AWeX on T/C E0 Lock bit mask
.equ MCU_AWEXELOCK_bp = 2 ; AWeX on T/C E0 Lock bit position
.equ MCU_AWEXCLOCK_bm = 0x01 ; AWeX on T/C C0 Lock bit mask
.equ MCU_AWEXCLOCK_bp = 0 ; AWeX on T/C C0 Lock bit position
;***************************************************************************
;** PMIC - Programmable Multi-level Interrupt Controller
;***************************************************************************/
; PMIC_STATUS masks
.equ PMIC_NMIEX_bm = 0x80 ; Non-maskable Interrupt Executing bit mask
.equ PMIC_NMIEX_bp = 7 ; Non-maskable Interrupt Executing bit position
.equ PMIC_HILVLEX_bm = 0x04 ; High Level Interrupt Executing bit mask
.equ PMIC_HILVLEX_bp = 2 ; High Level Interrupt Executing bit position
.equ PMIC_MEDLVLEX_bm = 0x02 ; Medium Level Interrupt Executing bit mask
.equ PMIC_MEDLVLEX_bp = 1 ; Medium Level Interrupt Executing bit position
.equ PMIC_LOLVLEX_bm = 0x01 ; Low Level Interrupt Executing bit mask
.equ PMIC_LOLVLEX_bp = 0 ; Low Level Interrupt Executing bit position
; PMIC_CTRL masks
.equ PMIC_RREN_bm = 0x80 ; Round-Robin Priority Enable bit mask
.equ PMIC_RREN_bp = 7 ; Round-Robin Priority Enable bit position
.equ PMIC_IVSEL_bm = 0x40 ; Interrupt Vector Select bit mask
.equ PMIC_IVSEL_bp = 6 ; Interrupt Vector Select bit position
.equ PMIC_HILVLEN_bm = 0x04 ; High Level Enable bit mask
.equ PMIC_HILVLEN_bp = 2 ; High Level Enable bit position
.equ PMIC_MEDLVLEN_bm = 0x02 ; Medium Level Enable bit mask
.equ PMIC_MEDLVLEN_bp = 1 ; Medium Level Enable bit position
.equ PMIC_LOLVLEN_bm = 0x01 ; Low Level Enable bit mask
.equ PMIC_LOLVLEN_bp = 0 ; Low Level Enable bit position
;***************************************************************************
;** EVSYS - Event System
;***************************************************************************/
; EVSYS_CH0MUX masks
.equ EVSYS_CHMUX_gm = 0xFF ; Event Channel 0 Multiplexer group mask
.equ EVSYS_CHMUX_gp = 0 ; Event Channel 0 Multiplexer group position
.equ EVSYS_CHMUX0_bm = (1<<0) ; Event Channel 0 Multiplexer bit 0 mask
.equ EVSYS_CHMUX0_bp = 0 ; Event Channel 0 Multiplexer bit 0 position
.equ EVSYS_CHMUX1_bm = (1<<1) ; Event Channel 0 Multiplexer bit 1 mask
.equ EVSYS_CHMUX1_bp = 1 ; Event Channel 0 Multiplexer bit 1 position
.equ EVSYS_CHMUX2_bm = (1<<2) ; Event Channel 0 Multiplexer bit 2 mask
.equ EVSYS_CHMUX2_bp = 2 ; Event Channel 0 Multiplexer bit 2 position
.equ EVSYS_CHMUX3_bm = (1<<3) ; Event Channel 0 Multiplexer bit 3 mask
.equ EVSYS_CHMUX3_bp = 3 ; Event Channel 0 Multiplexer bit 3 position
.equ EVSYS_CHMUX4_bm = (1<<4) ; Event Channel 0 Multiplexer bit 4 mask
.equ EVSYS_CHMUX4_bp = 4 ; Event Channel 0 Multiplexer bit 4 position
.equ EVSYS_CHMUX5_bm = (1<<5) ; Event Channel 0 Multiplexer bit 5 mask
.equ EVSYS_CHMUX5_bp = 5 ; Event Channel 0 Multiplexer bit 5 position
.equ EVSYS_CHMUX6_bm = (1<<6) ; Event Channel 0 Multiplexer bit 6 mask
.equ EVSYS_CHMUX6_bp = 6 ; Event Channel 0 Multiplexer bit 6 position
.equ EVSYS_CHMUX7_bm = (1<<7) ; Event Channel 0 Multiplexer bit 7 mask
.equ EVSYS_CHMUX7_bp = 7 ; Event Channel 0 Multiplexer bit 7 position
; EVSYS_CH1MUX masks
; Masks for CHMUX aready defined
; EVSYS_CH2MUX masks
; Masks for CHMUX aready defined
; EVSYS_CH3MUX masks
; Masks for CHMUX aready defined
; EVSYS_CH0CTRL masks
.equ EVSYS_QDIRM_gm = 0x60 ; Quadrature Decoder Index Recognition Mode group mask
.equ EVSYS_QDIRM_gp = 5 ; Quadrature Decoder Index Recognition Mode group position
.equ EVSYS_QDIRM0_bm = (1<<5) ; Quadrature Decoder Index Recognition Mode bit 0 mask
.equ EVSYS_QDIRM0_bp = 5 ; Quadrature Decoder Index Recognition Mode bit 0 position
.equ EVSYS_QDIRM1_bm = (1<<6) ; Quadrature Decoder Index Recognition Mode bit 1 mask
.equ EVSYS_QDIRM1_bp = 6 ; Quadrature Decoder Index Recognition Mode bit 1 position
.equ EVSYS_QDIEN_bm = 0x10 ; Quadrature Decoder Index Enable bit mask
.equ EVSYS_QDIEN_bp = 4 ; Quadrature Decoder Index Enable bit position
.equ EVSYS_QDEN_bm = 0x08 ; Quadrature Decoder Enable bit mask
.equ EVSYS_QDEN_bp = 3 ; Quadrature Decoder Enable bit position
.equ EVSYS_DIGFILT_gm = 0x07 ; Digital Filter group mask
.equ EVSYS_DIGFILT_gp = 0 ; Digital Filter group position
.equ EVSYS_DIGFILT0_bm = (1<<0) ; Digital Filter bit 0 mask
.equ EVSYS_DIGFILT0_bp = 0 ; Digital Filter bit 0 position
.equ EVSYS_DIGFILT1_bm = (1<<1) ; Digital Filter bit 1 mask
.equ EVSYS_DIGFILT1_bp = 1 ; Digital Filter bit 1 position
.equ EVSYS_DIGFILT2_bm = (1<<2) ; Digital Filter bit 2 mask
.equ EVSYS_DIGFILT2_bp = 2 ; Digital Filter bit 2 position
; EVSYS_CH1CTRL masks
; Masks for DIGFILT aready defined
; EVSYS_CH2CTRL masks
; Masks for QDIRM aready defined
; Masks for QDIEN aready defined
; Masks for QDEN aready defined
; Masks for DIGFILT aready defined
; EVSYS_CH3CTRL masks
; Masks for DIGFILT aready defined
; Quadrature Decoder Index Recognition Mode
.equ EVSYS_QDIRM_00_gc = (0x00<<5) ; QDPH0 = 0, QDPH90 = 0
.equ EVSYS_QDIRM_01_gc = (0x01<<5) ; QDPH0 = 0, QDPH90 = 1
.equ EVSYS_QDIRM_10_gc = (0x02<<5) ; QDPH0 = 1, QDPH90 = 0
.equ EVSYS_QDIRM_11_gc = (0x03<<5) ; QDPH0 = 1, QDPH90 = 1
; Digital filter coefficient
.equ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0) ; 1 SAMPLE
.equ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0) ; 2 SAMPLES
.equ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0) ; 3 SAMPLES
.equ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0) ; 4 SAMPLES
.equ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0) ; 5 SAMPLES
.equ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0) ; 6 SAMPLES
.equ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0) ; 7 SAMPLES
.equ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0) ; 8 SAMPLES
; Event Channel multiplexer input selection
.equ EVSYS_CHMUX_OFF_gc = (0x00<<0) ; Off
.equ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0) ; RTC Overflow
.equ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0) ; RTC Compare Match
.equ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0) ; Analog Comparator A Channel 0
.equ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0) ; Analog Comparator A Channel 1
.equ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0) ; Analog Comparator A Window
.equ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0) ; ADC A Channel 0
.equ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0) ; Port A, Pin0
.equ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0) ; Port A, Pin1
.equ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0) ; Port A, Pin2
.equ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0) ; Port A, Pin3
.equ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0) ; Port A, Pin4
.equ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0) ; Port A, Pin5
.equ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0) ; Port A, Pin6
.equ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0) ; Port A, Pin7
.equ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0) ; Port B, Pin0
.equ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0) ; Port B, Pin1
.equ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0) ; Port B, Pin2
.equ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0) ; Port B, Pin3
.equ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0) ; Port B, Pin4
.equ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0) ; Port B, Pin5
.equ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0) ; Port B, Pin6
.equ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0) ; Port B, Pin7
.equ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0) ; Port C, Pin0
.equ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0) ; Port C, Pin1
.equ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0) ; Port C, Pin2
.equ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0) ; Port C, Pin3
.equ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0) ; Port C, Pin4
.equ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0) ; Port C, Pin5
.equ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0) ; Port C, Pin6
.equ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0) ; Port C, Pin7
.equ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0) ; Port D, Pin0
.equ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0) ; Port D, Pin1
.equ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0) ; Port D, Pin2
.equ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0) ; Port D, Pin3
.equ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0) ; Port D, Pin4
.equ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0) ; Port D, Pin5
.equ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0) ; Port D, Pin6
.equ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0) ; Port D, Pin7
.equ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0) ; Port E, Pin0
.equ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0) ; Port E, Pin1
.equ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0) ; Port E, Pin2
.equ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0) ; Port E, Pin3
.equ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0) ; Port E, Pin4
.equ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0) ; Port E, Pin5
.equ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0) ; Port E, Pin6
.equ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0) ; Port E, Pin7
.equ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0) ; Port F, Pin0
.equ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0) ; Port F, Pin1
.equ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0) ; Port F, Pin2
.equ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0) ; Port F, Pin3
.equ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0) ; Port F, Pin4
.equ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0) ; Port F, Pin5
.equ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0) ; Port F, Pin6
.equ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0) ; Port F, Pin7
.equ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0) ; Prescaler, divide by 1
.equ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0) ; Prescaler, divide by 2
.equ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0) ; Prescaler, divide by 4
.equ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0) ; Prescaler, divide by 8
.equ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0) ; Prescaler, divide by 16
.equ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0) ; Prescaler, divide by 32
.equ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0) ; Prescaler, divide by 64
.equ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0) ; Prescaler, divide by 128
.equ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0) ; Prescaler, divide by 256
.equ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0) ; Prescaler, divide by 512
.equ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0) ; Prescaler, divide by 1024
.equ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0) ; Prescaler, divide by 2048
.equ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0) ; Prescaler, divide by 4096
.equ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0) ; Prescaler, divide by 8192
.equ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0) ; Prescaler, divide by 16384
.equ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0) ; Prescaler, divide by 32768
.equ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0) ; Timer/Counter C0 Overflow
.equ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0) ; Timer/Counter C0 Error
.equ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0) ; Timer/Counter C0 Compare or Capture A
.equ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0) ; Timer/Counter C0 Compare or Capture B
.equ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0) ; Timer/Counter C0 Compare or Capture C
.equ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0) ; Timer/Counter C0 Compare or Capture D
.equ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0) ; Timer/Counter C1 Overflow
.equ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0) ; Timer/Counter C1 Error
.equ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0) ; Timer/Counter C1 Compare or Capture A
.equ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0) ; Timer/Counter C1 Compare or Capture B
.equ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0) ; Timer/Counter D0 Overflow
.equ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0) ; Timer/Counter D0 Error
.equ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0) ; Timer/Counter D0 Compare or Capture A
.equ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0) ; Timer/Counter D0 Compare or Capture B
.equ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0) ; Timer/Counter D0 Compare or Capture C
.equ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0) ; Timer/Counter D0 Compare or Capture D
.equ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0) ; Timer/Counter E0 Overflow
.equ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0) ; Timer/Counter E0 Error
.equ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0) ; Timer/Counter E0 Compare or Capture A
.equ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0) ; Timer/Counter E0 Compare or Capture B
.equ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0) ; Timer/Counter E0 Compare or Capture C
.equ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0) ; Timer/Counter E0 Compare or Capture D
.equ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0) ; Timer/Counter F0 Overflow
.equ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0) ; Timer/Counter F0 Error
.equ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0) ; Timer/Counter F0 Compare or Capture A
.equ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0) ; Timer/Counter F0 Compare or Capture B
.equ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0) ; Timer/Counter F0 Compare or Capture C
.equ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0) ; Timer/Counter F0 Compare or Capture D
;***************************************************************************
;** NVM - Non Volatile Memory Controller
;***************************************************************************/
; NVM_CMD masks
.equ NVM_CMD_gm = 0xFF ; Command group mask
.equ NVM_CMD_gp = 0 ; Command group position
.equ NVM_CMD0_bm = (1<<0) ; Command bit 0 mask
.equ NVM_CMD0_bp = 0 ; Command bit 0 position
.equ NVM_CMD1_bm = (1<<1) ; Command bit 1 mask
.equ NVM_CMD1_bp = 1 ; Command bit 1 position
.equ NVM_CMD2_bm = (1<<2) ; Command bit 2 mask
.equ NVM_CMD2_bp = 2 ; Command bit 2 position
.equ NVM_CMD3_bm = (1<<3) ; Command bit 3 mask
.equ NVM_CMD3_bp = 3 ; Command bit 3 position
.equ NVM_CMD4_bm = (1<<4) ; Command bit 4 mask
.equ NVM_CMD4_bp = 4 ; Command bit 4 position
.equ NVM_CMD5_bm = (1<<5) ; Command bit 5 mask
.equ NVM_CMD5_bp = 5 ; Command bit 5 position
.equ NVM_CMD6_bm = (1<<6) ; Command bit 6 mask
.equ NVM_CMD6_bp = 6 ; Command bit 6 position
.equ NVM_CMD7_bm = (1<<7) ; Command bit 7 mask
.equ NVM_CMD7_bp = 7 ; Command bit 7 position
; NVM_CTRLA masks
.equ NVM_CMDEX_bm = 0x01 ; Command Execute bit mask
.equ NVM_CMDEX_bp = 0 ; Command Execute bit position
; NVM_CTRLB masks
.equ NVM_EEMAPEN_bm = 0x08 ; EEPROM Mapping Enable bit mask
.equ NVM_EEMAPEN_bp = 3 ; EEPROM Mapping Enable bit position
.equ NVM_FPRM_bm = 0x04 ; Flash Power Reduction Enable bit mask
.equ NVM_FPRM_bp = 2 ; Flash Power Reduction Enable bit position
.equ NVM_EPRM_bm = 0x02 ; EEPROM Power Reduction Enable bit mask
.equ NVM_EPRM_bp = 1 ; EEPROM Power Reduction Enable bit position
.equ NVM_SPMLOCK_bm = 0x01 ; SPM Lock bit mask
.equ NVM_SPMLOCK_bp = 0 ; SPM Lock bit position
; NVM_INTCTRL masks
.equ NVM_SPMLVL_gm = 0x0C ; SPM Interrupt Level group mask
.equ NVM_SPMLVL_gp = 2 ; SPM Interrupt Level group position
.equ NVM_SPMLVL0_bm = (1<<2) ; SPM Interrupt Level bit 0 mask
.equ NVM_SPMLVL0_bp = 2 ; SPM Interrupt Level bit 0 position
.equ NVM_SPMLVL1_bm = (1<<3) ; SPM Interrupt Level bit 1 mask
.equ NVM_SPMLVL1_bp = 3 ; SPM Interrupt Level bit 1 position
.equ NVM_EELVL_gm = 0x03 ; EEPROM Interrupt Level group mask
.equ NVM_EELVL_gp = 0 ; EEPROM Interrupt Level group position
.equ NVM_EELVL0_bm = (1<<0) ; EEPROM Interrupt Level bit 0 mask
.equ NVM_EELVL0_bp = 0 ; EEPROM Interrupt Level bit 0 position
.equ NVM_EELVL1_bm = (1<<1) ; EEPROM Interrupt Level bit 1 mask
.equ NVM_EELVL1_bp = 1 ; EEPROM Interrupt Level bit 1 position
; NVM_STATUS masks
.equ NVM_NVMBUSY_bm = 0x80 ; Non-volatile Memory Busy bit mask
.equ NVM_NVMBUSY_bp = 7 ; Non-volatile Memory Busy bit position
.equ NVM_FBUSY_bm = 0x40 ; Flash Memory Busy bit mask
.equ NVM_FBUSY_bp = 6 ; Flash Memory Busy bit position
.equ NVM_EELOAD_bm = 0x02 ; EEPROM Page Buffer Active Loading bit mask
.equ NVM_EELOAD_bp = 1 ; EEPROM Page Buffer Active Loading bit position
.equ NVM_FLOAD_bm = 0x01 ; Flash Page Buffer Active Loading bit mask
.equ NVM_FLOAD_bp = 0 ; Flash Page Buffer Active Loading bit position
; NVM_LOCKBITS masks
.equ NVM_BLBB_gm = 0xC0 ; Boot Lock Bits - Boot Section group mask
.equ NVM_BLBB_gp = 6 ; Boot Lock Bits - Boot Section group position
.equ NVM_BLBB0_bm = (1<<6) ; Boot Lock Bits - Boot Section bit 0 mask
.equ NVM_BLBB0_bp = 6 ; Boot Lock Bits - Boot Section bit 0 position
.equ NVM_BLBB1_bm = (1<<7) ; Boot Lock Bits - Boot Section bit 1 mask
.equ NVM_BLBB1_bp = 7 ; Boot Lock Bits - Boot Section bit 1 position
.equ NVM_BLBA_gm = 0x30 ; Boot Lock Bits - Application Section group mask
.equ NVM_BLBA_gp = 4 ; Boot Lock Bits - Application Section group position
.equ NVM_BLBA0_bm = (1<<4) ; Boot Lock Bits - Application Section bit 0 mask
.equ NVM_BLBA0_bp = 4 ; Boot Lock Bits - Application Section bit 0 position
.equ NVM_BLBA1_bm = (1<<5) ; Boot Lock Bits - Application Section bit 1 mask
.equ NVM_BLBA1_bp = 5 ; Boot Lock Bits - Application Section bit 1 position
.equ NVM_BLBAT_gm = 0x0C ; Boot Lock Bits - Application Table group mask
.equ NVM_BLBAT_gp = 2 ; Boot Lock Bits - Application Table group position
.equ NVM_BLBAT0_bm = (1<<2) ; Boot Lock Bits - Application Table bit 0 mask
.equ NVM_BLBAT0_bp = 2 ; Boot Lock Bits - Application Table bit 0 position
.equ NVM_BLBAT1_bm = (1<<3) ; Boot Lock Bits - Application Table bit 1 mask
.equ NVM_BLBAT1_bp = 3 ; Boot Lock Bits - Application Table bit 1 position
.equ NVM_LB_gm = 0x03 ; Lock Bits group mask
.equ NVM_LB_gp = 0 ; Lock Bits group position
.equ NVM_LB0_bm = (1<<0) ; Lock Bits bit 0 mask
.equ NVM_LB0_bp = 0 ; Lock Bits bit 0 position
.equ NVM_LB1_bm = (1<<1) ; Lock Bits bit 1 mask
.equ NVM_LB1_bp = 1 ; Lock Bits bit 1 position
; NVM_LOCKBITS_LOCKBITS masks
.equ NVM_LOCKBITS_BLBB_gm = 0xC0 ; Boot Lock Bits - Boot Section group mask
.equ NVM_LOCKBITS_BLBB_gp = 6 ; Boot Lock Bits - Boot Section group position
.equ NVM_LOCKBITS_BLBB0_bm = (1<<6) ; Boot Lock Bits - Boot Section bit 0 mask
.equ NVM_LOCKBITS_BLBB0_bp = 6 ; Boot Lock Bits - Boot Section bit 0 position
.equ NVM_LOCKBITS_BLBB1_bm = (1<<7) ; Boot Lock Bits - Boot Section bit 1 mask
.equ NVM_LOCKBITS_BLBB1_bp = 7 ; Boot Lock Bits - Boot Section bit 1 position
.equ NVM_LOCKBITS_BLBA_gm = 0x30 ; Boot Lock Bits - Application Section group mask
.equ NVM_LOCKBITS_BLBA_gp = 4 ; Boot Lock Bits - Application Section group position
.equ NVM_LOCKBITS_BLBA0_bm = (1<<4) ; Boot Lock Bits - Application Section bit 0 mask
.equ NVM_LOCKBITS_BLBA0_bp = 4 ; Boot Lock Bits - Application Section bit 0 position
.equ NVM_LOCKBITS_BLBA1_bm = (1<<5) ; Boot Lock Bits - Application Section bit 1 mask
.equ NVM_LOCKBITS_BLBA1_bp = 5 ; Boot Lock Bits - Application Section bit 1 position
.equ NVM_LOCKBITS_BLBAT_gm = 0x0C ; Boot Lock Bits - Application Table group mask
.equ NVM_LOCKBITS_BLBAT_gp = 2 ; Boot Lock Bits - Application Table group position
.equ NVM_LOCKBITS_BLBAT0_bm = (1<<2) ; Boot Lock Bits - Application Table bit 0 mask
.equ NVM_LOCKBITS_BLBAT0_bp = 2 ; Boot Lock Bits - Application Table bit 0 position
.equ NVM_LOCKBITS_BLBAT1_bm = (1<<3) ; Boot Lock Bits - Application Table bit 1 mask
.equ NVM_LOCKBITS_BLBAT1_bp = 3 ; Boot Lock Bits - Application Table bit 1 position
.equ NVM_LOCKBITS_LB_gm = 0x03 ; Lock Bits group mask
.equ NVM_LOCKBITS_LB_gp = 0 ; Lock Bits group position
.equ NVM_LOCKBITS_LB0_bm = (1<<0) ; Lock Bits bit 0 mask
.equ NVM_LOCKBITS_LB0_bp = 0 ; Lock Bits bit 0 position
.equ NVM_LOCKBITS_LB1_bm = (1<<1) ; Lock Bits bit 1 mask
.equ NVM_LOCKBITS_LB1_bp = 1 ; Lock Bits bit 1 position
; NVM_FUSES_FUSEBYTE0 masks
.equ NVM_FUSES_USERID_gm = 0xFF ; User ID group mask
.equ NVM_FUSES_USERID_gp = 0 ; User ID group position
.equ NVM_FUSES_USERID0_bm = (1<<0) ; User ID bit 0 mask
.equ NVM_FUSES_USERID0_bp = 0 ; User ID bit 0 position
.equ NVM_FUSES_USERID1_bm = (1<<1) ; User ID bit 1 mask
.equ NVM_FUSES_USERID1_bp = 1 ; User ID bit 1 position
.equ NVM_FUSES_USERID2_bm = (1<<2) ; User ID bit 2 mask
.equ NVM_FUSES_USERID2_bp = 2 ; User ID bit 2 position
.equ NVM_FUSES_USERID3_bm = (1<<3) ; User ID bit 3 mask
.equ NVM_FUSES_USERID3_bp = 3 ; User ID bit 3 position
.equ NVM_FUSES_USERID4_bm = (1<<4) ; User ID bit 4 mask
.equ NVM_FUSES_USERID4_bp = 4 ; User ID bit 4 position
.equ NVM_FUSES_USERID5_bm = (1<<5) ; User ID bit 5 mask
.equ NVM_FUSES_USERID5_bp = 5 ; User ID bit 5 position
.equ NVM_FUSES_USERID6_bm = (1<<6) ; User ID bit 6 mask
.equ NVM_FUSES_USERID6_bp = 6 ; User ID bit 6 position
.equ NVM_FUSES_USERID7_bm = (1<<7) ; User ID bit 7 mask
.equ NVM_FUSES_USERID7_bp = 7 ; User ID bit 7 position
; NVM_FUSES_FUSEBYTE1 masks
.equ NVM_FUSES_WDWP_gm = 0xF0 ; Watchdog Window Timeout Period group mask
.equ NVM_FUSES_WDWP_gp = 4 ; Watchdog Window Timeout Period group position
.equ NVM_FUSES_WDWP0_bm = (1<<4) ; Watchdog Window Timeout Period bit 0 mask
.equ NVM_FUSES_WDWP0_bp = 4 ; Watchdog Window Timeout Period bit 0 position
.equ NVM_FUSES_WDWP1_bm = (1<<5) ; Watchdog Window Timeout Period bit 1 mask
.equ NVM_FUSES_WDWP1_bp = 5 ; Watchdog Window Timeout Period bit 1 position
.equ NVM_FUSES_WDWP2_bm = (1<<6) ; Watchdog Window Timeout Period bit 2 mask
.equ NVM_FUSES_WDWP2_bp = 6 ; Watchdog Window Timeout Period bit 2 position
.equ NVM_FUSES_WDWP3_bm = (1<<7) ; Watchdog Window Timeout Period bit 3 mask
.equ NVM_FUSES_WDWP3_bp = 7 ; Watchdog Window Timeout Period bit 3 position
.equ NVM_FUSES_WDP_gm = 0x0F ; Watchdog Timeout Period group mask
.equ NVM_FUSES_WDP_gp = 0 ; Watchdog Timeout Period group position
.equ NVM_FUSES_WDP0_bm = (1<<0) ; Watchdog Timeout Period bit 0 mask
.equ NVM_FUSES_WDP0_bp = 0 ; Watchdog Timeout Period bit 0 position
.equ NVM_FUSES_WDP1_bm = (1<<1) ; Watchdog Timeout Period bit 1 mask
.equ NVM_FUSES_WDP1_bp = 1 ; Watchdog Timeout Period bit 1 position
.equ NVM_FUSES_WDP2_bm = (1<<2) ; Watchdog Timeout Period bit 2 mask
.equ NVM_FUSES_WDP2_bp = 2 ; Watchdog Timeout Period bit 2 position
.equ NVM_FUSES_WDP3_bm = (1<<3) ; Watchdog Timeout Period bit 3 mask
.equ NVM_FUSES_WDP3_bp = 3 ; Watchdog Timeout Period bit 3 position
; NVM_FUSES_FUSEBYTE2 masks
.equ NVM_FUSES_DVSDON_bm = 0x80 ; Spike Detector Enable bit mask
.equ NVM_FUSES_DVSDON_bp = 7 ; Spike Detector Enable bit position
.equ NVM_FUSES_BOOTRST_bm = 0x40 ; Boot Loader Section Reset Vector bit mask
.equ NVM_FUSES_BOOTRST_bp = 6 ; Boot Loader Section Reset Vector bit position
.equ NVM_FUSES_BODPD_gm = 0x03 ; BOD Operation in Power-Down Mode group mask
.equ NVM_FUSES_BODPD_gp = 0 ; BOD Operation in Power-Down Mode group position
.equ NVM_FUSES_BODPD0_bm = (1<<0) ; BOD Operation in Power-Down Mode bit 0 mask
.equ NVM_FUSES_BODPD0_bp = 0 ; BOD Operation in Power-Down Mode bit 0 position
.equ NVM_FUSES_BODPD1_bm = (1<<1) ; BOD Operation in Power-Down Mode bit 1 mask
.equ NVM_FUSES_BODPD1_bp = 1 ; BOD Operation in Power-Down Mode bit 1 position
; NVM_FUSES_FUSEBYTE4 masks
.equ NVM_FUSES_RSTDISBL_bm = 0x10 ; External Reset Disable bit mask
.equ NVM_FUSES_RSTDISBL_bp = 4 ; External Reset Disable bit position
.equ NVM_FUSES_SUT_gm = 0x0C ; Start-up Time group mask
.equ NVM_FUSES_SUT_gp = 2 ; Start-up Time group position
.equ NVM_FUSES_SUT0_bm = (1<<2) ; Start-up Time bit 0 mask
.equ NVM_FUSES_SUT0_bp = 2 ; Start-up Time bit 0 position
.equ NVM_FUSES_SUT1_bm = (1<<3) ; Start-up Time bit 1 mask
.equ NVM_FUSES_SUT1_bp = 3 ; Start-up Time bit 1 position
.equ NVM_FUSES_WDLOCK_bm = 0x02 ; Watchdog Timer Lock bit mask
.equ NVM_FUSES_WDLOCK_bp = 1 ; Watchdog Timer Lock bit position
; NVM_FUSES_FUSEBYTE5 masks
.equ NVM_FUSES_BODACT_gm = 0x30 ; BOD Operation in Active Mode group mask
.equ NVM_FUSES_BODACT_gp = 4 ; BOD Operation in Active Mode group position
.equ NVM_FUSES_BODACT0_bm = (1<<4) ; BOD Operation in Active Mode bit 0 mask
.equ NVM_FUSES_BODACT0_bp = 4 ; BOD Operation in Active Mode bit 0 position
.equ NVM_FUSES_BODACT1_bm = (1<<5) ; BOD Operation in Active Mode bit 1 mask
.equ NVM_FUSES_BODACT1_bp = 5 ; BOD Operation in Active Mode bit 1 position
.equ NVM_FUSES_EESAVE_bm = 0x08 ; Preserve EEPROM Through Chip Erase bit mask
.equ NVM_FUSES_EESAVE_bp = 3 ; Preserve EEPROM Through Chip Erase bit position
.equ NVM_FUSES_BODLVL_gm = 0x07 ; Brown Out Detection Voltage Level group mask
.equ NVM_FUSES_BODLVL_gp = 0 ; Brown Out Detection Voltage Level group position
.equ NVM_FUSES_BODLVL0_bm = (1<<0) ; Brown Out Detection Voltage Level bit 0 mask
.equ NVM_FUSES_BODLVL0_bp = 0 ; Brown Out Detection Voltage Level bit 0 position
.equ NVM_FUSES_BODLVL1_bm = (1<<1) ; Brown Out Detection Voltage Level bit 1 mask
.equ NVM_FUSES_BODLVL1_bp = 1 ; Brown Out Detection Voltage Level bit 1 position
.equ NVM_FUSES_BODLVL2_bm = (1<<2) ; Brown Out Detection Voltage Level bit 2 mask
.equ NVM_FUSES_BODLVL2_bp = 2 ; Brown Out Detection Voltage Level bit 2 position
; NVM Command
.equ NVM_CMD_NO_OPERATION_gc = (0x00<<0) ; Noop/Ordinary LPM
.equ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0) ; Read calibration row
.equ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0) ; Read user signature row
.equ NVM_CMD_READ_EEPROM_gc = (0x06<<0) ; Read EEPROM
.equ NVM_CMD_READ_FUSES_gc = (0x07<<0) ; Read fuse byte
.equ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0) ; Write lock bits
.equ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0) ; Erase user signature row
.equ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0) ; Write user signature row
.equ NVM_CMD_ERASE_APP_gc = (0x20<<0) ; Erase Application Section
.equ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0) ; Erase Application Section page
.equ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0) ; Load Flash page buffer
.equ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0) ; Write Application Section page
.equ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0) ; Erase-and-write Application Section page
.equ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0) ; Erase/flush Flash page buffer
.equ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0) ; Erase Boot Section page
.equ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0) ; Write Boot Section page
.equ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0) ; Erase-and-write Boot Section page
.equ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0) ; Erase EEPROM
.equ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0) ; Erase EEPROM page
.equ NVM_CMD_LOAD_EEPROM_BUFFER_gc = <