217 lines
6.5 KiB
NASM
217 lines
6.5 KiB
NASM
; ***************************************************************************
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; copyright : (C) 2025 by Martin Preuss
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; email : martin@libchipcard.de
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;
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; ***************************************************************************
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; * This file is part of the project "AqHome". *
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; * Please see toplevel file COPYING of that project for license details. *
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; ***************************************************************************
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.cseg
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; ---------------------------------------------------------------------------
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; @routine UART_HW_Uart1_Init @global
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;
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
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; @clobbers R16, R17, X
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UART_HW_Uart1_Init:
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M_UART_HW_Uart_Init 1
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_HW_Uart1_StartRx @global
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;
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; @clobbers R16
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UART_HW_Uart1_StartRx:
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M_UART_HW_Uart_StartRx 1
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_HW_Uart1_StopRx @global
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;
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; @clobbers R16
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UART_HW_Uart1_StopRx:
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M_UART_HW_Uart_StopRx 1
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_HW_Uart1_StartTx @global
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;
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
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; @clobbers R16
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UART_HW_Uart1_StartTx:
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M_UART_HW_Uart_StartTx 1
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_HW_Uart1_StopTx @global
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;
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
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; @clobbers R16
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UART_HW_Uart1_StopTx:
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M_UART_HW_Uart_StopTx 1
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_HW_Uart1_Flush
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;
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; Flush receiption buffer.
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;
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
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; @clobbers R16
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UART_HW_Uart1_Flush:
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M_UART_HW_Uart_Flush 1
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_HW_Uart1_RxCharIsr @global
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;
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
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; @clobbers R16 (R17, R18, R24, R25, X)
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UART_HW_Uart1_RxCharIsr:
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; check for errors
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lds r16, UCSR1A ; check for errors
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andi r16, (1<<FE1) | (1<<DOR1) | (1<<UPE1)
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brne UART_HW_Uart1_RxCharIsr_hwerr
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; read char
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lds r16, UCSR1A
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sbrs r16, RXC1
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rjmp UART_HW_Uart1_RxCharIsr_end ; no data
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lds r16, UDR1 ; r16=received char
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; check read mode
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ldd r17, Y+UART_HW_IFACE_OFFS_READMODE
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cpi r17, UART_HW_READMODE_READING
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breq UART_HW_Uart1_RxCharIsr_storeChar
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cpi r17, UART_HW_READMODE_SKIPPING
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breq UART_HW_Uart1_RxCharIsr_skipChar
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rjmp UART_HW_Uart1_RxCharIsr_overrun ; neither read nor skip mode
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UART_HW_Uart1_RxCharIsr_skipChar:
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clr r16
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std Y+NET_IFACE_OFFS_READTIMER, r16 ; reset read timer
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rjmp UART_HW_Uart1_RxCharIsr_end
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UART_HW_Uart1_RxCharIsr_storeChar:
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mov r18, r16 ; r18=received char
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; check buffer
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ldd r16, Y+UART_HW_IFACE_OFFS_READBUFNUM
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cpi r16, 0xff
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breq UART_HW_Uart1_RxCharIsr_overrun
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; check for buffer overrun
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ldd r17, Y+UART_HW_IFACE_OFFS_READBUFLEFT ; r17=bytes left
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tst r17
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breq UART_HW_Uart1_RxCharIsr_econtent ; msg too long
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; actually store byte, increment/decrement counters and pos
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ldd xl, Y+UART_HW_IFACE_OFFS_READBUFPOS_LOW
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ldd xh, Y+UART_HW_IFACE_OFFS_READBUFPOS_HIGH
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st X+, r18 ; r18=byte to store
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clr r16
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std Y+NET_IFACE_OFFS_READTIMER, r16 ; reset read timer
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std Y+UART_HW_IFACE_OFFS_READBUFPOS_LOW, xl
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std Y+UART_HW_IFACE_OFFS_READBUFPOS_HIGH, xh
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ldd r18, Y+UART_HW_IFACE_OFFS_READBUFUSED ; r18=bytes in buffer
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inc r18
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std Y+UART_HW_IFACE_OFFS_READBUFUSED, r18
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dec r17
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std Y+UART_HW_IFACE_OFFS_READBUFLEFT, r17
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breq UART_HW_Uart1_RxCharIsr_msgFinished
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; check msg size
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cpi r18, 2 ; bytes in buffer, exactly 2?
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brne UART_HW_Uart1_RxCharIsr_end ; nope, done
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sbiw xh:xl, 1 ; yes, determine message length (msgLen at previous pos)
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ld r16, X+ ; read payload length byte
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subi r16, -3 ; add 3 (dest addr, length, crc byte)
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cpi r16, (NET_BUFFERS_SIZE-1) ; total msg length ok?
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brcc UART_HW_Uart1_RxCharIsr_econtent ; content error (msg too long)
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subi r16, 2 ; subtract bytes already received
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std Y+UART_HW_IFACE_OFFS_READBUFLEFT, r16 ; set new number of bytes left
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brne UART_HW_Uart1_RxCharIsr_end ; jmp if still bytes left to receive
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UART_HW_Uart1_RxCharIsr_msgFinished:
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ldi r16, NET_IFACE_OFFS_PACKETSIN_LOW
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ldi r17, UART_HW_READMODE_MSGRECEIVED
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rjmp UART_HW_Uart1_RxCharIsr_incCounterAndEnterMode
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UART_HW_Uart1_RxCharIsr_hwerr:
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ldi r16, NET_IFACE_OFFS_ERR_IO_LOW
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rjmp UART_HW_Uart1_RxCharIsr_incCounterAndEnterSkipping
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UART_HW_Uart1_RxCharIsr_econtent:
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ldi r16, NET_IFACE_OFFS_ERR_CONTENT_LOW
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rjmp UART_HW_Uart1_RxCharIsr_incCounterAndEnterSkipping
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UART_HW_Uart1_RxCharIsr_overrun:
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; ldi r16, NET_IFACE_OFFS_ERR_NOBUF_LOW
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ldi r16, NET_IFACE_OFFS_ERR_MISSED_LOW
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UART_HW_Uart1_RxCharIsr_incCounterAndEnterSkipping:
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ldi r17, UART_HW_READMODE_SKIPPING
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ldi r16, NET_IFACE_OFFS_HANDLED_LOW
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UART_HW_Uart1_RxCharIsr_incCounterAndEnterMode:
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rcall NET_Interface_IncCounter16 ; (R24, R25)
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std Y+UART_HW_IFACE_OFFS_READMODE, r17 ; set read mode
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UART_HW_Uart1_RxCharIsr_end:
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ret
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; @end
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_HW_Uart1_TxUdreIsr @global
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;
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; Handler for UDRE1 interrupt called when TX data register is empty.
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;
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
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; @clobbers R16, R17, X
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UART_HW_Uart1_TxUdreIsr:
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M_UART_HW_Uart_TxUdreIsr 1
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_HW_Uart1_TxCharIsr @global
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;
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; Handler for TXC1 interrupt called when a last byte has been completely sent and
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; the data register is empty.
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;
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
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; @clobbers R16
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UART_HW_Uart1_TxCharIsr:
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M_UART_HW_Uart_TxCharIsr 1
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ret
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; @end
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