531cf49a6f
Directly use pins, no complicated redirections. Router modules will probably use real UARTs or MCUs programmed as UARTs.
97 lines
2.0 KiB
NASM
97 lines
2.0 KiB
NASM
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; Utils_WaitNanoSecs waittime_in_ns , cyles_already_used , waitcount_register
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;
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; cycles already used will be subtracted from the delay
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; the waittime resolution is 1 cycle (delay from exact to +1 cycle)
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; the maximum delay at 20MHz (50ns/clock) is 38350ns
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; waitcount register must specify an immediate register
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; taken from https://www.mikrocontroller.net/articles/AVR_Assembler_Makros#Verz%C3%B6gerung_um_X_Nanosekunden
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;
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.set Osc_Hz = clock ; 1 MHz
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.set cycle_time_ns = (1000000000 / Osc_Hz) ; clock duration
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.macro Utils_WaitNanoSecs
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.set cycles = ((@0 + cycle_time_ns - 1) / cycle_time_ns - @1)
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.if (cycles > (255 * 3 + 2))
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.error "MACRO Utils_WaitNanoSecs - too many cycles to burn"
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.else
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.if (cycles > 6)
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.set loop_cycles = (cycles / 3)
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ldi @2,loop_cycles
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dec @2
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brne pc-1
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.set cycles = (cycles - (loop_cycles * 3))
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.endif
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.if (cycles > 0)
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.if (cycles & 4)
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rjmp pc+1
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rjmp pc+1
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.endif
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.if (cycles & 2)
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rjmp pc+1
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.endif
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.if (cycles & 1)
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nop
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.endif
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.endif
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.endif
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.endmacro
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; ***************************************************************************
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; Utils_FillSram
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;
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; IN:
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; - x: pointer to SRAM to fill
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; - r16: value to fill the SRAM with
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; - r17: size of area to fill
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; OUT:
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; - nothing
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; MODIFIED REGISTERS: r17, x
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Utils_FillSram:
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tst r17
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breq Utils_FillSram_end
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Utils_FillSram_loop:
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st x+, r16
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dec r17
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brne Utils_FillSram_loop
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Utils_FillSram_end:
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ret
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; ***************************************************************************
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; Increment a 32 bit counter at the address given by X.
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; IN:
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; - X: Address of the 4 byte counter (1. byte is LSB)
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; OUT:
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; - nothing
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; MODIFIED REGISTERS: r18, r19, r20, r21, 22
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Utils_IncrementCounter32:
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ld r18, x+
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ld r19, x+
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ld r20, x+
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ld r21, x
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clr r22
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inc r18
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adc r19, r22
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adc r20, r22
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adc r21, r22
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st x, r21
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st -x, r20
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st -x, r19
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st -x, r18
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ret
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