318 lines
9.3 KiB
NASM
318 lines
9.3 KiB
NASM
; ***************************************************************************
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; copyright : (C) 2025 by Martin Preuss
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; email : martin@libchipcard.de
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;
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; ***************************************************************************
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; * This file is part of the project "AqHome". *
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; * Please see toplevel file COPYING of that project for license details. *
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; ***************************************************************************
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; ---------------------------------------------------------------------------
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; @macro M_UART_HW_Uart_Init
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;
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; @param %0 UART number ("0" for UART0)
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; @param Y pointer to interface data in SRAM
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; @clobbers R16, R17, X
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.macro M_UART_HW_Uart_Init
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rcall NET_Interface_Init
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; set baudrate
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.if clock == 8000000
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ldi r16, 25 ; (19.2Kb/s at 8MHz)
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ldi r17, 0
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.endif
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.if clock == 1000000
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ldi r16, 2 ; (19.2Kb/s at 1MHz)
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ldi r17, 0
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.endif
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sts UBRR@0H, r17
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sts UBRR@0L, r16
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; set character format
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ldi r16, (1<<USBS@0)|(3<<UCSZ@00)
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sts UCSR@0C, r16
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.endmacro
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; @end
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; ---------------------------------------------------------------------------
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; @macro M_UART_HW_Uart_StartRx
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;
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; @param %0 UART number ("0" for UART0)
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; @clobbers none
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.macro M_UART_HW_Uart_StartRx
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lds r16, UCSR@0B
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sbr r16, (1<<RXCIE@0) | (1<<RXEN@0) ; enable RX complete interrupt, enable receive
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sts UCSR@0B, r16
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.endmacro
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; @end
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; ---------------------------------------------------------------------------
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; @macro M_UART_HW_Uart_StopRx
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;
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; @param %0 UART number ("0" for UART0)
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; @clobbers R16
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.macro M_UART_HW_Uart_StopRx
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lds r16, UCSR@0B
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cbr r16, (1<<RXCIE@0 | (1<<RXEN@0)) ; disable RX complete interrupt, disable receive
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sts UCSR@0B, r16
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.endmacro
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; @end
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; ---------------------------------------------------------------------------
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; @macro M_UART_HW_Uart_StartTx
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;
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; @param %0 UART number ("0" for UART0)
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; @param Y pointer to interface data in SRAM
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; @clobbers R16
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.macro M_UART_HW_Uart_StartTx
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lds r16, UCSR@0A
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cbr r16, (1<<TXC@0) ; clear TXCn interrupt
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sts UCSR@0A, r16
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lds r16, UCSR@0B
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sbr r16, (1<<UDRIE@0) | (1<<TXC@0) | (1<<TXEN@0) ; enable TX UDRE and TXC1 interrupt, enable transceive
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sts UCSR@0B, r16
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.endmacro
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; @end
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; ---------------------------------------------------------------------------
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; @macro M_UART_HW_Uart_StopTx
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;
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; @param %0 UART number ("0" for UART0)
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; @param Y pointer to interface data in SRAM
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; @clobbers R16
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.macro M_UART_HW_Uart_StopTx
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lds r16, UCSR@0B
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cbr r16, (1<<UDRIE@0) | (1<<TXC@0) | (1<<TXEN@0) ; disable TX UDRE and TXC1 interrupt, enable transceive
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sts UCSR@0B, r16
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.endmacro
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; @end
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; ---------------------------------------------------------------------------
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; @macro M_UART_HW_Uart_Flush
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;
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; Flush receiption buffer.
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;
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; @param %0 UART number ("0" for UART0)
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; @param Y pointer to interface data in SRAM
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; @clobbers R16
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.macro M_UART_HW_Uart_Flush
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l_loop_%:
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lds r16, UCSR@0A
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sbrs r16, RXC@0
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rjmp l_end_%
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lds r16, UDR@0
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clr r16
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std Y+NET_IFACE_OFFS_READTIMER, r16
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rjmp l_loop_%
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l_end_%:
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.endmacro
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; @end
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; ---------------------------------------------------------------------------
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; @macro M_UART_HW_Uart_RxCharIsr
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;
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; @param %0 UART number ("0" for UART0)
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; @param Y pointer to interface data in SRAM
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; @clobbers R16 (R17, R18, R24, R25, X)
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.macro M_UART_HW_Uart_RxCharIsr
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; check for errors
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lds r16, UCSR@0A ; check for errors
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andi r16, (1<<FE@0) | (1<<DOR@0) | (1<<UPE@0)
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brne l_hwerr_%
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; read char
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lds r16, UCSR@0A
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sbrs r16, RXC@0
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rjmp l_end_% ; no data
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lds r16, UDR@0 ; r16=received char
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; check read mode
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ldd r17, Y+UART_HW_IFACE_OFFS_READMODE
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cpi r17, UART_HW_READMODE_READING
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breq l_storeChar_%
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cpi r17, UART_HW_READMODE_SKIPPING
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breq l_skipChar_%
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rjmp l_overrun_% ; neither read nor skip mode
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l_skipChar_%:
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clr r16
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std Y+NET_IFACE_OFFS_READTIMER, r16 ; reset read timer
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rjmp l_end_%
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l_storeChar_%:
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mov r18, r16 ; r18=received char
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; check for buffer overrun
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ldd r17, Y+UART_HW_IFACE_OFFS_READBUFLEFT ; r17=bytes left
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tst r17
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breq l_econtent_% ; msg too long
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; actually store byte, increment/decrement counters and pos
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ldd xl, Y+UART_HW_IFACE_OFFS_READBUFPOS_LOW
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ldd xh, Y+UART_HW_IFACE_OFFS_READBUFPOS_HIGH
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st X+, r18 ; r18=byte to store
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clr r16
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std Y+NET_IFACE_OFFS_READTIMER, r16 ; reset read timer
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std Y+UART_HW_IFACE_OFFS_READBUFPOS_LOW, xl
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std Y+UART_HW_IFACE_OFFS_READBUFPOS_HIGH, xh
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ldd r18, Y+UART_HW_IFACE_OFFS_READBUFUSED ; r18=bytes in buffer
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inc r18
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std Y+UART_HW_IFACE_OFFS_READBUFUSED, r18
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dec r17
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std Y+UART_HW_IFACE_OFFS_READBUFLEFT, r17
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breq l_msgFinished_%
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; check msg size
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cpi r18, 2 ; bytes in buffer, exactly 2?
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brne l_end_% ; nope, done
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sbiw xh:xl, 1 ; yes, determine message length (msgLen at previous pos)
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ld r16, X+ ; read payload length byte
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subi r16, -3 ; add 3 (dest addr, length, crc byte)
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cpi r16, (NET_BUFFERS_SIZE-1) ; total msg length ok?
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brcc l_econtent_% ; content error (msg too long)
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subi r16, 2 ; subtract bytes already received
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std Y+UART_HW_IFACE_OFFS_READBUFLEFT, r16 ; set new number of bytes left
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brne l_end_% ; jmp if still bytes left to received
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l_msgFinished_%:
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ldd r16, Y+UART_HW_IFACE_OFFS_READBUFNUM
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rcall NET_AddIncomingMsgNum ; (R17, R18, X)
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brcs l_msgStored_%
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; msg complete but could not store
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rcall NET_Buffer_Locate
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rcall UART_HW_Interface_SetReadBuffer ; reset/reuse current buffer
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ldi r16, NET_IFACE_OFFS_ERR_NOBUF_LOW
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ldi r17, UART_HW_READMODE_READING
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rjmp l_incCounterAndEnterMode_%
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l_msgStored_%:
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ldi r16, NET_IFACE_OFFS_PACKETSIN_LOW
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ldi r17, UART_HW_READMODE_MSGRECEIVED
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rjmp l_incCounterAndEnterMode_%
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l_hwerr_%:
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ldi r16, NET_IFACE_OFFS_ERR_IO_LOW
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rcall NET_Interface_IncCounter16
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ldi r16, UART_HW_READMODE_SKIPPING
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std Y+UART_HW_IFACE_OFFS_READMODE, r16 ; set read mode
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rjmp l_end_%
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l_econtent_%:
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ldi r16, NET_IFACE_OFFS_ERR_CONTENT_LOW
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rjmp l_incCounterAndEnterSkipping_%
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l_overrun_%:
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ldi r16, NET_IFACE_OFFS_ERR_NOBUF_LOW
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l_incCounterAndEnterSkipping_%:
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ldi r17, UART_HW_READMODE_SKIPPING
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l_incCounterAndEnterMode_%:
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rcall NET_Interface_IncCounter16 ; (R24, R25)
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std Y+UART_HW_IFACE_OFFS_READMODE, r17 ; set read mode
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l_end_%:
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.endmacro
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; @end
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; ---------------------------------------------------------------------------
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; @macro M_UART_HW_Uart_TxUdreIsr
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;
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; Handler for UDREn interrupt called when TX data register is empty.
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;
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; @param %0 UART number ("0" for UART0)
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; @param Y pointer to interface data in SRAM
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; @clobbers R16, R17, X
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.macro M_UART_HW_Uart_TxUdreIsr
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lds r16, UCSR@0A
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sbrs r16,UDRE@0
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rjmp l_disable_irq_% ; not ready
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; check write mode
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ldd r16, Y+UART_HW_IFACE_OFFS_WRITEMODE
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cpi r16, UART_HW_WRITEMODE_WRITING
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brne l_disable_irq_% ; not in writing mode
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; check whether we have an active write buffer
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ldd r16, Y+UART_HW_IFACE_OFFS_WRITEBUFNUM
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cpi r16, 0xff
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breq l_disable_irq_% ; no buffer
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; check whether there is data in the buffer to send
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ldd r17, Y+UART_HW_IFACE_OFFS_WRITEBUFLEFT ; r17=bytes left
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tst r17
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breq l_disable_irq_% ; nothing left to write
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; get read ptr, read byte, inc read ptr, store ptr and bytesLeft
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ldd xl, Y+UART_HW_IFACE_OFFS_WRITEBUFPOS_LOW
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ldd xh, Y+UART_HW_IFACE_OFFS_WRITEBUFPOS_HIGH
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ld r16, X+ ; r16=byte to write
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std Y+UART_HW_IFACE_OFFS_WRITEBUFPOS_LOW, xl
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std Y+UART_HW_IFACE_OFFS_WRITEBUFPOS_HIGH, xh
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dec r17
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std Y+UART_HW_IFACE_OFFS_WRITEBUFLEFT, r17
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; send byte, reset write timer
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sts UDR@0, r16
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clr r16
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std Y+NET_IFACE_OFFS_WRITETIMER, r16 ; reset write timer
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; still bytes left to write?
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tst r17
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brne l_end_%
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ldi r16, UART_HW_WRITEMODE_WAITBUFFEREMPTY
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std Y+UART_HW_IFACE_OFFS_WRITEMODE, r16 ; change mode to WAITBUFFEREMPTY
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l_disable_irq_%:
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; disable further DRE1 interrupts
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lds r16, UCSR@0B
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cbr r16, (1<<UDRIE@0) ; disable TX data register empty interrupt
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sts UCSR@0B, r16
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l_end_%:
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.endmacro
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; @end
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; ---------------------------------------------------------------------------
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; @macro M_UART_HW_Uart_TxCharIsr
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;
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; Handler for TXCn interrupt called when a last byte has been completely sent and
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; the data register is empty.
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;
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; @param %0 UART number ("0" for UART0)
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; @param Y pointer to interface data in SRAM
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; @clobbers R16
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.macro M_UART_HW_Uart_TxCharIsr
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; check write mode
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ldd r16, Y+UART_HW_IFACE_OFFS_WRITEMODE
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cpi r16, UART_HW_WRITEMODE_WAITBUFFEREMPTY
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brne l_end_%
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; disable further TXC1 interrupts
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lds r16, UCSR@0B
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cbr r16, (1<<TXC@0) ; disable TXC1 interrupt
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sts UCSR@0B, r16
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; change write mode to WRITEBUFFEREMPTY
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ldi r16, UART_HW_WRITEMODE_WRITEBUFFEREMPTY
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std Y+UART_HW_IFACE_OFFS_WRITEMODE, r16
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l_end_%:
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.endmacro
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; @end
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