avr: more work on hardware-based UART module.
This commit is contained in:
Martin Preuss
315
avr/modules/uart_hw/raw_uart1.asm
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315
avr/modules/uart_hw/raw_uart1.asm
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; ***************************************************************************
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; copyright : (C) 2025 by Martin Preuss
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; email : martin@libchipcard.de
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;
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; ***************************************************************************
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; * This file is part of the project "AqHome". *
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; * Please see toplevel file COPYING of that project for license details. *
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; ***************************************************************************
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; ---------------------------------------------------------------------------
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; @routine UART_HW_Uart1_RawInit @global
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;
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; @clobbers R16, R17
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UART_HW_Uart1_RawInit:
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; set baudrate
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;.if clock == 8000000
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; ldi r16, 25 ; (19.2Kb/s at 8MHz)
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; ldi r17, 0
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;.endif
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;.if clock == 1000000
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ldi r16, 3 ; (19.2Kb/s at 1MHz)
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ldi r17, 0
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;.endif
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sts UBRR1H, r17
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sts UBRR1L, r16
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; set character format (asynchronous USART, 8-bit, one stop bit, no parity)
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ldi r16, (3<<UCSZ10)
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sts UCSR1C, r16
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_HW_Uart1_RawSendPacket
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; Send packet.
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;
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; @param X buffer to send
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; @return CFLAG: set if okay (packet sent), cleared on error
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; @clobbers r16, r17, X
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UART_HW_Uart1_RawSendPacket:
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adiw xh:xl, 1
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ld r17, X
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sbiw xh:xl, 1
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ldi r16, 3 ; add DEST, LEN, CRC bytes
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add r17, r16
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lds r16, UCSR1B
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; cbr r16, (1<<UDRIE1) ; disable DRE interrupt
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sbr r16, (1<<TXEN1) ; enable transmit
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sts UCSR1B, r16
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;; clr r16 ; clear all pending interrupts
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;; sts UCSR1A, r16
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;ldi r17, 20
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UART_HW_Uart1_RawSendPacket_loop:
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lds r16, UCSR1A
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sbrs r16, UDRE1
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rjmp UART_HW_Uart1_RawSendPacket_loop
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sbr r16, (1<<TXC1)
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sts UCSR1A, r16
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ld r16, X+
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sts UDR1, r16
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dec r17
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brne UART_HW_Uart1_RawSendPacket_loop
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; disable transmit
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; lds r16, UCSR1B
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; cbr r16, (1<<TXEN1) ; disable transmit
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; sts UCSR1B, r16
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sec
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_HW_Uart1_EnableRawRecv @global
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;
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; Enable receiving messages in raw mode.
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;
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; @clobbers: r16
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UART_HW_Uart1_EnableRawRecv:
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lds r16, UCSR1B
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cbr r16, (1<<RXCIE1) ; disable RX complete interrupt
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sbr r16, (1<<RXEN1) ; enable receive
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sts UCSR1B, r16
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_HW_Uart1_DisableRawRecv @global
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;
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; Disable receiving messages in raw mode.
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;
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; @clobbers: r16
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UART_HW_Uart1_DisableRawRecv:
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lds r16, UCSR1B
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cbr r16, (1<<RXCIE1) ; disable RX complete interrupt
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cbr r16, (1<<RXEN1) ; disable receive
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sts UCSR1B, r16
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_HW_Uart1_RawRecvPacket
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; Receive packet.
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;
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; @param R16 COM address to listen to
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; @param R17 maximum value for accepted msg data (i.e. buffersize minus 3)
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; @param R18 max number of secs to wait for incoming message
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; @param X buffer to receive to
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; @return CFLAG set if okay (packet received), cleared on error
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; @return R16 error code if CFLAG is cleared (COM2_ERROR_NOTFORME, COM2_ERROR_IOERROR, COM2_ERROR_DATAERROR)
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; @clobbers: r16, r17, r18, r19, r22, X
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UART_HW_Uart1_RawRecvPacket:
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; wait for data
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push r16
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mov r16, r18
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rcall uartHwUart1RawWaitForByte ; (r16, r18, r22)
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pop r16
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brcc UART_HW_Uart1_RawRecvPacket_error
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; data available, start reading
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mov r19, r17 ; max msg payload size
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push r16
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; read destination address
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rcall uartHwUart1RawRecvByte ; (R16, R18, R22)
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pop r17 ; pop acceptable COM address from R16 to R17
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brcc UART_HW_Uart1_RawRecvPacket_error
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#ifndef COM_ACCEPT_ALL_DEST ; accept every destination address
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; compare destination address (accept "FF" and own address)
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cp r16, r17
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breq UART_HW_Uart1_RawRecvPacket_acceptAddr
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cpi r16, 0xff
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breq UART_HW_Uart1_RawRecvPacket_acceptAddr
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ldi r16, COM2_ERROR_NOTFORME
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rjmp UART_HW_Uart1_RawRecvPacket_error
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#endif
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UART_HW_Uart1_RawRecvPacket_acceptAddr:
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st X+, r16
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; read msg length
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rcall uartHwUart1RawRecvByte ; (R16, R18, R22)
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brcc UART_HW_Uart1_RawRecvPacket_error
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cp r16, r19 ; (COM2_BUFFER_SIZE-3)
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brcc UART_HW_Uart1_RawRecvPacket_error
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tst r16
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breq UART_HW_Uart1_RawRecvPacket_error
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st X+, r16
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inc r16
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mov r17, r16
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; read message content
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UART_HW_Uart1_RawRecvPacket_loop:
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rcall uartHwUart1RawRecvByte ; (R16, R18, R22)
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brcc UART_HW_Uart1_RawRecvPacket_error
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st X+, r16
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dec r17
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brne UART_HW_Uart1_RawRecvPacket_loop
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sec
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rjmp UART_HW_Uart1_RawRecvPacket_end
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UART_HW_Uart1_RawRecvPacket_error:
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clc
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UART_HW_Uart1_RawRecvPacket_end:
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine uartHwUart1RawRecvByte
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; Receive one byte.
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;
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; @return CFLAG set if okay, cleared on error
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; @return R16 error code if CFLAG is cleared
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; @clobbers: r16 (r18, r22)
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uartHwUart1RawRecvByte:
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rcall uartHwUart1RawWaitForByte1ms ; (r18, r22)
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brcc uartHwUart1RawRecvByte_error
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lds r16, UCSR1A ; check for errors
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andi r16, (1<<FE1) | (1<<DOR1) | (1<<UPE1)
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brne uartHwUart1RawRecvByte_error
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lds r16, UDR1
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sec
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ret
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uartHwUart1RawRecvByte_error:
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ldi r16, COM2_ERROR_IOERROR
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clc
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine uartHwUart1RawWaitForByte
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; wait for up to given number of secs for incoming byte
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;
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; @return CFLAG set if okay, cleared on error
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; @param r16 number of secs to wait
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; @clobbers: r16, r18, r22
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uartHwUart1RawWaitForByte:
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uartHwUart1RawWaitForByte_loop:
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rcall uartHwUart1RawWaitForByte1s ; (r18, r22)
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brcs uartHwUart1RawWaitForByte_haveByte
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dec r16
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brne uartHwUart1RawWaitForByte_loop
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clc
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uartHwUart1RawWaitForByte_haveByte:
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine uartHwUart1RawWaitForByte1s
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; wait for up to 1s for incoming byte
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;
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; @return CFLAG set if okay, cleared on error
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; @clobbers: r18, r22
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uartHwUart1RawWaitForByte1s:
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ldi r18, 10
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uartHwUart1RawWaitForByte1s_loop:
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push r18
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rcall uartHwUart1RawWaitForByte100ms ; (r18, r22)
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pop r18
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brcs uartHwUart1RawWaitForByte1s_haveByte
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; sbi LED_SIMPLE_PORTIN, LED_SIMPLE_PINNUM ; toggle
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dec r18
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brne uartHwUart1RawWaitForByte1s_loop
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clc
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uartHwUart1RawWaitForByte1s_haveByte:
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine uartHwUart1RawWaitForByte100ms
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; wait for up to 100ms for incoming byte
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;
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; @return CFLAG set if okay, cleared on error
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; @clobbers: r18, r22
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uartHwUart1RawWaitForByte100ms:
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ldi r18, 100
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uartHwUart1RawWaitForByte100ms_loop:
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push r18
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rcall uartHwUart1RawWaitForByte1ms
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pop r18
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brcs uartHwUart1RawWaitForByte100ms_haveByte
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dec r18
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brne uartHwUart1RawWaitForByte100ms_loop
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clc
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uartHwUart1RawWaitForByte100ms_haveByte:
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine uartHwUart1RawWaitForByte1ms
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; wait for up to 1ms for incoming byte
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;
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; @return CFLAG set if okay, cleared on error
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; @clobbers: r18, r22
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uartHwUart1RawWaitForByte1ms:
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ldi r18, 100
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uartHwUart1RawWaitForByte1ms_loop:
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lds r22, UCSR1A
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sbrc r22, RXC1
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rjmp uartHwUart1RawWaitForByte1ms_haveByte
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rcall Utils_WaitFor10MicroSecs ; wait for 10us (R22)
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dec r18
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brne uartHwUart1RawWaitForByte1ms_loop
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clc
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ret
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uartHwUart1RawWaitForByte1ms_haveByte:
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sec
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ret
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; @end
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.equ COMIO_RawSendPacket = UART_HW_Uart1_RawSendPacket
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.equ COMIO_RawRecvPacket = UART_HW_Uart1_RawRecvPacket
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.equ COMIO_EnableRawRecv = UART_HW_Uart1_EnableRawRecv
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.equ COMIO_DisableRawRecv = UART_HW_Uart1_DisableRawRecv
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