From ecb2d85ea2fdc4cfab50c4744ea5fdc5fb645026 Mon Sep 17 00:00:00 2001
From: Martin Preuss <martin@aquamaniac.de>
Date: Sun, 19 Jan 2025 15:46:21 +0100
Subject: [PATCH] avr: more work on hardware-based UART module.

---
 avr/modules/uart_hw/buffers.asm        |  72 ------
 avr/modules/uart_hw/defs.asm           |  56 ++---
 avr/modules/uart_hw/lowlevel.asm       |  77 ++++--
 avr/modules/uart_hw/lowlevel_uart1.asm | 135 +++++++++++
 avr/modules/uart_hw/raw_uart1.asm      | 315 +++++++++++++++++++++++++
 5 files changed, 534 insertions(+), 121 deletions(-)
 create mode 100644 avr/modules/uart_hw/lowlevel_uart1.asm
 create mode 100644 avr/modules/uart_hw/raw_uart1.asm

diff --git a/avr/modules/uart_hw/buffers.asm b/avr/modules/uart_hw/buffers.asm
index 29385d2..ec5aee2 100644
--- a/avr/modules/uart_hw/buffers.asm
+++ b/avr/modules/uart_hw/buffers.asm
@@ -13,13 +13,6 @@
 uartHwDataBegin:
   ; fixed buffers for incoming and outgoing messages
   uartHw_buffers:             .byte UART_HW_FIXEDBUFFERS_NUM*UART_HW_FIXEDBUFFERS_SIZE
-
-  ; ringbuffer for buffer numbers of incoming msgs
-  uartHw_ringBufferMsgNumIn:  .byte RINGBUFFERY_OFFS_DATA+UART_HW_MSGNUMINBUF_SIZE
-
-  ; ringbuffer for buffer numbers of outgoing msgs
-  uartHw_ringBufferMsgNumOut: .byte RINGBUFFERY_OFFS_DATA+UART_HW_MSGNUMOUTBUF_SIZE
-
 uartHwDataEnd:
 
 
@@ -106,68 +99,3 @@ UART_HW_FixedBuffers_Locate_end:
 
 
 
-; ---------------------------------------------------------------------------
-; @routine UART_HW_AddIncomingMsg @global
-;
-; @return CFLAG set if buffer available, cleared otherwise
-; @return r16 buffer num
-; @return X pointer to start of buffer
-; @clobbers R17, R18, X, Y
-
-UART_HW_AddIncomingMsg:
-  ldi yl, LOW(uartHw_ringBufferMsgNumIn)
-  ldi yh, HIGH(uartHw_ringBufferMsgNumIn)
-  rjmp RingBufferY_WriteByte              ; (R17, R18, X)
-; @end
-
-
-
-; ---------------------------------------------------------------------------
-; @routine UART_HW_GetNextIncomingMsg @global
-;
-; @return CFLAG set if buffer available, cleared otherwise
-; @return r16 buffer num
-; @return X pointer to start of buffer
-; @clobbers R17, R18, X, Y
-
-UART_HW_GetNextIncomingMsg:
-  ldi yl, LOW(uartHw_ringBufferMsgNumIn)
-  ldi yh, HIGH(uartHw_ringBufferMsgNumIn)
-  rjmp RingBufferY_ReadByte               ; (R17, R18, X)
-; @end
-
-
-
-; ---------------------------------------------------------------------------
-; @routine UART_HW_AddOutgoingMsg @global
-;
-; @return CFLAG set if buffer available, cleared otherwise
-; @return r16 buffer num
-; @return X pointer to start of buffer
-; @clobbers R17, R18, X, Y
-
-UART_HW_AddOutgoingMsg:
-  ldi yl, LOW(uartHw_ringBufferMsgNumOut)
-  ldi yh, HIGH(uartHw_ringBufferMsgNumOut)
-  rjmp RingBufferY_WriteByte              ; (R17, R18, X)
-; @end
-
-
-
-; ---------------------------------------------------------------------------
-; @routine UART_HW_GetNextOutgoingMsg @global
-;
-; @return CFLAG set if buffer available, cleared otherwise
-; @return r16 buffer num
-; @return X pointer to start of buffer
-; @clobbers R17, R18, X, Y
-
-UART_HW_GetNextOutgoingMsg:
-  ldi yl, LOW(uartHw_ringBufferMsgNumOut)
-  ldi yh, HIGH(uartHw_ringBufferMsgNumOut)
-  rjmp RingBufferY_ReadByte               ; (R17, R18, X)
-; @end
-
-
-
-
diff --git a/avr/modules/uart_hw/defs.asm b/avr/modules/uart_hw/defs.asm
index c256ad3..336db9b 100644
--- a/avr/modules/uart_hw/defs.asm
+++ b/avr/modules/uart_hw/defs.asm
@@ -8,47 +8,41 @@
 ; ***************************************************************************
 
 
-.equ UART_HW_MSGNUMINBUF_SIZE          = 8
-.equ UART_HW_MSGNUMOUTBUF_SIZE         = 4
-
-.equ UART_HW_FIXEDBUFFERS_NUM          = 6
-.equ UART_HW_FIXEDBUFFERS_SIZE         = 32 ; adapt UART_HW_FixedBuffers_Locate if you change this value!
+.equ UART_HW_IFACE_READBUF_SIZE        = 8
+.equ UART_HW_IFACE_WRITEBUF_SIZE       = 8
 
 
+.equ UART_HW_MODE_OFF                  = 0
+.equ UART_HW_MODE_IDLE                 = 1
+.equ UART_HW_MODE_READING              = 2
+.equ UART_HW_MODE_WRITING              = 4
+.equ UART_HW_MODE_SKIPPING             = 8
 
-.equ UART_HW_STATE_OFF                 = 0
-.equ UART_HW_STATE_IDLE                = 1
-.equ UART_HW_STATE_READING             = 2
-.equ UART_HW_STATE_WRITING             = 3
-.equ UART_HW_STATE_SKIPPING            = 4
-
-.equ UART_HW_IFACE_MSGIDBUF_SIZE       = 8
-.equ UART_HW_IFACE_READBUF_SIZE        = 24
 
+.equ UART_HW_STATUS_UNDERRUN           = 0x01
+.equ UART_HW_STATUS_OVERRUN            = 0x02
+.equ UART_HW_STATUS_HWERR              = 0x04
+.equ UART_HW_STATUS_ATTN               = 0x80
 
 
 .equ UART_HW_IFACE_OFFS_MODE           = 0
 .equ UART_HW_IFACE_OFFS_STATUS         = 1
-.equ UART_HW_IFACE_OFFS_READBUFFERNUM  = 2  ; num of buffer currently read
-.equ UART_HW_IFACE_OFFS_READBUFFERPOS  = 3  ; current pos in readbuffer
-.equ UART_HW_IFACE_OFFS_READBUFFERLEFT = 4  ; bytes left to read for current message
+.equ UART_HW_IFACE_OFFS_READTIMER      = 2
 
-.equ UART_HW_IFACE_OFFS_WRITEBUFFERNUM = 5  ; num of buffer currently written from to network
-.equ UART_HW_IFACE_OFFS_WRITEBUFFERPTR = 6  ; pointer to next pos in current write buffer to write from (2 bytes)
-.equ UART_HW_IFACE_OFFS_WRITEBUFFERLEFT= 8  ; bytes left to write for current message
+.equ UART_HW_IFACE_OFFS_READBUF        = 3  ; ringbuffer for incoming chars
+.equ UART_HW_IFACE_OFFS_READBUF_MAX    = UART_HW_IFACE_OFFS_READBUF
+.equ UART_HW_IFACE_OFFS_READBUF_USED   = UART_HW_IFACE_OFFS_READBUF+1
+.equ UART_HW_IFACE_OFFS_READBUF_RDPOS  = UART_HW_IFACE_OFFS_READBUF+2
+.equ UART_HW_IFACE_OFFS_READBUF_WRPOS  = UART_HW_IFACE_OFFS_READBUF+3
+.equ UART_HW_IFACE_OFFS_READBUF_DATA   = UART_HW_IFACE_OFFS_READBUF+4 ; UART_HW_IFACE_READBUF_SIZE bytes
 
-.equ UART_HW_IFACE_OFFS_RINGBUF_MAX    = 9
-.equ UART_HW_IFACE_OFFS_RINGBUF_USED   = 10 ; ringbuffer for incoming chars
-.equ UART_HW_IFACE_OFFS_RINGBUF_RDPOS  = 11
-.equ UART_HW_IFACE_OFFS_RINGBUF_WRPOS  = 12
-.equ UART_HW_IFACE_OFFS_RINGBUF_DATA   = 13
+.equ UART_HW_IFACE_OFFS_WRITEBUF       = UART_HW_IFACE_OFFS_READBUF_DATA+UART_HW_IFACE_READBUF_SIZE
+.equ UART_HW_IFACE_OFFS_WRITEBUF_MAX   = UART_HW_IFACE_OFFS_WRITEBUF
+.equ UART_HW_IFACE_OFFS_WRITEBUF_USED  = UART_HW_IFACE_OFFS_WRITEBUF+1
+.equ UART_HW_IFACE_OFFS_WRITEBUF_RDPOS = UART_HW_IFACE_OFFS_WRITEBUF+2
+.equ UART_HW_IFACE_OFFS_WRITEBUF_WRPOS = UART_HW_IFACE_OFFS_WRITEBUF+3
+.equ UART_HW_IFACE_OFFS_WRITEBUF_DATA  = UART_HW_IFACE_OFFS_WRITEBUF+4
 
-.equ UART_HW_IFACE_OFFS_MSGIDBUF_MAX   = UART_HW_IFACE_OFFS_RINGBUF_DATA+14 ; ringbuffer for ids of outbound messages
-.equ UART_HW_IFACE_OFFS_MSGIDBUF_USED  = UART_HW_IFACE_OFFS_RINGBUF_DATA+15 ; ringbuffer for ids of outbound messages
-.equ UART_HW_IFACE_OFFS_MSGIDBUF_RDPOS = UART_HW_IFACE_OFFS_RINGBUF_DATA+16
-.equ UART_HW_IFACE_OFFS_MSGIDBUF_WRPOS = UART_HW_IFACE_OFFS_RINGBUF_DATA+17
-.equ UART_HW_IFACE_OFFS_MSGIDBUF_DATA  = UART_HW_IFACE_OFFS_RINGBUF_DATA+18
-
-.equ UART_HW_IFACE_SIZE                = UART_HW_IFACE_OFFS_MSGIDBUF_DATA+UART_HW_IFACE_MSGIDBUF_SIZE
+.equ UART_HW_IFACE_SIZE                = UART_HW_IFACE_OFFS_WRITEBUF_DATA+UART_HW_IFACE_WRITEBUF_SIZE
 
 
diff --git a/avr/modules/uart_hw/lowlevel.asm b/avr/modules/uart_hw/lowlevel.asm
index e7d2a7f..403d121 100644
--- a/avr/modules/uart_hw/lowlevel.asm
+++ b/avr/modules/uart_hw/lowlevel.asm
@@ -57,35 +57,33 @@ UART_HW_InterfaceInit:
   clr r16
   rcall Utils_FillSram         ; (R17, X)
   m_ringbuffer_y_reset UART_HW_IFACE_READBUF_SIZE, \
-                       UART_HW_IFACE_OFFS_RINGBUF_USED, \
-                       UART_HW_IFACE_OFFS_RINGBUF_RDPOS, \
-                       UART_HW_IFACE_OFFS_RINGBUF_WRPOS, \
-                       UART_HW_IFACE_OFFS_RINGBUF_DATA
-  m_ringbuffer_y_reset UART_HW_IFACE_MSGIDBUF_SIZE, \
-                       UART_HW_IFACE_OFFS_MSGIDBUF_USED, \
-                       UART_HW_IFACE_OFFS_MSGIDBUF_RDPOS, \
-                       UART_HW_IFACE_OFFS_MSGIDBUF_WRPOS, \
-                       UART_HW_IFACE_OFFS_MSGIDBUF_DATA
-  ldi r16, 0xff
-  std Y+UART_HW_IFACE_OFFS_READBUFFERNUM, r16
-  std Y+UART_HW_IFACE_OFFS_WRITEBUFFERNUM, r16
+                       UART_HW_IFACE_OFFS_READBUF_USED, \
+                       UART_HW_IFACE_OFFS_READBUF_RDPOS, \
+                       UART_HW_IFACE_OFFS_READBUF_WRPOS, \
+                       UART_HW_IFACE_OFFS_READBUF_DATA
+
+  m_ringbuffer_y_reset UART_HW_IFACE_WRITEBUF_SIZE, \
+                       UART_HW_IFACE_OFFS_WRITEBUF_USED, \
+                       UART_HW_IFACE_OFFS_WRITEBUF_RDPOS, \
+                       UART_HW_IFACE_OFFS_WRITEBUF_WRPOS, \
+                       UART_HW_IFACE_OFFS_WRITEBUF_DATA
   ret
 ; @end
 
 
 
 ; ---------------------------------------------------------------------------
-; @routine UART_HW_InterfaceAddReadByte
+; @routine UART_HW_InterfaceWriteToReadBuffer @global
 ;
 ; @return CFLAG on success, cleared on error
 ; @param r16 byte to write
 ; @param Y pointer to start of interface data
 ; @clobbers R17, R18, X
 
-UART_HW_InterfaceAddReadByte:
+UART_HW_InterfaceWriteToReadBuffer:
   push yl
     push yh
-      adiw yh:yl, UART_HW_IFACE_OFFS_RINGBUF_MAX
+      adiw yh:yl, UART_HW_IFACE_OFFS_READBUF
       rcall RingBufferY_WriteByte                  ; R17, R18, X
     pop yh
   pop yl
@@ -95,17 +93,17 @@ UART_HW_InterfaceAddReadByte:
 
 
 ; ---------------------------------------------------------------------------
-; @routine UART_HW_InterfaceGetNextReadByte
+; @routine UART_HW_InterfaceReadFromReadBuffer @global
 ;
 ; @return CFLAG on success, cleared on error
 ; @return R16 byte read
 ; @param Y pointer to start of interface data
 ; @clobbers R17, R18, X
 
-UART_HW_InterfaceGetNextReadByte:
+UART_HW_InterfaceReadFromReadBuffer:
   push yl
     push yh
-      adiw yh:yl, UART_HW_IFACE_OFFS_RINGBUF_MAX
+      adiw yh:yl, UART_HW_IFACE_OFFS_READBUF
       rcall RingBufferY_ReadByte                  ; R17, R18, X
     pop yh
   pop yl
@@ -114,3 +112,46 @@ UART_HW_InterfaceGetNextReadByte:
 
 
 
+; ---------------------------------------------------------------------------
+; @routine UART_HW_InterfaceWriteToWriteBuffer @global
+;
+; @return CFLAG on success, cleared on error
+; @param r16 byte to write
+; @param Y pointer to start of interface data
+; @clobbers R17, R18, X
+
+UART_HW_InterfaceWriteToWriteBuffer:
+  push yl
+    push yh
+      adiw yh:yl, UART_HW_IFACE_OFFS_WRITEBUF
+      rcall RingBufferY_WriteByte                  ; R17, R18, X
+    pop yh
+  pop yl
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine UART_HW_InterfaceReadFromWriteBuffer @global
+;
+; @return CFLAG on success, cleared on error
+; @return R16 byte read
+; @param Y pointer to start of interface data
+; @clobbers R17, R18, X
+
+UART_HW_InterfaceReadFromWriteBuffer:
+  push yl
+    push yh
+      adiw yh:yl, UART_HW_IFACE_OFFS_WRITEBUF
+      rcall RingBufferY_ReadByte                  ; R17, R18, X
+    pop yh
+  pop yl
+  ret
+; @end
+
+
+
+
+
+
diff --git a/avr/modules/uart_hw/lowlevel_uart1.asm b/avr/modules/uart_hw/lowlevel_uart1.asm
new file mode 100644
index 0000000..b4dc76b
--- /dev/null
+++ b/avr/modules/uart_hw/lowlevel_uart1.asm
@@ -0,0 +1,135 @@
+; ***************************************************************************
+; copyright   : (C) 2025 by Martin Preuss
+; email       : martin@libchipcard.de
+;
+; ***************************************************************************
+; * This file is part of the project "AqHome".                              *
+; * Please see toplevel file COPYING of that project for license details.   *
+; ***************************************************************************
+
+
+.dseg
+;  uartHw_TtyOn1Interface: .byte UART_HW_IFACE_SIZE
+
+
+
+.cseg
+
+
+
+; ---------------------------------------------------------------------------
+; @routine UART_HW_Uart1_StartRx @global
+;
+; @clobbers none
+
+UART_HW_Uart1_StartRx:
+  lds r16, UCSR1B
+  sbr r16, (1<<RXCIE1)                      ; enable RX complete interrupt
+  sbr r16, (1<<RXEN1)                       ; enable receive
+  sts UCSR1B, r16
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine UART_HW_Uart1_StopRx @global
+;
+; @clobbers none
+
+UART_HW_Uart1_StopRx:
+  lds r16, UCSR1B
+  cbr r16, (1<<RXCIE1)                      ; disable RX complete interrupt
+  cbr r16, (1<<RXEN1)                       ; disable receive
+  sts UCSR1B, r16
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine UART_HW_Uart1_StartTx @global
+;
+; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
+; @clobbers none
+
+UART_HW_Uart1_StartTx:
+  lds r16, UCSR1B
+  sbr r16, (1<<UDRIE1)                      ; enable TX data register empty interrupt
+  sbr r16, (1<<TXEN1)                       ; enable transceive
+  sts UCSR1B, r16
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine UART_HW_Uart1_StopTx @global
+;
+; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
+; @clobbers none
+
+UART_HW_Uart1_StopTx:
+  lds r16, UCSR1B
+  cbr r16, (1<<UDRIE1)                      ; disable TX data register empty interrupt
+  cbr r16, (1<<TXEN1)                       ; disable transceive
+  sts UCSR1B, r16
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine UART_HW_Uart1_RxCharIsr @global
+;
+; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
+; @clobbers R16 (R17, R18, X)
+
+UART_HW_Uart1_RxCharIsr:
+  in r16, UCSR1A                              ; check for errors
+  andi r16, (1<<FE1) | (1<<DOR1) | (1<<UPE1)
+  breq UART_HW_Uart1_RxCharIsr_recv
+  ldd r16, Y+UART_HW_IFACE_OFFS_STATUS
+  ori r16, UART_HW_STATUS_HWERR
+  std Y+UART_HW_IFACE_OFFS_STATUS, r16
+  rjmp UART_HW_Uart1_RxCharIsr_end
+UART_HW_Uart1_RxCharIsr_recv:
+  lds r16, UCSR1A
+  sbrs r16, RXC1
+    rjmp UART_HW_Uart1_RxCharIsr_end          ; no data
+  lds r16, UDR1
+  rcall UART_HW_InterfaceWriteToReadBuffer    ; (R17, R18, X)
+  brcs UART_HW_Uart1_RxCharIsr_end
+  ldd r16, Y+UART_HW_IFACE_OFFS_STATUS        ; set overrun error
+  ori r16, UART_HW_STATUS_OVERRUN
+  std Y+UART_HW_IFACE_OFFS_STATUS, r16
+UART_HW_Uart1_RxCharIsr_end:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine UART_HW_Uart1_TxCharIsr @global
+;
+; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
+; @clobbers R16, (R17, R18, X)
+
+UART_HW_Uart1_TxCharIsr:
+  lds r16, UCSR1A
+  sbrs r16,UDRE1
+    rjmp UART_HW_Uart1_TxCharIsr_end           ; not ready
+  rcall UART_HW_InterfaceReadFromWriteBuffer   ; (R17, R18, X)
+  brcs UART_HW_Uart1_TxCharIsr_send            ; no data in buffer
+  ldd r16, Y+UART_HW_IFACE_OFFS_STATUS         ; set underrun error
+  ori r16, UART_HW_STATUS_UNDERRUN
+  std Y+UART_HW_IFACE_OFFS_STATUS, r16
+  rjmp UART_HW_Uart1_TxCharIsr_end
+UART_HW_Uart1_TxCharIsr_send:
+  sts UDR1, r16
+UART_HW_Uart1_TxCharIsr_end:
+  ret
+; @end
+
+
+
diff --git a/avr/modules/uart_hw/raw_uart1.asm b/avr/modules/uart_hw/raw_uart1.asm
new file mode 100644
index 0000000..32ee68e
--- /dev/null
+++ b/avr/modules/uart_hw/raw_uart1.asm
@@ -0,0 +1,315 @@
+; ***************************************************************************
+; copyright   : (C) 2025 by Martin Preuss
+; email       : martin@libchipcard.de
+;
+; ***************************************************************************
+; * This file is part of the project "AqHome".                              *
+; * Please see toplevel file COPYING of that project for license details.   *
+; ***************************************************************************
+
+
+
+; ---------------------------------------------------------------------------
+; @routine UART_HW_Uart1_RawInit @global
+;
+; @clobbers R16, R17
+
+UART_HW_Uart1_RawInit:
+  ; set baudrate
+;.if clock == 8000000
+;  ldi r16, 25 ; (19.2Kb/s at 8MHz)
+;  ldi r17, 0
+;.endif
+
+;.if clock == 1000000
+  ldi r16, 3  ; (19.2Kb/s at 1MHz)
+  ldi r17, 0  
+;.endif
+
+  sts UBRR1H, r17
+  sts UBRR1L, r16
+
+  ; set character format (asynchronous USART, 8-bit, one stop bit, no parity)
+  ldi r16, (3<<UCSZ10)
+  sts UCSR1C, r16
+
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine UART_HW_Uart1_RawSendPacket
+; Send packet.
+;
+; @param X buffer to send
+; @return CFLAG: set if okay (packet sent), cleared on error
+; @clobbers r16, r17, X
+
+UART_HW_Uart1_RawSendPacket:
+  adiw xh:xl, 1
+  ld r17, X
+  sbiw xh:xl, 1
+  ldi r16, 3     ; add DEST, LEN, CRC bytes
+  add r17, r16
+  
+  lds r16, UCSR1B
+;  cbr r16, (1<<UDRIE1)  ; disable DRE interrupt
+  sbr r16, (1<<TXEN1)   ; enable transmit
+  sts UCSR1B, r16
+
+;;  clr r16               ; clear all pending interrupts
+;;  sts UCSR1A, r16
+
+;ldi r17, 20
+
+UART_HW_Uart1_RawSendPacket_loop:
+      lds r16, UCSR1A
+      sbrs r16, UDRE1
+    rjmp UART_HW_Uart1_RawSendPacket_loop
+    sbr r16, (1<<TXC1)
+    sts UCSR1A, r16
+    ld r16, X+
+    sts UDR1, r16
+    dec r17
+  brne UART_HW_Uart1_RawSendPacket_loop
+  ; disable transmit
+;  lds r16, UCSR1B
+;  cbr r16, (1<<TXEN1)   ; disable transmit
+;  sts UCSR1B, r16
+  sec
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine UART_HW_Uart1_EnableRawRecv @global
+;
+; Enable receiving messages in raw mode.
+;
+; @clobbers: r16
+
+UART_HW_Uart1_EnableRawRecv:
+  lds r16, UCSR1B
+  cbr r16, (1<<RXCIE1)                      ; disable RX complete interrupt
+  sbr r16, (1<<RXEN1)                       ; enable receive
+  sts UCSR1B, r16
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine UART_HW_Uart1_DisableRawRecv @global
+;
+; Disable receiving messages in raw mode.
+;
+; @clobbers: r16
+
+UART_HW_Uart1_DisableRawRecv:
+  lds r16, UCSR1B
+  cbr r16, (1<<RXCIE1)                      ; disable RX complete interrupt
+  cbr r16, (1<<RXEN1)                       ; disable receive
+  sts UCSR1B, r16
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine UART_HW_Uart1_RawRecvPacket
+; Receive packet.
+;
+; @param  R16   COM address to listen to
+; @param  R17   maximum value for accepted msg data (i.e. buffersize minus 3)
+; @param  R18   max number of secs to wait for incoming message
+; @param  X     buffer to receive to
+; @return CFLAG set if okay (packet received), cleared on error
+; @return R16   error code if CFLAG is cleared (COM2_ERROR_NOTFORME, COM2_ERROR_IOERROR, COM2_ERROR_DATAERROR)
+; @clobbers: r16, r17, r18, r19, r22, X
+
+UART_HW_Uart1_RawRecvPacket:
+  ; wait for data
+  push r16
+    mov r16, r18
+    rcall uartHwUart1RawWaitForByte            ; (r16, r18, r22)
+  pop r16
+  brcc UART_HW_Uart1_RawRecvPacket_error
+
+  ; data available, start reading
+  mov r19, r17                                 ; max msg payload size
+  push r16
+    ; read destination address
+    rcall uartHwUart1RawRecvByte               ; (R16, R18, R22)
+  pop r17                                      ; pop acceptable COM address from R16 to R17
+  brcc UART_HW_Uart1_RawRecvPacket_error
+#ifndef COM_ACCEPT_ALL_DEST                    ; accept every destination address
+  ; compare destination address (accept "FF" and own address)
+  cp r16, r17
+  breq UART_HW_Uart1_RawRecvPacket_acceptAddr
+  cpi r16, 0xff
+  breq UART_HW_Uart1_RawRecvPacket_acceptAddr
+  ldi r16, COM2_ERROR_NOTFORME
+  rjmp UART_HW_Uart1_RawRecvPacket_error
+#endif
+UART_HW_Uart1_RawRecvPacket_acceptAddr:
+  st X+, r16
+  ; read msg length
+  rcall uartHwUart1RawRecvByte                 ; (R16, R18, R22)
+  brcc UART_HW_Uart1_RawRecvPacket_error
+  cp r16, r19                                  ; (COM2_BUFFER_SIZE-3)
+  brcc UART_HW_Uart1_RawRecvPacket_error
+  tst r16
+  breq UART_HW_Uart1_RawRecvPacket_error
+  st X+, r16
+  inc r16
+  mov r17, r16
+  ; read message content
+UART_HW_Uart1_RawRecvPacket_loop:
+    rcall uartHwUart1RawRecvByte               ; (R16, R18, R22)
+    brcc UART_HW_Uart1_RawRecvPacket_error
+    st X+, r16
+    dec r17
+  brne UART_HW_Uart1_RawRecvPacket_loop
+  sec
+  rjmp UART_HW_Uart1_RawRecvPacket_end
+UART_HW_Uart1_RawRecvPacket_error:
+  clc
+UART_HW_Uart1_RawRecvPacket_end:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine uartHwUart1RawRecvByte
+; Receive one byte.
+;
+; @return CFLAG set if okay, cleared on error
+; @return R16 error code if CFLAG is cleared
+; @clobbers: r16 (r18, r22)
+
+uartHwUart1RawRecvByte:
+  rcall uartHwUart1RawWaitForByte1ms          ; (r18, r22)
+  brcc uartHwUart1RawRecvByte_error
+  lds r16, UCSR1A                              ; check for errors
+  andi r16, (1<<FE1) | (1<<DOR1) | (1<<UPE1)
+  brne uartHwUart1RawRecvByte_error
+  lds r16, UDR1
+  sec
+  ret
+uartHwUart1RawRecvByte_error:
+  ldi r16, COM2_ERROR_IOERROR
+  clc
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine uartHwUart1RawWaitForByte
+; wait for up to given number of secs for incoming byte
+;
+; @return CFLAG set if okay, cleared on error
+; @param  r16   number of secs to wait
+; @clobbers: r16, r18, r22
+
+uartHwUart1RawWaitForByte:
+uartHwUart1RawWaitForByte_loop:
+    rcall uartHwUart1RawWaitForByte1s         ; (r18, r22)
+    brcs uartHwUart1RawWaitForByte_haveByte
+    dec r16
+  brne uartHwUart1RawWaitForByte_loop
+  clc
+uartHwUart1RawWaitForByte_haveByte:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine uartHwUart1RawWaitForByte1s
+; wait for up to 1s for incoming byte
+;
+; @return CFLAG set if okay, cleared on error
+; @clobbers: r18, r22
+
+uartHwUart1RawWaitForByte1s:
+  ldi r18, 10
+uartHwUart1RawWaitForByte1s_loop:
+    push r18
+      rcall uartHwUart1RawWaitForByte100ms     ; (r18, r22)
+    pop r18
+    brcs uartHwUart1RawWaitForByte1s_haveByte
+;    sbi LED_SIMPLE_PORTIN, LED_SIMPLE_PINNUM ; toggle
+    dec r18
+  brne uartHwUart1RawWaitForByte1s_loop
+  clc
+uartHwUart1RawWaitForByte1s_haveByte:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine uartHwUart1RawWaitForByte100ms
+; wait for up to 100ms for incoming byte
+;
+; @return CFLAG set if okay, cleared on error
+; @clobbers: r18, r22
+
+uartHwUart1RawWaitForByte100ms:
+  ldi r18, 100
+uartHwUart1RawWaitForByte100ms_loop:
+    push r18
+      rcall uartHwUart1RawWaitForByte1ms
+    pop r18
+    brcs uartHwUart1RawWaitForByte100ms_haveByte
+    dec r18
+  brne uartHwUart1RawWaitForByte100ms_loop
+  clc
+uartHwUart1RawWaitForByte100ms_haveByte:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine uartHwUart1RawWaitForByte1ms
+; wait for up to 1ms for incoming byte
+;
+; @return CFLAG set if okay, cleared on error
+; @clobbers: r18, r22
+
+uartHwUart1RawWaitForByte1ms:
+  ldi r18, 100
+uartHwUart1RawWaitForByte1ms_loop:
+    lds r22, UCSR1A
+    sbrc r22, RXC1
+      rjmp uartHwUart1RawWaitForByte1ms_haveByte
+    rcall Utils_WaitFor10MicroSecs                ; wait for 10us (R22)
+    dec r18
+  brne uartHwUart1RawWaitForByte1ms_loop
+  clc
+  ret
+uartHwUart1RawWaitForByte1ms_haveByte:
+  sec
+  ret
+; @end
+
+
+
+.equ COMIO_RawSendPacket  = UART_HW_Uart1_RawSendPacket
+.equ COMIO_RawRecvPacket  = UART_HW_Uart1_RawRecvPacket
+.equ COMIO_EnableRawRecv  = UART_HW_Uart1_EnableRawRecv
+.equ COMIO_DisableRawRecv = UART_HW_Uart1_DisableRawRecv
+
+
+
+
+
+
+
+
+