avr: more work on hardware-based UART module.

2025-01-19 15:46:21 +01:00
parent c390b1059c
commit ecb2d85ea2
5 changed files with 534 additions and 121 deletions
--- a/avr/modules/uart_hw/lowlevel_uart1.asm
+++ b/avr/modules/uart_hw/lowlevel_uart1.asm
@@ -0,0 +1,135 @@
+; ***************************************************************************
+; copyright   : (C) 2025 by Martin Preuss
+; email       : martin@libchipcard.de
+;
+; ***************************************************************************
+; * This file is part of the project "AqHome".                              *
+; * Please see toplevel file COPYING of that project for license details.   *
+; ***************************************************************************
+
+
+.dseg
+;  uartHw_TtyOn1Interface: .byte UART_HW_IFACE_SIZE
+
+
+
+.cseg
+
+
+
+; ---------------------------------------------------------------------------
+; @routine UART_HW_Uart1_StartRx @global
+;
+; @clobbers none
+
+UART_HW_Uart1_StartRx:
+  lds r16, UCSR1B
+  sbr r16, (1<<RXCIE1)                      ; enable RX complete interrupt
+  sbr r16, (1<<RXEN1)                       ; enable receive
+  sts UCSR1B, r16
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine UART_HW_Uart1_StopRx @global
+;
+; @clobbers none
+
+UART_HW_Uart1_StopRx:
+  lds r16, UCSR1B
+  cbr r16, (1<<RXCIE1)                      ; disable RX complete interrupt
+  cbr r16, (1<<RXEN1)                       ; disable receive
+  sts UCSR1B, r16
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine UART_HW_Uart1_StartTx @global
+;
+; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
+; @clobbers none
+
+UART_HW_Uart1_StartTx:
+  lds r16, UCSR1B
+  sbr r16, (1<<UDRIE1)                      ; enable TX data register empty interrupt
+  sbr r16, (1<<TXEN1)                       ; enable transceive
+  sts UCSR1B, r16
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine UART_HW_Uart1_StopTx @global
+;
+; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
+; @clobbers none
+
+UART_HW_Uart1_StopTx:
+  lds r16, UCSR1B
+  cbr r16, (1<<UDRIE1)                      ; disable TX data register empty interrupt
+  cbr r16, (1<<TXEN1)                       ; disable transceive
+  sts UCSR1B, r16
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine UART_HW_Uart1_RxCharIsr @global
+;
+; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
+; @clobbers R16 (R17, R18, X)
+
+UART_HW_Uart1_RxCharIsr:
+  in r16, UCSR1A                              ; check for errors
+  andi r16, (1<<FE1) | (1<<DOR1) | (1<<UPE1)
+  breq UART_HW_Uart1_RxCharIsr_recv
+  ldd r16, Y+UART_HW_IFACE_OFFS_STATUS
+  ori r16, UART_HW_STATUS_HWERR
+  std Y+UART_HW_IFACE_OFFS_STATUS, r16
+  rjmp UART_HW_Uart1_RxCharIsr_end
+UART_HW_Uart1_RxCharIsr_recv:
+  lds r16, UCSR1A
+  sbrs r16, RXC1
+    rjmp UART_HW_Uart1_RxCharIsr_end          ; no data
+  lds r16, UDR1
+  rcall UART_HW_InterfaceWriteToReadBuffer    ; (R17, R18, X)
+  brcs UART_HW_Uart1_RxCharIsr_end
+  ldd r16, Y+UART_HW_IFACE_OFFS_STATUS        ; set overrun error
+  ori r16, UART_HW_STATUS_OVERRUN
+  std Y+UART_HW_IFACE_OFFS_STATUS, r16
+UART_HW_Uart1_RxCharIsr_end:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine UART_HW_Uart1_TxCharIsr @global
+;
+; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
+; @clobbers R16, (R17, R18, X)
+
+UART_HW_Uart1_TxCharIsr:
+  lds r16, UCSR1A
+  sbrs r16,UDRE1
+    rjmp UART_HW_Uart1_TxCharIsr_end           ; not ready
+  rcall UART_HW_InterfaceReadFromWriteBuffer   ; (R17, R18, X)
+  brcs UART_HW_Uart1_TxCharIsr_send            ; no data in buffer
+  ldd r16, Y+UART_HW_IFACE_OFFS_STATUS         ; set underrun error
+  ori r16, UART_HW_STATUS_UNDERRUN
+  std Y+UART_HW_IFACE_OFFS_STATUS, r16
+  rjmp UART_HW_Uart1_TxCharIsr_end
+UART_HW_Uart1_TxCharIsr_send:
+  sts UDR1, r16
+UART_HW_Uart1_TxCharIsr_end:
+  ret
+; @end
+
+
+