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add additional waitstate after acquiting bus.

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Martin Preuss
2025-05-04 03:35:59 +02:00
parent e6ea506a74
commit b3f19b0432
1 changed files with 1 additions and 0 deletions
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avr/modules/uart_bitbang2/lowlevel.asm
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@@ -291,6 +291,7 @@ uartBitbang_SendPacket:
rcall uartBitbang_AcquireBus
brcc uartBitbang_SendPacket_lineBusyError
rcall uartBitbang_WaitForOneBitLength ; wait for one bit duration (R22)
rcall uartBitbang_WaitForOneBitLength ; wait for one bit duration (R22)
rcall uartBitbang_WaitForOneBitLength ; wait for one bit duration (R22)