avr: more work on uart_hw module.

avr/modules/uart_hw/lowlevel_uart1.asm

@@ -13,6 +13,38 @@
 
 
 
+; ---------------------------------------------------------------------------
+; @routine UART_HW_Uart1_Init @global
+;
+; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
+; @clobbers R16, R17, X
+
+UART_HW_Uart1_Init:
+  rcall UART_HW_InterfaceInit
+
+  ; set baudrate
+.if clock == 8000000
+  ldi r16, 25 ; (19.2Kb/s at 8MHz)
+  ldi r17, 0
+.endif
+
+.if clock == 1000000
+  ldi r16, 2  ; (19.2Kb/s at 1MHz)
+  ldi r17, 0  
+.endif
+
+  sts UBRR1H, r17
+  sts UBRR1L, r16
+
+  ; set character format 
+  ldi r16, (1<<USBS1)|(3<<UCSZ10)
+  sts UCSR1C, r16
+
+  ret
+; @end
+
+
+
 ; ---------------------------------------------------------------------------
 ; @routine UART_HW_Uart1_StartRx @global
 ;
@@ -112,7 +144,13 @@ UART_HW_Uart1_TxCharIsr:
   sbrs r16,UDRE1
     rjmp UART_HW_Uart1_TxCharIsr_end           ; not ready
   rcall UART_HW_InterfaceReadFromWriteBuffer   ; (R17, R18, X)
-  brcs UART_HW_Uart1_TxCharIsr_send            ; no data in buffer
+  brcs UART_HW_Uart1_TxCharIsr_send            ; got a byte, go send
+
+  ; disable further DRE1 interrupts
+  lds r16, UCSR1B
+  cbr r16, (1<<UDRIE1)                         ; disable TX data register empty interrupt
+  sts UCSR1B, r16
+  ; set underrun status (TODO: maybe change this later)
   ldd r16, Y+UART_HW_IFACE_OFFS_STATUS         ; set underrun error
   ori r16, UART_HW_STATUS_UNDERRUN
   std Y+UART_HW_IFACE_OFFS_STATUS, r16