avr: fixed 1-wire protocol for multiple speeds.
fixed delays won't work with 8MHz when calibrated for 1MHz... use wait macro instead.
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@@ -136,7 +136,7 @@ Ds18b20_OnTimer_done:
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Ds18b20_SendCommand:
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mov r18, r16
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rcall OwiMaster_Reset ; (r22)
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rcall OwiMaster_Reset ; (r21, r22)
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tst r16 ; presence detected?
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breq Ds18b20_SendCommand_error ; nope, jump
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@@ -166,7 +166,7 @@ Ds18b20_SendCommand_error:
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; @clobbers r16, r18, r19, r23, X (r17, r20, r21, r22)
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Ds18b20_ReadRom:
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rcall OwiMaster_Reset ; (r22)
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rcall OwiMaster_Reset ; (r21, r22)
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tst r16 ; presence detected?
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breq Ds18b20_ReadRom_error ; nope, jump
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@@ -36,7 +36,7 @@ OwiMaster_Init:
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; Cave: Needs interrupts to be disabled!
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;
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; @return r16 0xff if slave presence signal received, 0x00 otherwise
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; @clobbers r22
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; @clobbers r21, r22
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OwiMaster_Reset:
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; send RESET pulse (min. 480usec)
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@@ -47,15 +47,30 @@ OwiMaster_Reset:
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rcall Utils_WaitFor100MicroSecs
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rcall Utils_WaitFor100MicroSecs
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rcall Utils_WaitFor100MicroSecs
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cbi OWI_DDR, OWI_PINNUM ; set to input
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cbi OWI_DDR, OWI_PINNUM ; set to input
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; after 16-60 uS slave pulls line low for 60-240 uS
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; if present slave pulls line low for 60 usecs (we check after 30 usecs)
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Utils_WaitNanoSecs 30000, 0, r22
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clr r16
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sbic OWI_PORTIN, OWI_PINNUM
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rjmp OwiMaster_Reset_done
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dec r16
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rcall owiWaitForDataState1ms ; wait for line pulled up
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ldi r21, 100
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OwiMaster_Reset_LoopWaitForLow: ; wait for line low
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Utils_WaitNanoSecs 5000, 0, r22
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sbis OWI_PORTIN, OWI_PINNUM
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rjmp OwiMaster_Reset_isLow
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dec r21
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brne OwiMaster_Reset_LoopWaitForLow
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clr r16 ; not present
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rjmp OwiMaster_Reset_done
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OwiMaster_Reset_isLow:
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ldi r21, 160
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OwiMaster_Reset_LoopWaitForHigh: ; wait for line high
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Utils_WaitNanoSecs 5000, 0, r22
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sbic OWI_PORTIN, OWI_PINNUM
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rjmp OwiMaster_Reset_isHigh
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dec r21
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brne OwiMaster_Reset_LoopWaitForHigh
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clr r16 ; not present
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rjmp OwiMaster_Reset_done
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OwiMaster_Reset_isHigh:
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ldi r16, 0xff ; presence detected
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OwiMaster_Reset_done:
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ret
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; @end
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@@ -75,16 +90,16 @@ OwiMaster_SendByte:
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cbi OWI_PORTOUT, OWI_PINNUM ; set value to zero
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ldi r21, 8
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OwiMaster_SendByte_loop:
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sbi OWI_DDR, OWI_PINNUM ; set to output
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lsr r16 ; bit to send -> CARRY
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brcs OwiMaster_SendByte_setHigh
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sbi OWI_DDR, OWI_PINNUM ; set to output (pull line low)
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lsr r16 ; +1 bit to send -> CARRY
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brcs OwiMaster_SendByte_setHigh ; +1 / +2
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OwiMaster_SendByte_setLow:
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Utils_WaitNanoSecs 60000, 0, r22 ; set to low for 60 usecs ("0")
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cbi OWI_DDR, OWI_PINNUM ; set to output
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Utils_WaitNanoSecs 5000, 0, r22 ; set to low for 5 usecs ("1")
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Utils_WaitNanoSecs 60000, 0, r22 ; low for 60 usecs
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cbi OWI_DDR, OWI_PINNUM ; set to input (pulls line high)
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Utils_WaitNanoSecs 5000, 0, r22 ; wait for 5 usecs
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rjmp OwiMaster_SendByte_loopEnd
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OwiMaster_SendByte_setHigh:
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Utils_WaitNanoSecs 5000, 0, r22 ; set to low for 5 usecs ("1")
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Utils_WaitNanoSecs 5000, 0, r22 ; keep low for 5 usecs
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cbi OWI_DDR, OWI_PINNUM ; set to output
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Utils_WaitNanoSecs 60000, 0, r22 ; keep high for remainder of write slot
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OwiMaster_SendByte_loopEnd:
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