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avr: consolidated uart_hw module

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This commit is contained in:
Martin Preuss
2025-03-27 00:20:58 +01:00
parent 3555b49219
commit 89542e06c9
9 changed files with 290 additions and 507 deletions
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6
avr/devices/n00/n00_boot.asm
View File

@@ -104,10 +104,6 @@ main:
; ***************************************************************************
; includes
.include "modules/uart_bitbang/bytelevel.asm"
.include "modules/uart_bitbang/packetlevel.asm"
.include "modules/com2/crc.asm"
.include "common/crc8.asm"
.include "common/utils_wait_fixed.asm"
.include "common/utils_copy_from_flash.asm"
.include "common/utils_copy_sdram.asm"
@@ -121,6 +117,8 @@ main:
.include "modules/flash/flashprocess.asm"
.include "modules/flash/wait.asm"
.include "modules/bootloader/main.asm"
.include "modules/network/msg/defs.asm"
.include "modules/network/msg/crc.asm"

1
avr/devices/t03/defs.asm
View File

@@ -21,6 +21,7 @@
; [MOSI,PRG] SDA (I2C) PA6 7 8 PA5 TXD1 (UART1) [MISO, PRG]
; -------
;
; when using ATTN1: LED=PA3, ATTN1=PB2 !!
; ***************************************************************************

2
avr/devices/t03/main.asm
View File

@@ -312,8 +312,6 @@ initModules:
.include "modules/uart_hw/defs.asm"
.include "modules/uart_hw/lowlevel.asm"
.include "modules/uart_hw/m_lowlevel_uart.asm"
.include "modules/uart_hw/lowlevel_uart0.asm"
.include "modules/uart_hw/lowlevel_uart1.asm"
.include "modules/uart_hw/ttyonuart1.asm"
.include "modules/uart_hw/comonuart0.asm"

7
avr/modules/flash/io_uart1.asm
View File

@@ -46,6 +46,13 @@ ioRawInit:
; cbr r16, (1<<UDRIE1) ; disable DRE interrupt
ori r16, (1<<RXEN1) | (1<<TXEN1) ; enable transmit and receive
sts UCSR1B, r16
.ifdef COM_ATTN_PUE
lds r16, COM_ATTN_PUE
cbr r16, COM_ATTN_PIN ; disable pullup on ATTN
sts COM_ATTN_PUE, r16
.endif
ret
;@end

2
avr/modules/uart_hw/0BUILD
View File

@@ -6,8 +6,6 @@
comonuart0.asm
defs.asm
lowlevel.asm
lowlevel_uart0.asm
lowlevel_uart1.asm
m_lowlevel_uart.asm
ttyonuart1.asm
</extradist>

184
avr/modules/uart_hw/comonuart0.asm
View File

@@ -30,10 +30,10 @@ comOnUart0_iface: .byte UART_HW_IFACE_SIZE
ComOnUart0_Init:
ldi yl, LOW(comOnUart0_iface)
ldi yh, HIGH(comOnUart0_iface)
rcall UART_HW_Uart0_SetAttnInput ; (none)
rcall comOnUart0SetAttnInput ; (none)
rcall UART_HW_Interface_Init ; (R16, R17, X)
rcall UART_HW_Uart0_Init ; (R16, R17, X)
rcall comOnUart0Init ; (R16, R17, X)
ldi r16, COMONUART0_IFACENUM
std Y+NET_IFACE_OFFS_IFACENUM, r16
@@ -92,7 +92,7 @@ ComOnUart0_RxCharIsr:
push yh
ldi yl, LOW(comOnUart0_iface)
ldi yh, HIGH(comOnUart0_iface)
rcall UART_HW_Uart0_RxCharIsr ; (R16, R17, R18, R24, R25, X)
rcall comOnUart0RxCharIsr ; (R16, R17, R18, R24, R25, X)
pop yh
pop yl
pop xh
@@ -125,7 +125,7 @@ ComOnUart0_TxUdreIsr:
push yh
ldi yl, LOW(comOnUart0_iface)
ldi yh, HIGH(comOnUart0_iface)
rcall UART_HW_Uart0_TxUdreIsr ; (R16, R17, X)
rcall comOnUart0TxUdreIsr ; (R16, R17, X)
pop yh
pop yl
pop xh
@@ -156,7 +156,7 @@ ComOnUart0_TxCharIsr:
push yh
ldi yl, LOW(comOnUart0_iface)
ldi yh, HIGH(comOnUart0_iface)
rcall UART_HW_Uart0_TxCharIsr ; (R16, R17, R18, X)
rcall comOnUart0TxCharIsr ; (R16, R17, R18, X)
pop yh
pop yl
pop xh
@@ -249,34 +249,34 @@ comOnUart0EnterReading_okay:
std Y+UART_HW_IFACE_OFFS_READMODE, r16
clr r16
std Y+NET_IFACE_OFFS_READTIMER, r16
rcall UART_HW_Uart0_StartRx ; R16
rcall comOnUart0StartRx ; R16
ret
; @end
; ---------------------------------------------------------------------------
; @routine ComOnUart0_SendBuffer @global
; @routine comOnUart0SendBuffer @global
;
; @param Y pointer to interface data in SRAM
; @clobbers R16, R17
ComOnUart0_SendBuffer:
comOnUart0SendBuffer:
push r15
in r15, SREG
cli
ldd r17, Y+UART_HW_IFACE_OFFS_WRITEMODE
cpi r17, UART_HW_WRITEMODE_IDLE
breq ComOnUart0_SendBuffer_setBuffer
breq comOnUart0SendBuffer_setBuffer
out SREG, r15
pop r15
clc
ret
ComOnUart0_SendBuffer_setBuffer:
comOnUart0SendBuffer_setBuffer:
rcall UART_HW_Interface_SetWriteBuffer ; (R17)
ldi r17, UART_HW_WRITEMODE_WRITING
std Y+UART_HW_IFACE_OFFS_WRITEMODE, r17
rcall UART_HW_Uart0_StartTx ; (R16)
rcall comOnUart0StartTx ; (R16)
pop r15
out SREG, r15
sec
@@ -363,12 +363,12 @@ comOnUart0RunWriteIdle:
sbis COM_ATTN_INPUT, COM_ATTN_PIN ; ATTN low?
rjmp comOnUart0RunWriteIdle_end ; yes, line busy, jmp
rcall UART_HW_Uart0_SetAttnLow ; reserve bus as soon as possible
rcall comOnUart0SetAttnLow ; reserve bus as soon as possible
Utils_WaitNanoSecs COM_BIT_LENGTH, 0, r22 ; wait for one bit duration
Utils_WaitNanoSecs COM_BIT_LENGTH, 0, r22 ; wait for one bit duration
rcall NET_Buffer_Locate ; (R17)
rcall ComOnUart0_SendBuffer ; (R16, R17)
rcall comOnUart0SendBuffer ; (R16, R17)
rcall NET_Interface_GetNextOutgoingMsgNum ; take msg from queue (R17, R18, X)
comOnUart0RunWriteIdle_end:
ret
@@ -411,9 +411,9 @@ comOnUart0RunWriteBufferEmpty:
std Y+UART_HW_IFACE_OFFS_WRITEBUFNUM, r17
rcall NET_Buffer_ReleaseByNum ; (R16, X)
comOnUart0RunWriteBufferEmpty_setIdle:
rcall UART_HW_Uart0_StopTx ; disable transceiver and interrupts (R16)
rcall comOnUart0StopTx ; disable transceiver and interrupts (R16)
rcall UART_HW_Uart0_SetAttnInput ; set ATTN as input
rcall comOnUart0SetAttnInput ; set ATTN as input
ldi r16, UART_HW_WRITEMODE_IDLE
std Y+UART_HW_IFACE_OFFS_WRITEMODE, r16
@@ -466,7 +466,7 @@ comOnUart0RunReading:
ldd r16, Y+NET_IFACE_OFFS_READTIMER
cpi r16, COMONUART0_READ_TIMEOUT
brcs comOnUart0RunReading_end
rcall UART_HW_Uart0_StopRx ; (R16)
rcall comOnUart0StopRx ; (R16)
ldd r16, Y+UART_HW_IFACE_OFFS_READBUFNUM
ldi r17, 0xff
std Y+UART_HW_IFACE_OFFS_READBUFNUM, r17
@@ -517,14 +517,150 @@ comOnUart0RunMsgReceived:
; DEBUG begin
ldi r16, NET_IFACE_OFFS_HANDLED_LOW
rcall NET_Interface_IncCounter16 ; (R24, R25)
; DEBUG end
; ---------------------------------------------------------------------------
; @routine comOnUart0Init @global
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
; @clobbers R16, R17, X
comOnUart0Init:
.ifdef COM_ATTN_PUE
lds r16, COM_ATTN_PUE
cbr r16, COM_ATTN_PIN ; disable pullup on ATTN
sts COM_ATTN_PUE, r16
.endif
rcall comOnUart0SetAttnInput
M_UART_HW_Uart_Init 0
ret
; @end
; ---------------------------------------------------------------------------
; @routine comOnUart0StartRx @global
;
; @clobbers R16
comOnUart0StartRx:
M_UART_HW_Uart_StartRx 0
ret
; @end
; ---------------------------------------------------------------------------
; @routine comOnUart0StopRx @global
;
; @clobbers R16
comOnUart0StopRx:
M_UART_HW_Uart_StopRx 0
ret
; @end
; ---------------------------------------------------------------------------
; @routine comOnUart0StartTx @global
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
; @clobbers R16
comOnUart0StartTx:
M_UART_HW_Uart_StartTx 0
ret
; @end
; ---------------------------------------------------------------------------
; @routine comOnUart0StopTx @global
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
; @clobbers R16
comOnUart0StopTx:
M_UART_HW_Uart_StopTx 0
ret
; @end
; ---------------------------------------------------------------------------
; @routine comOnUart0RxCharIsr @global
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
; @clobbers R16 (R17, R18, R24, R25, X)
comOnUart0RxCharIsr:
M_UART_HW_Uart_RxCharHalfDuplexIsr 0
ret
; @end
; ---------------------------------------------------------------------------
; @routine comOnUart0TxUdreIsr @global
;
; Handler for UDRE1 interrupt called when TX data register is empty.
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
; @clobbers R16, R17, X
comOnUart0TxUdreIsr:
M_UART_HW_Uart_TxUdreIsr 0
ret
; @end
; ---------------------------------------------------------------------------
; @routine comOnUart0TxCharIsr @global
;
; Handler for TXC1 interrupt called when a last byte has been completely sent and
; the data register is empty.
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
; @clobbers R16
comOnUart0TxCharIsr:
M_UART_HW_Uart_TxCharIsr 0
ret
; @end
; ---------------------------------------------------------------------------
; @routine comOnUart0SetAttnInput @global
;
; Set ATTN line as input (making it effectively HIGH due to pull-up resistor on
; the line)
;
; @clobbers none
comOnUart0SetAttnInput:
cbi COM_ATTN_DDR, COM_ATTN_PIN ; set ATTN as input
.ifdef COM_ATTN_PUE
; cbi COM_ATTN_PUE, COM_ATTN_PIN ; disable pullup on ATTN
.else
cbi COM_ATTN_OUTPUT, COM_ATTN_PIN ; disable pullup on ATTN
.endif
ret
; @end
; ---------------------------------------------------------------------------
; @routine comOnUart0SetAttnLow @global
;
; Set ATTN line low.
;
; @clobbers none
comOnUart0SetAttnLow:
sbi COM_ATTN_DDR, COM_ATTN_PIN ; set ATTN as output
cbi COM_ATTN_OUTPUT, COM_ATTN_PIN ; set ATTN low
ret
; @end
; DEBUG begin
ldi r16, NET_IFACE_OFFS_ERR_MISSED_LOW
rcall NET_Interface_IncCounter16 ; (R24, R25)
; DEBUG end

249
avr/modules/uart_hw/lowlevel_uart0.asm
View File

@@ -1,249 +0,0 @@
; ***************************************************************************
; copyright : (C) 2025 by Martin Preuss
; email : martin@libchipcard.de
;
; ***************************************************************************
; * This file is part of the project "AqHome". *
; * Please see toplevel file COPYING of that project for license details. *
; ***************************************************************************
.cseg
; ---------------------------------------------------------------------------
; @routine UART_HW_Uart0_Init @global
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
; @clobbers R16, R17, X
UART_HW_Uart0_Init:
M_UART_HW_Uart_Init 0
ret
; @end
; ---------------------------------------------------------------------------
; @routine UART_HW_Uart0_StartRx @global
;
; @clobbers R16
UART_HW_Uart0_StartRx:
M_UART_HW_Uart_StartRx 0
ret
; @end
; ---------------------------------------------------------------------------
; @routine UART_HW_Uart0_StopRx @global
;
; @clobbers R16
UART_HW_Uart0_StopRx:
M_UART_HW_Uart_StopRx 0
ret
; @end
; ---------------------------------------------------------------------------
; @routine UART_HW_Uart0_StartTx @global
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
; @clobbers R16
UART_HW_Uart0_StartTx:
M_UART_HW_Uart_StartTx 0
ret
; @end
; ---------------------------------------------------------------------------
; @routine UART_HW_Uart0_StopTx @global
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
; @clobbers R16
UART_HW_Uart0_StopTx:
M_UART_HW_Uart_StopTx 0
ret
; @end
; ---------------------------------------------------------------------------
; @routine UART_HW_Uart0_Flush
;
; Flush receiption buffer.
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
; @clobbers R16
UART_HW_Uart0_Flush:
M_UART_HW_Uart_Flush 0
ret
; @end
; ---------------------------------------------------------------------------
; @routine UART_HW_Uart0_RxCharIsr @global
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
; @clobbers R16 (R17, R18, R24, R25, X)
UART_HW_Uart0_RxCharIsr:
M_UART_HW_Uart_RxCharHalfDuplexIsr 0
ret
#if 0
; check for errors
lds r16, UCSR0A ; check for errors
andi r16, (1<<FE0) | (1<<DOR0) | (1<<UPE0)
brne UART_HW_Uart0_RxCharIsr_hwerr
; read char
lds r16, UCSR0A
sbrs r16, RXC0
rjmp UART_HW_Uart0_RxCharIsr_end ; no data
lds r16, UDR0 ; r16=received char
; check read mode
ldd r17, Y+UART_HW_IFACE_OFFS_READMODE
cpi r17, UART_HW_READMODE_READING
breq UART_HW_Uart0_RxCharIsr_storeChar
cpi r17, UART_HW_READMODE_SKIPPING
breq UART_HW_Uart0_RxCharIsr_skipChar
rjmp UART_HW_Uart0_RxCharIsr_overrun ; neither read nor skip mode
UART_HW_Uart0_RxCharIsr_skipChar:
clr r16
std Y+NET_IFACE_OFFS_READTIMER, r16 ; reset read timer
rjmp UART_HW_Uart0_RxCharIsr_end
UART_HW_Uart0_RxCharIsr_storeChar:
mov r18, r16 ; r18=received char
; check buffer
ldd r16, Y+UART_HW_IFACE_OFFS_READBUFNUM
cpi r16, 0xff
breq UART_HW_Uart0_RxCharIsr_overrun
; check for buffer overrun
ldd r17, Y+UART_HW_IFACE_OFFS_READBUFLEFT ; r17=bytes left
tst r17
breq UART_HW_Uart0_RxCharIsr_econtent ; msg too long
; actually store byte, increment/decrement counters and pos
ldd xl, Y+UART_HW_IFACE_OFFS_READBUFPOS_LOW
ldd xh, Y+UART_HW_IFACE_OFFS_READBUFPOS_HIGH
st X+, r18 ; r18=byte to store
clr r16
std Y+NET_IFACE_OFFS_READTIMER, r16 ; reset read timer
std Y+UART_HW_IFACE_OFFS_READBUFPOS_LOW, xl
std Y+UART_HW_IFACE_OFFS_READBUFPOS_HIGH, xh
ldd r18, Y+UART_HW_IFACE_OFFS_READBUFUSED ; r18=bytes in buffer
inc r18
std Y+UART_HW_IFACE_OFFS_READBUFUSED, r18
dec r17
std Y+UART_HW_IFACE_OFFS_READBUFLEFT, r17
breq UART_HW_Uart0_RxCharIsr_msgFinished
; check msg size
cpi r18, 2 ; bytes in buffer, exactly 2?
brne UART_HW_Uart0_RxCharIsr_end ; nope, done
sbiw xh:xl, 1 ; yes, determine message length (msgLen at previous pos)
ld r16, X+ ; read payload length byte
subi r16, -3 ; add 3 (dest addr, length, crc byte)
cpi r16, (NET_BUFFERS_SIZE-1) ; total msg length ok?
brcc UART_HW_Uart0_RxCharIsr_econtent ; content error (msg too long)
subi r16, 2 ; subtract bytes already received
std Y+UART_HW_IFACE_OFFS_READBUFLEFT, r16 ; set new number of bytes left
brne UART_HW_Uart0_RxCharIsr_end ; jmp if still bytes left to receive
UART_HW_Uart0_RxCharIsr_msgFinished:
rcall UART_HW_Uart0_StopRx ; (R16)
ldi r16, NET_IFACE_OFFS_PACKETSIN_LOW
ldi r17, UART_HW_READMODE_MSGRECEIVED
rjmp UART_HW_Uart0_RxCharIsr_incCounterAndEnterMode
UART_HW_Uart0_RxCharIsr_hwerr:
ldi r16, NET_IFACE_OFFS_ERR_IO_LOW
rjmp UART_HW_Uart0_RxCharIsr_incCounterAndEnterSkipping
UART_HW_Uart0_RxCharIsr_econtent:
ldi r16, NET_IFACE_OFFS_ERR_CONTENT_LOW
rjmp UART_HW_Uart0_RxCharIsr_incCounterAndEnterSkipping
UART_HW_Uart0_RxCharIsr_overrun:
ldi r16, NET_IFACE_OFFS_ERR_NOBUF_LOW
UART_HW_Uart0_RxCharIsr_incCounterAndEnterSkipping:
rcall UART_HW_Uart0_StopRx ; (R16)
rcall UART_HW_Uart0_Flush ; (r16)
ldi r17, UART_HW_READMODE_SKIPPING
UART_HW_Uart0_RxCharIsr_incCounterAndEnterMode:
rcall NET_Interface_IncCounter16 ; (R24, R25)
std Y+UART_HW_IFACE_OFFS_READMODE, r17 ; set read mode
UART_HW_Uart0_RxCharIsr_end:
ret
#endif
; @end
; ---------------------------------------------------------------------------
; @routine UART_HW_Uart0_TxUdreIsr @global
;
; Handler for UDRE1 interrupt called when TX data register is empty.
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
; @clobbers R16, R17, X
UART_HW_Uart0_TxUdreIsr:
M_UART_HW_Uart_TxUdreIsr 0
ret
; @end
; ---------------------------------------------------------------------------
; @routine UART_HW_Uart0_TxCharIsr @global
;
; Handler for TXC1 interrupt called when a last byte has been completely sent and
; the data register is empty.
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
; @clobbers R16
UART_HW_Uart0_TxCharIsr:
M_UART_HW_Uart_TxCharIsr 0
ret
; @end
; ---------------------------------------------------------------------------
; @routine UART_HW_Uart0_SetAttnInput @global
;
; Set ATTN line as input (making it effectively HIGH due to pull-up resistor on
; the line)
;
; @clobbers none
UART_HW_Uart0_SetAttnInput:
M_UART_HW_Uart_SetAttnInput
ret
; @end
; ---------------------------------------------------------------------------
; @routine UART_HW_Uart0_SetAttnLow @global
;
; Set ATTN line low.
;
; @clobbers none
UART_HW_Uart0_SetAttnLow:
M_UART_HW_Uart_SetAttnLow
ret
; @end

218
avr/modules/uart_hw/lowlevel_uart1.asm
View File

@@ -1,218 +0,0 @@
; ***************************************************************************
; copyright : (C) 2025 by Martin Preuss
; email : martin@libchipcard.de
;
; ***************************************************************************
; * This file is part of the project "AqHome". *
; * Please see toplevel file COPYING of that project for license details. *
; ***************************************************************************
.cseg
; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_Init @global
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
; @clobbers R16, R17, X
UART_HW_Uart1_Init:
M_UART_HW_Uart_Init 1
ret
; @end
; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_StartRx @global
;
; @clobbers R16
UART_HW_Uart1_StartRx:
M_UART_HW_Uart_StartRx 1
ret
; @end
; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_StopRx @global
;
; @clobbers R16
UART_HW_Uart1_StopRx:
M_UART_HW_Uart_StopRx 1
ret
; @end
; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_StartTx @global
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
; @clobbers R16
UART_HW_Uart1_StartTx:
M_UART_HW_Uart_StartTx 1
ret
; @end
; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_StopTx @global
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
; @clobbers R16
UART_HW_Uart1_StopTx:
M_UART_HW_Uart_StopTx 1
ret
; @end
; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_Flush
;
; Flush receiption buffer.
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
; @clobbers R16
UART_HW_Uart1_Flush:
M_UART_HW_Uart_Flush 1
ret
; @end
; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_RxCharIsr @global
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
; @clobbers R16 (R17, R18, R24, R25, X)
UART_HW_Uart1_RxCharIsr:
M_UART_HW_Uart_RxCharFullDuplexIsr 1
ret
#if 0
; check for errors
lds r16, UCSR1A ; check for errors
andi r16, (1<<FE1) | (1<<DOR1) | (1<<UPE1)
brne UART_HW_Uart1_RxCharIsr_hwerr
; read char
lds r16, UCSR1A
sbrs r16, RXC1
rjmp UART_HW_Uart1_RxCharIsr_end ; no data
lds r16, UDR1 ; r16=received char
; check read mode
ldd r17, Y+UART_HW_IFACE_OFFS_READMODE
cpi r17, UART_HW_READMODE_READING
breq UART_HW_Uart1_RxCharIsr_storeChar
cpi r17, UART_HW_READMODE_SKIPPING
breq UART_HW_Uart1_RxCharIsr_skipChar
rjmp UART_HW_Uart1_RxCharIsr_overrun ; neither read nor skip mode
UART_HW_Uart1_RxCharIsr_skipChar:
clr r16
std Y+NET_IFACE_OFFS_READTIMER, r16 ; reset read timer
rjmp UART_HW_Uart1_RxCharIsr_end
UART_HW_Uart1_RxCharIsr_storeChar:
mov r18, r16 ; r18=received char
; check buffer
ldd r16, Y+UART_HW_IFACE_OFFS_READBUFNUM
cpi r16, 0xff
breq UART_HW_Uart1_RxCharIsr_overrun
; check for buffer overrun
ldd r17, Y+UART_HW_IFACE_OFFS_READBUFLEFT ; r17=bytes left
tst r17
breq UART_HW_Uart1_RxCharIsr_econtent ; msg too long
; actually store byte, increment/decrement counters and pos
ldd xl, Y+UART_HW_IFACE_OFFS_READBUFPOS_LOW
ldd xh, Y+UART_HW_IFACE_OFFS_READBUFPOS_HIGH
st X+, r18 ; r18=byte to store
clr r16
std Y+NET_IFACE_OFFS_READTIMER, r16 ; reset read timer
std Y+UART_HW_IFACE_OFFS_READBUFPOS_LOW, xl
std Y+UART_HW_IFACE_OFFS_READBUFPOS_HIGH, xh
ldd r18, Y+UART_HW_IFACE_OFFS_READBUFUSED ; r18=bytes in buffer
inc r18
std Y+UART_HW_IFACE_OFFS_READBUFUSED, r18
dec r17
std Y+UART_HW_IFACE_OFFS_READBUFLEFT, r17
breq UART_HW_Uart1_RxCharIsr_msgFinished
; check msg size
cpi r18, 2 ; bytes in buffer, exactly 2?
brne UART_HW_Uart1_RxCharIsr_end ; nope, done
sbiw xh:xl, 1 ; yes, determine message length (msgLen at previous pos)
ld r16, X+ ; read payload length byte
subi r16, -3 ; add 3 (dest addr, length, crc byte)
cpi r16, (NET_BUFFERS_SIZE-1) ; total msg length ok?
brcc UART_HW_Uart1_RxCharIsr_econtent ; content error (msg too long)
subi r16, 2 ; subtract bytes already received
std Y+UART_HW_IFACE_OFFS_READBUFLEFT, r16 ; set new number of bytes left
brne UART_HW_Uart1_RxCharIsr_end ; jmp if still bytes left to receive
UART_HW_Uart1_RxCharIsr_msgFinished:
ldi r16, NET_IFACE_OFFS_PACKETSIN_LOW
ldi r17, UART_HW_READMODE_MSGRECEIVED
rjmp UART_HW_Uart1_RxCharIsr_incCounterAndEnterMode
UART_HW_Uart1_RxCharIsr_hwerr:
ldi r16, NET_IFACE_OFFS_ERR_IO_LOW
rjmp UART_HW_Uart1_RxCharIsr_incCounterAndEnterSkipping
UART_HW_Uart1_RxCharIsr_econtent:
ldi r16, NET_IFACE_OFFS_ERR_CONTENT_LOW
rjmp UART_HW_Uart1_RxCharIsr_incCounterAndEnterSkipping
UART_HW_Uart1_RxCharIsr_overrun:
; ldi r16, NET_IFACE_OFFS_ERR_NOBUF_LOW
ldi r16, NET_IFACE_OFFS_ERR_MISSED_LOW
UART_HW_Uart1_RxCharIsr_incCounterAndEnterSkipping:
ldi r17, UART_HW_READMODE_SKIPPING
ldi r16, NET_IFACE_OFFS_HANDLED_LOW
UART_HW_Uart1_RxCharIsr_incCounterAndEnterMode:
rcall NET_Interface_IncCounter16 ; (R24, R25)
std Y+UART_HW_IFACE_OFFS_READMODE, r17 ; set read mode
UART_HW_Uart1_RxCharIsr_end:
#endif
; @end
; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_TxUdreIsr @global
;
; Handler for UDRE1 interrupt called when TX data register is empty.
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
; @clobbers R16, R17, X
UART_HW_Uart1_TxUdreIsr:
M_UART_HW_Uart_TxUdreIsr 1
ret
; @end
; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_TxCharIsr @global
;
; Handler for TXC1 interrupt called when a last byte has been completely sent and
; the data register is empty.
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
; @clobbers R16
UART_HW_Uart1_TxCharIsr:
M_UART_HW_Uart_TxCharIsr 1
ret
; @end

128
avr/modules/uart_hw/ttyonuart1.asm
View File

@@ -31,7 +31,7 @@ TtyOnUart1_Init:
ldi yl, LOW(ttyOnUart1_iface)
ldi yh, HIGH(ttyOnUart1_iface)
rcall UART_HW_Interface_Init ; (R16, R17, X)
rcall UART_HW_Uart1_Init ; (R16, R17, X)
rcall ttyOnUart1Init ; (R16, R17, X)
ldi r16, TTYONUART1_IFACENUM
std Y+NET_IFACE_OFFS_IFACENUM, r16
ret
@@ -82,7 +82,7 @@ TtyOnUart1_RxCharIsr:
push yh
ldi yl, LOW(ttyOnUart1_iface)
ldi yh, HIGH(ttyOnUart1_iface)
rcall UART_HW_Uart1_RxCharIsr ; (R16, R17, R18, R24, R25, X)
rcall ttyOnUart1RxCharIsr ; (R16, R17, R18, R24, R25, X)
pop yh
pop yl
pop xh
@@ -115,7 +115,7 @@ TtyOnUart1_TxUdreIsr:
push yh
ldi yl, LOW(ttyOnUart1_iface)
ldi yh, HIGH(ttyOnUart1_iface)
rcall UART_HW_Uart1_TxUdreIsr ; (R16, R17, X)
rcall ttyOnUart1TxUdreIsr ; (R16, R17, X)
pop yh
pop yl
pop xh
@@ -146,7 +146,7 @@ TtyOnUart1_TxCharIsr:
push yh
ldi yl, LOW(ttyOnUart1_iface)
ldi yh, HIGH(ttyOnUart1_iface)
rcall UART_HW_Uart1_TxCharIsr ; (R16, R17, R18, X)
rcall ttyOnUart1TxCharIsr ; (R16, R17, R18, X)
pop yh
pop yl
pop xh
@@ -181,7 +181,7 @@ TtyOnUart1_SendBuffer_setBuffer:
rcall UART_HW_Interface_SetWriteBuffer ; (R17)
ldi r17, UART_HW_WRITEMODE_WRITING
std Y+UART_HW_IFACE_OFFS_WRITEMODE, r17
rcall UART_HW_Uart1_StartTx ; (R16)
rcall ttyOnUart1StartTx ; (R16)
pop r15
out SREG, r15
sec
@@ -284,7 +284,7 @@ ttyOnUart1RunWaitBufferEmpty_checkTimer:
ldd r16, Y+NET_IFACE_OFFS_WRITETIMER
cpi r16, 10
brcs ttyOnUart1RunWaitBufferEmpty_end
rcall UART_HW_Uart1_StopTx ; disable transceiver and interrupts (R16)
rcall ttyOnUart1StopTx ; disable transceiver and interrupts (R16)
ldi r16, NET_IFACE_OFFS_ERR_COLLISIONS_LOW
rcall NET_Interface_IncCounter16 ; (R24, R25)
ttyOnUart1RunWaitBufferEmpty_enterIdle:
@@ -302,7 +302,7 @@ ttyOnUart1RunWaitBufferEmpty_end:
; @clobbers R16, R17, X (R24, R25)
ttyOnUart1RunWriteBufferEmpty:
rcall UART_HW_Uart1_StopTx ; disable transceiver and interrupts (R16)
rcall ttyOnUart1StopTx ; disable transceiver and interrupts (R16)
ldi r16, UART_HW_WRITEMODE_IDLE
std Y+UART_HW_IFACE_OFFS_WRITEMODE, r16
ldi r16, NET_IFACE_OFFS_PACKETSOUT_LOW ; increment packets counter
@@ -342,7 +342,7 @@ ttyOnUart1RunReadIdle:
brcc ttyOnUart1RunReadIdle_noBuf
ldi r16, UART_HW_READMODE_READING
std Y+UART_HW_IFACE_OFFS_READMODE, r16
rcall UART_HW_Uart1_StartRx ; R16
rcall ttyOnUart1StartRx ; R16
ret
ttyOnUart1RunReadIdle_noBuf:
ldi r16, NET_IFACE_OFFS_ERR_NOBUF_LOW
@@ -400,3 +400,115 @@ ttyOnUart1RunMsgReceived:
; ---------------------------------------------------------------------------
; @routine ttyOnUart1Init @global
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
; @clobbers R16, R17, X
ttyOnUart1Init:
M_UART_HW_Uart_Init 1
ret
; @end
; ---------------------------------------------------------------------------
; @routine ttyOnUart1StartRx @global
;
; @clobbers R16
ttyOnUart1StartRx:
M_UART_HW_Uart_StartRx 1
ret
; @end
; ---------------------------------------------------------------------------
; @routine ttyOnUart1StopRx @global
;
; @clobbers R16
ttyOnUart1StopRx:
M_UART_HW_Uart_StopRx 1
ret
; @end
; ---------------------------------------------------------------------------
; @routine ttyOnUart1StartTx @global
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
; @clobbers R16
ttyOnUart1StartTx:
M_UART_HW_Uart_StartTx 1
ret
; @end
; ---------------------------------------------------------------------------
; @routine ttyOnUart1StopTx @global
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
; @clobbers R16
ttyOnUart1StopTx:
M_UART_HW_Uart_StopTx 1
ret
; @end
; ---------------------------------------------------------------------------
; @routine ttyOnUart1RxCharIsr @global
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
; @clobbers R16 (R17, R18, R24, R25, X)
ttyOnUart1RxCharIsr:
M_UART_HW_Uart_RxCharFullDuplexIsr 1
ret
; @end
; ---------------------------------------------------------------------------
; @routine ttyOnUart1TxUdreIsr @global
;
; Handler for UDRE1 interrupt called when TX data register is empty.
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
; @clobbers R16, R17, X
ttyOnUart1TxUdreIsr:
M_UART_HW_Uart_TxUdreIsr 1
ret
; @end
; ---------------------------------------------------------------------------
; @routine ttyOnUart1TxCharIsr @global
;
; Handler for TXC1 interrupt called when a last byte has been completely sent and
; the data register is empty.
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
; @clobbers R16
ttyOnUart1TxCharIsr:
M_UART_HW_Uart_TxCharIsr 1
ret
; @end