TWIMASTER: Added two-wire-master code (bitbang).
This commit is contained in:
Martin Preuss
372
avr/twimaster.asm
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372
avr/twimaster.asm
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; ***************************************************************************
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; defines
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.equ TWI_BIT_LENGTH = 100000 ; 100000 and 200000 works for display
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; ***************************************************************************
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; data
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.dseg
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twiMasterDataBegin:
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twiMasterScanEnabled: .byte 1
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twiMasterLastScanned: .byte 1
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twiMasterDataEnd:
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; ***************************************************************************
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; code
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.cseg
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; ---------------------------------------------------------------------------
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; macros
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.macro twiClockHi
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cbi TWI_DDR_SCL, TWI_PINNUM_SCL ; set to input
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cbi TWI_PORT_SCL, TWI_PINNUM_SCL ; disable internal pullup
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.endmacro
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.macro twiClockLo
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sbi TWI_DDR_SCL, TWI_PINNUM_SCL ; set to output
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cbi TWI_PORT_SCL, TWI_PINNUM_SCL ; set to low
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.endmacro
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.macro twiDataHi
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cbi TWI_DDR_SDA, TWI_PINNUM_SDA ; set to input
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cbi TWI_PORT_SDA, TWI_PINNUM_SDA ; disable internal pullup
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.endmacro
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.macro twiDataLo
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sbi TWI_DDR_SDA, TWI_PINNUM_SDA ; set to output
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cbi TWI_PORT_SDA, TWI_PINNUM_SDA ; set to low
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.endmacro
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; ---------------------------------------------------------------------------
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; TWI_Master_Init
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;
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; IN:
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; OUT:
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; - CFLAG: set if okay, clear on error
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; USED:
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TWI_Master_Init:
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twiClockHi
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twiDataHi
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; preset SRAM data area
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ldi xh, HIGH(twiMasterDataBegin)
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ldi xl, LOW(twiMasterDataBegin)
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clr r16
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ldi r17, (twiMasterDataEnd-twiMasterDataBegin)
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rcall Utils_FillSram
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sec
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ret
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; ---------------------------------------------------------------------------
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; TWI_Master_Fini
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;
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; IN:
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; OUT:
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; USED:
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TWI_Master_Fini:
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sec
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ret
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; ---------------------------------------------------------------------------
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; TWI_Master_Run
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;
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; IN:
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; OUT:
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; USED:
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TWI_Master_Run:
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clc
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ret
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; ---------------------------------------------------------------------------
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; twiStart
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;
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; Send START condition on the bus.
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;
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; IN:
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; - nothing
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; OUT:
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; - nothing
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; USED: R22
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twiStart:
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twiDataHi
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Utils_WaitNanoSecs TWI_BIT_LENGTH, 0, r22
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twiClockHi
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Utils_WaitNanoSecs TWI_BIT_LENGTH, 0, r22
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twiDataLo
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Utils_WaitNanoSecs TWI_BIT_LENGTH, 0, r22
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twiClockLo
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Utils_WaitNanoSecs TWI_BIT_LENGTH, 0, r22
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ret
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; ---------------------------------------------------------------------------
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; twiStop
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;
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; Send STOP condition on the bus.
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;
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; IN:
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; - nothing
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; OUT:
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; - nothing
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; USED: R22
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twiStop:
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twiDataLo
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Utils_WaitNanoSecs TWI_BIT_LENGTH, 0, r22
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twiClockHi
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Utils_WaitNanoSecs TWI_BIT_LENGTH, 0, r22
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twiDataHi
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Utils_WaitNanoSecs TWI_BIT_LENGTH, 0, r22
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ret
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; ---------------------------------------------------------------------------
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; twiRestart
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;
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; Send START condition again (needed for some chips to send address in write mode
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; and receive data afterwards in read mode).
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;
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; IN:
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; - nothing
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; OUT:
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; - nothing
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; USED: R22
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twiRestart:
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twiDataHi
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twiClockHi
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rjmp twiStart
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; ---------------------------------------------------------------------------
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; twiReadBit
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;
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; Read a bit from the line (handling SCL line and possible clock stretching).
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;
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; IN:
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; - nothing
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; OUT:
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; - CARRY flag set: okay, cleared on error
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; - R16: bit read (if CARRY flag set), i.e. 0x00 or 0x01
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; USED: R16, R22
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twiReadBit:
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twiDataHi
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Utils_WaitNanoSecs TWI_BIT_LENGTH, 0, r22
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twiClockHi
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Utils_WaitNanoSecs TWI_BIT_LENGTH, 0, r22
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ldi r16, 100
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twiReadBit_loop:
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sbic TWI_PIN_SCL, TWI_PINNUM_SCL
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rjmp twiReadBit_clockReleased
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Utils_WaitNanoSecs TWI_BIT_LENGTH/20, 0, r22
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dec r16
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brne twiReadBit_loop
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; timeout
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clc
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ret
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twiReadBit_clockReleased:
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Utils_WaitNanoSecs TWI_BIT_LENGTH, 0, r22
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ldi r16, 1
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sbis TWI_PIN_SDA, TWI_PINNUM_SDA
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clr r16
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Utils_WaitNanoSecs TWI_BIT_LENGTH, 0, r22
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twiClockLo
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Utils_WaitNanoSecs TWI_BIT_LENGTH, 0, r22
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sec
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ret
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; ---------------------------------------------------------------------------
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; twiWriteBit
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;
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; Write a bit from the line (handling SCL and SDA line and possible clock stretching).
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;
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; IN:
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; - R16: bit to send (either 0x00 or 0x01)
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; OUT:
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; - CARRY flag set: okay, cleared on error
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; USED: R16, R22
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twiWriteBit:
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twiClockLo
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Utils_WaitNanoSecs TWI_BIT_LENGTH, 0, r22
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tst r16
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breq twiWriteBit_write0
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twiDataHi
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rjmp twiWriteBit_written
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twiWriteBit_write0:
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twiDataLo
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twiWriteBit_written:
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Utils_WaitNanoSecs TWI_BIT_LENGTH, 0, r22
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twiClockHi
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Utils_WaitNanoSecs TWI_BIT_LENGTH, 0, r22
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ldi r16, 100
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twiWriteBit_loop:
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sbic TWI_PIN_SCL, TWI_PINNUM_SCL
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rjmp twiWriteBit_clockReleased
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Utils_WaitNanoSecs TWI_BIT_LENGTH/20, 0, r22
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dec r16
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brne twiWriteBit_loop
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; timeout
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clc
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ret
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twiWriteBit_clockReleased:
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Utils_WaitNanoSecs TWI_BIT_LENGTH, 0, r22
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twiClockLo
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Utils_WaitNanoSecs TWI_BIT_LENGTH, 0, r22
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sec
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ret
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; ---------------------------------------------------------------------------
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; twiSendByte
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;
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; Write a byte to the bus and reads the ACK bit back.
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;
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; IN:
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; - R16: byte to send
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; OUT:
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; - CARRY flag set: okay, cleared on error
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; - R16: ACK bit read (0x00 or 0x01)
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; USED: R16, R17, R18, R22
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twiSendByte:
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mov r17, r16
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ldi r18, 8
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twiSendByte_loop:
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clr r16
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lsl r17 ; shift MSB out into carry flag
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rol r16 ; shift carry flag into r16
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rcall twiWriteBit ; (R16, R22)
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brcc twiSendByte_error
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dec r18
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brne twiSendByte_loop
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rcall twiReadBit ; r16: ACK bit received
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brcc twiSendByte_error
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sec
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ret
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twiSendByte_error:
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clc
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ret
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; ---------------------------------------------------------------------------
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; twiReceiveByte
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;
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; Read a byte from the bus. Does not send an ACK bit, this must be done by the caller,
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; if required.
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;
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; IN:
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; OUT:
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; - CARRY flag set: okay, cleared on error
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; - R16: byte received
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; USED: R16, R17, R18, R22
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twiReceiveByte:
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clr r17
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ldi r18, 8
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twiReceiveByte_loop:
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rcall twiReadBit
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brcc twiReceiveByte_error
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lsr r16
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rol r17
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dec r18
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brne twiReceiveByte_loop
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mov r16, r17
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sec
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ret
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twiReceiveByte_error:
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clc
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ret
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TWI_Master_ScanNext:
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in r15, SREG
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cli
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lds r16, twiMasterScanEnabled
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tst r16
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breq TWI_Master_ScanNext_end
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lds r16, twiMasterLastScanned
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tst r16
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brne TWI_Master_ScanNext_inc
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ldi r16, 7
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TWI_Master_ScanNext_inc:
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inc r16
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cpi r16, 121
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breq TWI_Master_ScanNext_finshed
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; check current address
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mov r21, r16
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rcall twiStart
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sec
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rol r16 ; (ADDR<<1) + 1: read from address
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rcall twiSendByte
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brcc TWI_Master_ScanNext_abort ; clock stretching too long, bus error
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sts twiMasterLastScanned, r21
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rcall twiStop
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tst r16
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brne TWI_Master_ScanNext_noAnswer
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; send message about available address
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mov r1, r21
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ldi r16, 1
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mov r2, r16
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ldi r16, 255 ; send to all
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push r15
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rcall COM_EnqueueI2cBusMember
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pop r15
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rjmp TWI_Master_ScanNext_end
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TWI_Master_ScanNext_noAnswer:
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; send message about available address
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; mov r1, r21
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; clr r2
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; ldi r16, 255 ; send to all
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; push r15
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; rcall COM_EnqueueI2cBusMember
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; pop r15
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rjmp TWI_Master_ScanNext_end
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TWI_Master_ScanNext_abort:
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rcall twiStop
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rjmp TWI_Master_ScanNext_end
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TWI_Master_ScanNext_finshed:
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clr r16
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sts twiMasterScanEnabled, r16
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TWI_Master_ScanNext_end:
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out SREG, r15
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ret
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