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avr: some sorting.

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This commit is contained in:
Martin Preuss
2024-09-18 20:22:13 +02:00
parent 5ca1fd4275
commit 741dd4fe12
1 changed files with 11 additions and 7 deletions
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18
avr/modules/basetimer/main.asm
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@@ -51,17 +51,12 @@ BaseTimer_Init: ; setup timer for IRQ every 100ms
ldi r17, (baseTimerModuleData_end-baseTimerModuleData) ldi r17, (baseTimerModuleData_end-baseTimerModuleData)
rcall Utils_FillSram rcall Utils_FillSram
ldi r16, (1<<CS02) | (1<<CS00) ; Prescaler 1024 ldi r16, (1<<CS02) | (0<<CS01) | (1<<CS00) ; Prescaler 1024
out TCCR0B, r16 out TCCR0B, r16
ldi r16, (1<<WGM01) ; CTC mode ldi r16, (1<<WGM01) | (0<<WGM00) ; CTC mode
out TCCR0A, r16 out TCCR0A, r16
ldi r16, (1<<OCF0A) ; clear pending interrupts
out TIFR0, r16
ldi r16, (1<<OCIE0A) ; Timer/Counter0 Output Compare Match A Interrupt Enable
out TIMSK0, r16
; ;
; Settings for clock 1Mhz (default) ; Settings for clock 1Mhz (default)
@@ -74,6 +69,7 @@ BaseTimer_Init: ; setup timer for IRQ every 100ms
ldi r16, 1 ldi r16, 1
sts baseTimerModuleReloadValue, r16 sts baseTimerModuleReloadValue, r16
sts baseTimerModuleTickCounter, r16
.endif .endif
; ;
@@ -87,8 +83,16 @@ BaseTimer_Init: ; setup timer for IRQ every 100ms
ldi r16, 10 ldi r16, 10
sts baseTimerModuleReloadValue, r16 sts baseTimerModuleReloadValue, r16
sts baseTimerModuleTickCounter, r16
.endif .endif
ldi r16, (1<<OCF0A) ; clear pending interrupts
out TIFR0, r16
ldi r16, (1<<OCIE0A) ; Timer/Counter0 Output Compare Match A Interrupt Enable
out TIMSK0, r16
sec sec
ret ret
; @end ; @end