From 741dd4fe12c0f1fe6a7fc36444f3a84aed0bc6de Mon Sep 17 00:00:00 2001
From: Martin Preuss <martin@aquamaniac.de>
Date: Wed, 18 Sep 2024 20:22:13 +0200
Subject: [PATCH] avr: some sorting.

---
 avr/modules/basetimer/main.asm | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

diff --git a/avr/modules/basetimer/main.asm b/avr/modules/basetimer/main.asm
index 8e3e249..e4bb851 100644
--- a/avr/modules/basetimer/main.asm
+++ b/avr/modules/basetimer/main.asm
@@ -51,17 +51,12 @@ BaseTimer_Init:            ; setup timer for IRQ every 100ms
   ldi r17, (baseTimerModuleData_end-baseTimerModuleData)
   rcall Utils_FillSram
 
-  ldi r16, (1<<CS02) | (1<<CS00)  ; Prescaler 1024
+  ldi r16, (1<<CS02) | (0<<CS01) | (1<<CS00)  ; Prescaler 1024
   out TCCR0B, r16
   
-  ldi r16, (1<<WGM01)             ; CTC mode
+  ldi r16, (1<<WGM01) | (0<<WGM00)             ; CTC mode
   out TCCR0A, r16
 
-  ldi r16, (1<<OCF0A)             ; clear pending interrupts
-  out TIFR0, r16
-  
-  ldi r16, (1<<OCIE0A)            ; Timer/Counter0 Output Compare Match A Interrupt Enable
-  out TIMSK0, r16
 
 ;
 ; Settings for clock 1Mhz (default)
@@ -74,6 +69,7 @@ BaseTimer_Init:            ; setup timer for IRQ every 100ms
 
   ldi r16, 1
   sts baseTimerModuleReloadValue, r16
+  sts baseTimerModuleTickCounter, r16
 .endif
 
 ;
@@ -87,8 +83,16 @@ BaseTimer_Init:            ; setup timer for IRQ every 100ms
 
   ldi r16, 10
   sts baseTimerModuleReloadValue, r16
+  sts baseTimerModuleTickCounter, r16
 .endif
 
+
+  ldi r16, (1<<OCF0A)             ; clear pending interrupts
+  out TIFR0, r16
+  
+  ldi r16, (1<<OCIE0A)            ; Timer/Counter0 Output Compare Match A Interrupt Enable
+  out TIMSK0, r16
+
   sec
   ret
 ; @end