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avr: more work on hardware based uart module.

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This commit is contained in:
Martin Preuss
2025-01-27 00:20:45 +01:00
parent a96bd7fc07
commit 52bbfcfb15
11 changed files with 650 additions and 71 deletions
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32
avr/modules/uart_hw/lowlevel_uart1.asm
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@@ -20,8 +20,7 @@
UART_HW_Uart1_StartRx:
lds r16, UCSR1B
sbr r16, (1<<RXCIE1) ; enable RX complete interrupt
sbr r16, (1<<RXEN1) ; enable receive
sbr r16, (1<<RXCIE1) | (1<<RXEN1) ; enable RX complete interrupt, enable receive
sts UCSR1B, r16
ret
; @end
@@ -35,8 +34,7 @@ UART_HW_Uart1_StartRx:
UART_HW_Uart1_StopRx:
lds r16, UCSR1B
cbr r16, (1<<RXCIE1) ; disable RX complete interrupt
cbr r16, (1<<RXEN1) ; disable receive
cbr r16, (1<<RXCIE1 | (1<<RXEN1)) ; disable RX complete interrupt, disable receive
sts UCSR1B, r16
ret
; @end
@@ -51,8 +49,7 @@ UART_HW_Uart1_StopRx:
UART_HW_Uart1_StartTx:
lds r16, UCSR1B
sbr r16, (1<<UDRIE1) ; enable TX data register empty interrupt
sbr r16, (1<<TXEN1) ; enable transceive
sbr r16, (1<<UDRIE1) | (1<<TXEN1) ; enable TX data register empty interrupt, enable transceive
sts UCSR1B, r16
ret
; @end
@@ -67,8 +64,7 @@ UART_HW_Uart1_StartTx:
UART_HW_Uart1_StopTx:
lds r16, UCSR1B
cbr r16, (1<<UDRIE1) ; disable TX data register empty interrupt
cbr r16, (1<<TXEN1) ; disable transceive
cbr r16, (1<<UDRIE1) | (1<<TXEN1) ; disable TX data register empty interrupt, disable transceive
sts UCSR1B, r16
ret
; @end
@@ -82,22 +78,22 @@ UART_HW_Uart1_StopTx:
; @clobbers R16 (R17, R18, X)
UART_HW_Uart1_RxCharIsr:
in r16, UCSR1A ; check for errors
lds r16, UCSR1A ; check for errors
andi r16, (1<<FE1) | (1<<DOR1) | (1<<UPE1)
breq UART_HW_Uart1_RxCharIsr_recv
ldd r16, Y+UART_HW_IFACE_OFFS_STATUS
ori r16, UART_HW_STATUS_HWERR
std Y+UART_HW_IFACE_OFFS_STATUS, r16
rjmp UART_HW_Uart1_RxCharIsr_end
breq UART_HW_Uart1_RxCharIsr_recv ; no error, receive next char
ldd r16, Y+UART_HW_IFACE_OFFS_STATUS ; set error status
ori r16, UART_HW_STATUS_HWERR ; -> HWERR
rjmp UART_HW_Uart1_RxCharIsr_setStatusAndEnd
UART_HW_Uart1_RxCharIsr_recv:
lds r16, UCSR1A
sbrs r16, RXC1
rjmp UART_HW_Uart1_RxCharIsr_end ; no data
rjmp UART_HW_Uart1_RxCharIsr_end ; no data
lds r16, UDR1
rcall UART_HW_InterfaceWriteToReadBuffer ; (R17, R18, X)
rcall UART_HW_InterfaceWriteToReadBuffer ; (R17, R18, X)
brcs UART_HW_Uart1_RxCharIsr_end
ldd r16, Y+UART_HW_IFACE_OFFS_STATUS ; set overrun error
ori r16, UART_HW_STATUS_OVERRUN
ldd r16, Y+UART_HW_IFACE_OFFS_STATUS ; set overrun error
ori r16, UART_HW_STATUS_OVERRUN ; -> OVERRUN
UART_HW_Uart1_RxCharIsr_setStatusAndEnd:
std Y+UART_HW_IFACE_OFFS_STATUS, r16
UART_HW_Uart1_RxCharIsr_end:
ret