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avr: fixed code order.

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only disable interrupts if message sent completely.
This commit is contained in:
Martin Preuss
2025-02-12 00:36:54 +01:00
parent 393d4b4f56
commit 35f2c2bd7e
1 changed files with 5 additions and 5 deletions
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10
avr/modules/uart_hw/m_lowlevel_uart.asm
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@@ -238,16 +238,16 @@ l_end_%:
; @clobbers R16 ; @clobbers R16
.macro M_UART_HW_Uart_TxCharIsr .macro M_UART_HW_Uart_TxCharIsr
; disable further TXC1 interrupts
lds r16, UCSR@0B
cbr r16, (1<<TXC@0) ; disable TXC1 interrupt
sts UCSR@0B, r16
; check write mode ; check write mode
ldd r16, Y+UART_HW_IFACE_OFFS_WRITEMODE ldd r16, Y+UART_HW_IFACE_OFFS_WRITEMODE
cpi r16, UART_HW_WRITEMODE_WAITBUFFEREMPTY cpi r16, UART_HW_WRITEMODE_WAITBUFFEREMPTY
brne l_end_% brne l_end_%
; disable further TXC1 interrupts
lds r16, UCSR@0B
cbr r16, (1<<TXC@0) ; disable TXC1 interrupt
sts UCSR@0B, r16
; change write mode to WRITEBUFFEREMPTY ; change write mode to WRITEBUFFEREMPTY
ldi r16, UART_HW_WRITEMODE_WRITEBUFFEREMPTY ldi r16, UART_HW_WRITEMODE_WRITEBUFFEREMPTY
std Y+UART_HW_IFACE_OFFS_WRITEMODE, r16 std Y+UART_HW_IFACE_OFFS_WRITEMODE, r16