From 35f2c2bd7e6bd13796481ac99d2c3a653db2c11a Mon Sep 17 00:00:00 2001
From: Martin Preuss <martin@aquamaniac.de>
Date: Wed, 12 Feb 2025 00:36:54 +0100
Subject: [PATCH] avr: fixed code order.

only disable interrupts if message sent completely.
---
 avr/modules/uart_hw/m_lowlevel_uart.asm | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/avr/modules/uart_hw/m_lowlevel_uart.asm b/avr/modules/uart_hw/m_lowlevel_uart.asm
index 03f14d4..a0d2f09 100644
--- a/avr/modules/uart_hw/m_lowlevel_uart.asm
+++ b/avr/modules/uart_hw/m_lowlevel_uart.asm
@@ -238,16 +238,16 @@ l_end_%:
 ; @clobbers R16
 
 .macro M_UART_HW_Uart_TxCharIsr
-  ; disable further TXC1 interrupts
-  lds r16, UCSR@0B
-  cbr r16, (1<<TXC@0)                          ; disable TXC1 interrupt
-  sts UCSR@0B, r16
-
   ; check write mode
   ldd r16, Y+UART_HW_IFACE_OFFS_WRITEMODE
   cpi r16, UART_HW_WRITEMODE_WAITBUFFEREMPTY
   brne l_end_%
 
+  ; disable further TXC1 interrupts
+  lds r16, UCSR@0B
+  cbr r16, (1<<TXC@0)                          ; disable TXC1 interrupt
+  sts UCSR@0B, r16
+
   ; change write mode to WRITEBUFFEREMPTY
   ldi r16, UART_HW_WRITEMODE_WRITEBUFFEREMPTY
   std Y+UART_HW_IFACE_OFFS_WRITEMODE, r16