avr: fixed code order.

only disable interrupts if message sent completely.
This commit is contained in:
Martin Preuss
2025-02-12 00:36:54 +01:00
parent 393d4b4f56
commit 35f2c2bd7e

View File

@@ -238,16 +238,16 @@ l_end_%:
; @clobbers R16
.macro M_UART_HW_Uart_TxCharIsr
; disable further TXC1 interrupts
lds r16, UCSR@0B
cbr r16, (1<<TXC@0) ; disable TXC1 interrupt
sts UCSR@0B, r16
; check write mode
ldd r16, Y+UART_HW_IFACE_OFFS_WRITEMODE
cpi r16, UART_HW_WRITEMODE_WAITBUFFEREMPTY
brne l_end_%
; disable further TXC1 interrupts
lds r16, UCSR@0B
cbr r16, (1<<TXC@0) ; disable TXC1 interrupt
sts UCSR@0B, r16
; change write mode to WRITEBUFFEREMPTY
ldi r16, UART_HW_WRITEMODE_WRITEBUFFEREMPTY
std Y+UART_HW_IFACE_OFFS_WRITEMODE, r16