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reset uart_hw code to what works on t03.

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This commit is contained in:
Martin Preuss
2025-05-24 17:45:33 +02:00
parent 027edb9aba
commit 349c11d641
4 changed files with 42 additions and 202 deletions
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146
avr/modules/uart_hw/m_lowlevel_uart.asm
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@@ -30,16 +30,12 @@
ldi r17, 0
.endif
M_IO_WRITE UBRR@0H, r17
M_IO_WRITE UBRR@0L, r16
sts UBRR@0H, r17
sts UBRR@0L, r16
; set character format
.ifdef URSEL
ldi r16, (1<<URSEL) | (1<<USBS@0)|(3<<UCSZ@00)
.else
ldi r16, (1<<USBS@0)|(3<<UCSZ@00)
.endif
M_IO_WRITE UCSR@0C, r16
sts UCSR@0C, r16
.endmacro
; @end
@@ -52,9 +48,9 @@
; @clobbers none
.macro M_UART_HW_Uart_StartRx
M_IO_READ r16, UCSR@0B
lds r16, UCSR@0B
sbr r16, (1<<RXCIE@0) | (1<<RXEN@0) ; enable RX complete interrupt, enable receive
M_IO_WRITE UCSR@0B, r16
sts UCSR@0B, r16
.endmacro
; @end
@@ -67,9 +63,9 @@
; @clobbers R16
.macro M_UART_HW_Uart_StopRx
M_IO_READ r16, UCSR@0B
lds r16, UCSR@0B
cbr r16, (1<<RXCIE@0 | (1<<RXEN@0)) ; disable RX complete interrupt, disable receive
M_IO_WRITE UCSR@0B, r16
sts UCSR@0B, r16
.endmacro
; @end
@@ -83,13 +79,12 @@
; @clobbers R16
.macro M_UART_HW_Uart_StartTx
M_IO_READ r16, UCSR@0A
lds r16, UCSR@0A
cbr r16, (1<<TXC@0) ; clear TXCn interrupt
M_IO_WRITE UCSR@0A, r16
M_IO_READ r16, UCSR@0B
sts UCSR@0A, r16
lds r16, UCSR@0B
sbr r16, (1<<UDRIE@0) | (1<<TXC@0) | (1<<TXEN@0) ; enable TX UDRE and TXC1 interrupt, enable transceive
M_IO_WRITE UCSR@0B, r16
sts UCSR@0B, r16
.endmacro
; @end
@@ -103,9 +98,9 @@
; @clobbers R16
.macro M_UART_HW_Uart_StopTx
M_IO_READ r16, UCSR@0B
lds r16, UCSR@0B
cbr r16, (1<<UDRIE@0) | (1<<TXC@0) | (1<<TXEN@0) ; disable TX UDRE and TXC1 interrupt, enable transceive
M_IO_WRITE UCSR@0B, r16
sts UCSR@0B, r16
.endmacro
; @end
@@ -122,10 +117,10 @@
.macro M_UART_HW_Uart_Flush
l_loop_%:
M_IO_READ r16, UCSR@0A
lds r16, UCSR@0A
sbrs r16, RXC@0
rjmp l_end_%
M_IO_READ r16, USART@0_DATAREG
lds r16, UDR@0
clr r16
std Y+NET_IFACE_OFFS_READTIMER, r16
rjmp l_loop_%
@@ -144,14 +139,14 @@ l_end_%:
.macro M_UART_HW_Uart_RxCharHalfDuplexIsr
; check for errors
M_IO_READ r16, UCSR@0A ; check for errors
lds r16, UCSR@0A ; check for errors
andi r16, (1<<FE@0) | (1<<DOR@0) | (1<<UPE@0)
brne l_hwerr_%
; read char
M_IO_READ r16, UCSR@0A
lds r16, UCSR@0A
sbrs r16, RXC@0
rjmp l_end_% ; no data
M_IO_READ r16, USART@0_DATAREG ; r16=received char
lds r16, UDR@0 ; r16=received char
; check read mode
ldd r17, Y+UART_HW_IFACE_OFFS_READMODE
cpi r17, UART_HW_READMODE_READING
@@ -208,9 +203,6 @@ l_msgFinished_%:
ldi r17, UART_HW_READMODE_MSGRECEIVED
rjmp l_incCounterAndEnterMode_%
l_hwerr_%:
sbrc r16, DOR ; (1<<FE@0) | (1<<DOR@0) | (1<<UPE@0)
rjmp DEBUG2
ldi r16, NET_IFACE_OFFS_ERR_IO_LOW
rjmp l_incCounterAndEnterSkipping_%
l_econtent_%:
@@ -231,90 +223,6 @@ l_end_%:
; ---------------------------------------------------------------------------
; @macro M_UART_HW_Uart_EnterReceivedChar
;
; @param %0 UART number ("0" for UART0)
; @param r16 received char
; @param Y pointer to interface data in SRAM
; @clobbers R16 (R17, R18, R24, R25, X)
.macro M_UART_HW_Uart_EnterReceivedChar
; check read mode
ldd r17, Y+UART_HW_IFACE_OFFS_READMODE
cpi r17, UART_HW_READMODE_READING
breq l_storeChar_%
cpi r17, UART_HW_READMODE_SKIPPING
breq l_skipChar_%
rjmp l_overrun_% ; neither read nor skip mode
l_skipChar_%:
clr r16
std Y+NET_IFACE_OFFS_READTIMER, r16 ; reset read timer
rjmp l_end_%
l_storeChar_%:
mov r18, r16 ; r18=received char
; check buffer
ldd r16, Y+UART_HW_IFACE_OFFS_READBUFNUM
cpi r16, 0xff
breq l_overrun_%
; check for buffer overrun
ldd r17, Y+UART_HW_IFACE_OFFS_READBUFLEFT ; r17=bytes left
tst r17
breq l_econtent_% ; msg too long
; actually store byte, increment/decrement counters and pos
ldd xl, Y+UART_HW_IFACE_OFFS_READBUFPOS_LOW
ldd xh, Y+UART_HW_IFACE_OFFS_READBUFPOS_HIGH
st X+, r18 ; r18=byte to store
clr r16
std Y+NET_IFACE_OFFS_READTIMER, r16 ; reset read timer
std Y+UART_HW_IFACE_OFFS_READBUFPOS_LOW, xl
std Y+UART_HW_IFACE_OFFS_READBUFPOS_HIGH, xh
ldd r18, Y+UART_HW_IFACE_OFFS_READBUFUSED ; r18=bytes in buffer
inc r18
std Y+UART_HW_IFACE_OFFS_READBUFUSED, r18
dec r17
std Y+UART_HW_IFACE_OFFS_READBUFLEFT, r17
breq l_msgFinished_%
; check msg size
cpi r18, 2 ; bytes in buffer, exactly 2?
brne l_end_% ; nope, done
sbiw xh:xl, 1 ; yes, determine message length (msgLen at previous pos)
ld r16, X+ ; read payload length byte
inc r16 ; + dest addr
inc r16 ; + msg length
inc r16 ; + CRC byte
cpi r16, (NET_BUFFERS_SIZE-2) ; total msg length ok? (subtract 1 for buffer header byte)
brcc l_econtent_% ; content error (msg too long)
subi r16, 2 ; subtract bytes already received
std Y+UART_HW_IFACE_OFFS_READBUFLEFT, r16 ; set new number of bytes left
brne l_end_% ; jmp if still bytes left to receive
l_msgFinished_%:
M_UART_HW_Uart_StopRx @0 ; (R16)
ldi r16, NET_IFACE_OFFS_PACKETSIN_LOW
ldi r17, UART_HW_READMODE_MSGRECEIVED
rjmp l_incCounterAndEnterMode_%
l_econtent_%:
ldi r16, NET_IFACE_OFFS_ERR_CONTENT_LOW
rjmp l_incCounterAndEnterSkipping_%
l_overrun_%:
ldi r16, NET_IFACE_OFFS_ERR_NOBUF_LOW
l_incCounterAndEnterSkipping_%:
M_UART_HW_Uart_StopRx @0 ; (R16)
ldi r17, UART_HW_READMODE_SKIPPING
l_incCounterAndEnterMode_%:
rcall NET_Interface_IncCounter16 ; (R24, R25)
std Y+UART_HW_IFACE_OFFS_READMODE, r17 ; set read mode
l_end_%:
.endmacro
; @end
; ---------------------------------------------------------------------------
; @macro M_UART_HW_Uart_RxCharFullDuplexIsr
;
@@ -324,14 +232,14 @@ l_end_%:
.macro M_UART_HW_Uart_RxCharFullDuplexIsr
; check for errors
M_IO_READ r16, UCSR@0A ; check for errors
lds r16, UCSR@0A ; check for errors
andi r16, (1<<FE@0) | (1<<DOR@0) | (1<<UPE@0)
brne l_hwerr_%
; read char
M_IO_READ r16, UCSR@0A
lds r16, UCSR@0A
sbrs r16, RXC@0
rjmp l_end_% ; no data
M_IO_READ r16, USART@0_DATAREG ; r16=received char
lds r16, UDR@0 ; r16=received char
; check read mode
ldd r17, Y+UART_HW_IFACE_OFFS_READMODE
cpi r17, UART_HW_READMODE_READING
@@ -418,7 +326,7 @@ l_end_%:
; @clobbers R16, R17, X
.macro M_UART_HW_Uart_TxUdreIsr
M_IO_READ r16, UCSR@0A
lds r16, UCSR@0A
sbrs r16,UDRE@0
rjmp l_disable_irq_% ; not ready
@@ -447,7 +355,7 @@ l_end_%:
std Y+UART_HW_IFACE_OFFS_WRITEBUFLEFT, r17
; send byte, reset write timer
M_IO_WRITE USART@0_DATAREG, r16
sts UDR@0, r16
clr r16
std Y+NET_IFACE_OFFS_WRITETIMER, r16 ; reset write timer
@@ -459,9 +367,9 @@ l_end_%:
l_disable_irq_%:
; disable further DRE1 interrupts
M_IO_READ r16, UCSR@0B
lds r16, UCSR@0B
cbr r16, (1<<UDRIE@0) ; disable TX data register empty interrupt
M_IO_WRITE UCSR@0B, r16
sts UCSR@0B, r16
l_end_%:
.endmacro
; @end
@@ -485,9 +393,9 @@ l_end_%:
brne l_end_%
; disable further TXC1 interrupts
M_IO_READ r16, UCSR@0B
lds r16, UCSR@0B
cbr r16, (1<<TXC@0) ; disable TXC1 interrupt
M_IO_WRITE UCSR@0B, r16
sts UCSR@0B, r16
; change write mode to WRITEBUFFEREMPTY
ldi r16, UART_HW_WRITEMODE_WRITEBUFFEREMPTY