From 349c11d64157fd191f1c509fd75955d07e13ca9c Mon Sep 17 00:00:00 2001
From: Martin Preuss <martin@aquamaniac.de>
Date: Sat, 24 May 2025 17:45:33 +0200
Subject: [PATCH] reset uart_hw code to what works on t03.

---
 avr/modules/uart_hw/comonuart0.asm      |  95 +++------------
 avr/modules/uart_hw/lowlevel.asm        |   1 -
 avr/modules/uart_hw/m_lowlevel_uart.asm | 146 +++++-------------------
 avr/modules/uart_hw/ttyonuart1.asm      |   2 +-
 4 files changed, 42 insertions(+), 202 deletions(-)

diff --git a/avr/modules/uart_hw/comonuart0.asm b/avr/modules/uart_hw/comonuart0.asm
index f4305da..60ebe7b 100644
--- a/avr/modules/uart_hw/comonuart0.asm
+++ b/avr/modules/uart_hw/comonuart0.asm
@@ -10,7 +10,7 @@
 
 .equ COMONUART0_IFACENUM = 1
 .equ COMONUART0_READ_TIMEOUT = 3
-.equ COMONUART0_MSG_INTERVAL = 0
+.equ COMONUART0_MSG_INTERVAL = 1
 
 
 
@@ -30,32 +30,17 @@ comOnUart0_iface: .byte UART_HW_IFACE_SIZE
 ComOnUart0_Init:
   ldi yl, LOW(comOnUart0_iface)
   ldi yh, HIGH(comOnUart0_iface)
-  rcall comOnUart0SetAttnInput            ; (none)
+  rcall comOnUart0SetAttnInput   ; (none)
 
   rcall UART_HW_Interface_Init            ; (R16, R17, X)
-  rcall comOnUart0Init                    ; (R16, R17, X)
+  rcall comOnUart0Init                ; (R16, R17, X)
   ldi r16, COMONUART0_IFACENUM
   std Y+NET_IFACE_OFFS_IFACENUM, r16
 
-.if COM_IRQ_BIT_ATTN == INT0
-  M_IO_READ r16, MCUCR
-  cbr r16, (1<<ISC01) | (1<<ISC00)
-  sbr r16, (1<<ISC01) | (0<<ISC00)        ; falling edge of ATTN
-;  sbr r16, (0<<ISC01) | (0<<ISC00)         ; low level triggers
-
-  M_IO_READ r16, COM_IRQ_ADDR_ATTN        ; enable irq for ATTN line
-  sbr r16, (1<<COM_IRQ_BIT_ATTN)
-  M_IO_WRITE COM_IRQ_ADDR_ATTN, r16
-
-.endif
-
-
-.ifdef COM_IRQ_GIMSK_ATTN
-  M_IO_READ r16, GIMSK                    ; enable pin change irq PCIE0 or PCIE1
-  sbr r16, (1<<COM_IRQ_GIMSK_ATTN)
-  M_IO_WRITE GIMSK, R16
-.endif
-
+  sbi COM_IRQ_ADDR_ATTN, COM_IRQ_BIT_ATTN ; enable pin change irq for ATTN line
+  in r16, GIMSK                           ; enable pin change irq PCIE0 or PCIE1
+  ori r16, (1<<COM_IRQ_GIMSK_ATTN)
+  out GIMSK, R16
   ldi r16, (1<<COM_IRQ_GIFR_ATTN)         ; clear pending irq by writing 1 to ATTN bit
   out GIFR, r16
 
@@ -218,8 +203,6 @@ ComOnUart0_AttnChangeIsr:
 ; @clobbers R16 (R17, R24, R25, X)
 
 comOnUart0ActOnAttn:
-;  cbi LED_SIMPLE_PORT, LED_SIMPLE_PINNUM   ; on DEBUG
-  
   ldd r16, Y+UART_HW_IFACE_OFFS_WRITEMODE  ; test for active write mode
   cpi r16, UART_HW_WRITEMODE_IDLE
   brne comOnUart0ActOnAttn_end             ; in write mode, don't start read mode
@@ -230,7 +213,6 @@ comOnUart0ActOnAttn:
 
   sbic COM_ATTN_INPUT, COM_ATTN_PIN        ; ATTN high?
     rjmp comOnUart0ActOnAttn_end
-
   rcall comOnUart0StartReading           ; (R16, R17, R24, R25, X)
 
 comOnUart0ActOnAttn_end:
@@ -379,7 +361,6 @@ comOnUart0RunWriteIdle:
   rcall NET_Interface_GetNextOutgoingMsgNum  ; take msg from queue (R17, R18, X)
 comOnUart0RunWriteIdle_end:
   ret
-; @end
 
 
 ; ---------------------------------------------------------------------------
@@ -536,8 +517,6 @@ comOnUart0Init:
     lds r16, COM_ATTN_PUE
     cbr r16, COM_ATTN_PIN           ; disable pullup on ATTN
     sts COM_ATTN_PUE, r16
-.else
-  cbi COM_ATTN_OUTPUT, COM_ATTN_PIN ; disable pullup on ATTN
 .endif
   rcall comOnUart0SetAttnInput
   M_UART_HW_Uart_Init 0
@@ -552,10 +531,6 @@ comOnUart0Init:
 ; @clobbers R16
 
 comOnUart0StartRx:
-  M_IO_READ r16, UCSR0A                              ; clear errors
-  cbr r16, (1<<FE0) | (1<<DOR0) | (1<<UPE0)
-  M_IO_WRITE UCSR0A, r16
-
   M_UART_HW_Uart_StartRx 0
   ret
 ; @end
@@ -603,46 +578,15 @@ comOnUart0StopTx:
 ; @routine comOnUart0RxCharIsr @global
 ;
 ; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
-; @clobbers R16, R17 (R18, R24, R25, X)
-
-comOnUart0RxCharIsr:
-;  M_UART_HW_Uart_RxCharHalfDuplexIsr 0
-  M_IO_READ r16, UCSR0A                              ; check for errors
-;  mov r17, r16
-;  andi r17, (1<<FE0) | (1<<DOR0) | (1<<UPE0)
-;  brne comOnUart0RxCharIsr_hwerr
-  sbrs r16, RXC0
-    rjmp comOnUart0RxCharIsr_end
-  M_IO_READ r16, USART0_DATAREG                      ; r16=received char
-  rcall comOnUart0EnterReceivedChar
-  rjmp comOnUart0RxCharIsr_end
-comOnUart0RxCharIsr_hwerr:
-  M_UART_HW_Uart_StopRx 0                ; (R16)
-  ldi r16, NET_IFACE_OFFS_ERR_IO_LOW
-  ldi r17, UART_HW_READMODE_SKIPPING
-  rcall NET_Interface_IncCounter16              ; (R24, R25)
-  std Y+UART_HW_IFACE_OFFS_READMODE, r17        ; set read mode
-comOnUart0RxCharIsr_end:
-  ret
-; @end
-
-
-
-; ---------------------------------------------------------------------------
-; @routine comOnUart0EnterReceivedChar
-;
-; @param r16 received char
-; @param Y pointer to interface data in SRAM
 ; @clobbers R16 (R17, R18, R24, R25, X)
 
-comOnUart0EnterReceivedChar:
-  M_UART_HW_Uart_EnterReceivedChar 0
+comOnUart0RxCharIsr:
+  M_UART_HW_Uart_RxCharHalfDuplexIsr 0
   ret
 ; @end
 
 
 
-
 ; ---------------------------------------------------------------------------
 ; @routine comOnUart0TxUdreIsr @global
 ;
@@ -683,17 +627,12 @@ comOnUart0TxCharIsr:
 ; @clobbers none
 
 comOnUart0SetAttnInput:
-  cbi COM_ATTN_DDR, COM_ATTN_PIN          ; set ATTN as input
-.ifndef COM_ATTN_PUE
-  cbi COM_ATTN_OUTPUT, COM_ATTN_PIN       ; disable pullup on ATTN
+  cbi COM_ATTN_DDR, COM_ATTN_PIN           ; set ATTN as input
+.ifdef COM_ATTN_PUE
+;  cbi COM_ATTN_PUE, COM_ATTN_PIN           ; disable pullup on ATTN
+.else
+  cbi COM_ATTN_OUTPUT, COM_ATTN_PIN        ; disable pullup on ATTN
 .endif
-
-.if COM_IRQ_BIT_ATTN == INT0
-  M_IO_READ r16, COM_IRQ_ADDR_ATTN        ; enable irq for ATTN line
-  sbr r16, (1<<COM_IRQ_BIT_ATTN)
-  M_IO_WRITE COM_IRQ_ADDR_ATTN, r16
-.endif
-
   ret
 ; @end
 
@@ -707,12 +646,6 @@ comOnUart0SetAttnInput:
 ; @clobbers none
 
 comOnUart0SetAttnLow:
-.if COM_IRQ_BIT_ATTN == INT0
-  M_IO_READ r16, COM_IRQ_ADDR_ATTN        ; disable irq for ATTN line
-  cbr r16, (1<<COM_IRQ_BIT_ATTN)
-  M_IO_WRITE COM_IRQ_ADDR_ATTN, r16
-.endif
-
   sbi COM_ATTN_DDR, COM_ATTN_PIN            ; set ATTN as output
   cbi COM_ATTN_OUTPUT, COM_ATTN_PIN         ; set ATTN low
   ret
diff --git a/avr/modules/uart_hw/lowlevel.asm b/avr/modules/uart_hw/lowlevel.asm
index 376bc47..e223100 100644
--- a/avr/modules/uart_hw/lowlevel.asm
+++ b/avr/modules/uart_hw/lowlevel.asm
@@ -85,7 +85,6 @@ UART_HW_Interface_SetWriteBuffer:
 ; ---------------------------------------------------------------------------
 ; @routine UART_HW_Interface_EnsureReadBuffer
 ;
-; @return CFLAG set if okay, cleared on error
 ; @clobbers R16 (R17, R24, R25, X)
 
 UART_HW_Interface_EnsureReadBuffer:
diff --git a/avr/modules/uart_hw/m_lowlevel_uart.asm b/avr/modules/uart_hw/m_lowlevel_uart.asm
index 693fc24..d9da1b8 100644
--- a/avr/modules/uart_hw/m_lowlevel_uart.asm
+++ b/avr/modules/uart_hw/m_lowlevel_uart.asm
@@ -30,16 +30,12 @@
   ldi r17, 0  
 .endif
 
-  M_IO_WRITE UBRR@0H, r17
-  M_IO_WRITE UBRR@0L, r16
+  sts UBRR@0H, r17
+  sts UBRR@0L, r16
 
   ; set character format 
-.ifdef URSEL
-  ldi r16, (1<<URSEL) | (1<<USBS@0)|(3<<UCSZ@00)
-.else
   ldi r16, (1<<USBS@0)|(3<<UCSZ@00)
-.endif
-  M_IO_WRITE UCSR@0C, r16
+  sts UCSR@0C, r16
 .endmacro
 ; @end
 
@@ -52,9 +48,9 @@
 ; @clobbers none
 
 .macro M_UART_HW_Uart_StartRx
-  M_IO_READ r16, UCSR@0B
+  lds r16, UCSR@0B
   sbr r16, (1<<RXCIE@0) | (1<<RXEN@0)  ; enable RX complete interrupt, enable receive
-  M_IO_WRITE UCSR@0B, r16
+  sts UCSR@0B, r16
 .endmacro
 ; @end
 
@@ -67,9 +63,9 @@
 ; @clobbers R16
 
 .macro M_UART_HW_Uart_StopRx
-  M_IO_READ r16, UCSR@0B
+  lds r16, UCSR@0B
   cbr r16, (1<<RXCIE@0 | (1<<RXEN@0))   ; disable RX complete interrupt, disable receive
-  M_IO_WRITE UCSR@0B, r16
+  sts UCSR@0B, r16
 .endmacro
 ; @end
 
@@ -83,13 +79,12 @@
 ; @clobbers R16
 
 .macro M_UART_HW_Uart_StartTx
-  M_IO_READ r16, UCSR@0A
+  lds r16, UCSR@0A
   cbr r16, (1<<TXC@0)                               ; clear TXCn interrupt
-  M_IO_WRITE UCSR@0A, r16
-
-  M_IO_READ r16, UCSR@0B
+  sts UCSR@0A, r16
+  lds r16, UCSR@0B
   sbr r16, (1<<UDRIE@0) | (1<<TXC@0) | (1<<TXEN@0)  ; enable TX UDRE and TXC1 interrupt, enable transceive
-  M_IO_WRITE UCSR@0B, r16
+  sts UCSR@0B, r16
 .endmacro
 ; @end
 
@@ -103,9 +98,9 @@
 ; @clobbers R16
 
 .macro M_UART_HW_Uart_StopTx
-  M_IO_READ r16, UCSR@0B
+  lds r16, UCSR@0B
   cbr r16, (1<<UDRIE@0) | (1<<TXC@0) | (1<<TXEN@0)  ; disable TX UDRE and TXC1 interrupt, enable transceive
-  M_IO_WRITE UCSR@0B, r16
+  sts UCSR@0B, r16
 .endmacro
 ; @end
 
@@ -122,10 +117,10 @@
 
 .macro M_UART_HW_Uart_Flush
 l_loop_%:
-    M_IO_READ r16, UCSR@0A
+    lds r16, UCSR@0A
     sbrs r16, RXC@0
       rjmp l_end_%
-    M_IO_READ r16, USART@0_DATAREG
+    lds r16, UDR@0
     clr r16
     std Y+NET_IFACE_OFFS_READTIMER, r16
   rjmp l_loop_%
@@ -144,14 +139,14 @@ l_end_%:
 
 .macro M_UART_HW_Uart_RxCharHalfDuplexIsr
   ; check for errors
-  M_IO_READ r16, UCSR@0A                              ; check for errors
+  lds r16, UCSR@0A                              ; check for errors
   andi r16, (1<<FE@0) | (1<<DOR@0) | (1<<UPE@0)
   brne l_hwerr_%
   ; read char
-  M_IO_READ r16, UCSR@0A
+  lds r16, UCSR@0A
   sbrs r16, RXC@0
     rjmp l_end_%                                ; no data
-  M_IO_READ r16, USART@0_DATAREG                                ; r16=received char
+  lds r16, UDR@0                                ; r16=received char
   ; check read mode
   ldd r17, Y+UART_HW_IFACE_OFFS_READMODE
   cpi r17, UART_HW_READMODE_READING
@@ -208,9 +203,6 @@ l_msgFinished_%:
   ldi r17, UART_HW_READMODE_MSGRECEIVED
   rjmp l_incCounterAndEnterMode_%
 l_hwerr_%:
-  sbrc r16, DOR       ; (1<<FE@0) | (1<<DOR@0) | (1<<UPE@0)
-    rjmp DEBUG2
-
   ldi r16, NET_IFACE_OFFS_ERR_IO_LOW
   rjmp l_incCounterAndEnterSkipping_%
 l_econtent_%:
@@ -231,90 +223,6 @@ l_end_%:
 
 
 
-
-; ---------------------------------------------------------------------------
-; @macro M_UART_HW_Uart_EnterReceivedChar
-;
-; @param %0 UART number ("0" for UART0)
-; @param r16 received char
-; @param Y pointer to interface data in SRAM
-; @clobbers R16 (R17, R18, R24, R25, X)
-
-.macro M_UART_HW_Uart_EnterReceivedChar
-  ; check read mode
-  ldd r17, Y+UART_HW_IFACE_OFFS_READMODE
-  cpi r17, UART_HW_READMODE_READING
-  breq l_storeChar_%
-  cpi r17, UART_HW_READMODE_SKIPPING
-  breq l_skipChar_%
-  rjmp l_overrun_%                              ; neither read nor skip mode
-l_skipChar_%:
-  clr r16
-  std Y+NET_IFACE_OFFS_READTIMER, r16           ; reset read timer
-  rjmp l_end_%
-l_storeChar_%:
-  mov r18, r16                                  ; r18=received char
-  ; check buffer
-  ldd r16, Y+UART_HW_IFACE_OFFS_READBUFNUM
-  cpi r16, 0xff
-  breq l_overrun_%
-
-  ; check for buffer overrun
-  ldd r17, Y+UART_HW_IFACE_OFFS_READBUFLEFT     ; r17=bytes left
-  tst r17
-  breq l_econtent_%         ; msg too long
-
-  ; actually store byte, increment/decrement counters and pos
-  ldd xl, Y+UART_HW_IFACE_OFFS_READBUFPOS_LOW
-  ldd xh, Y+UART_HW_IFACE_OFFS_READBUFPOS_HIGH
-  st X+, r18                                    ; r18=byte to store
-  clr r16
-  std Y+NET_IFACE_OFFS_READTIMER, r16           ; reset read timer
-  std Y+UART_HW_IFACE_OFFS_READBUFPOS_LOW, xl
-  std Y+UART_HW_IFACE_OFFS_READBUFPOS_HIGH, xh
-  ldd r18, Y+UART_HW_IFACE_OFFS_READBUFUSED     ; r18=bytes in buffer
-  inc r18
-  std Y+UART_HW_IFACE_OFFS_READBUFUSED, r18
-  dec r17
-  std Y+UART_HW_IFACE_OFFS_READBUFLEFT, r17
-  breq l_msgFinished_%
-
-  ; check msg size
-  cpi r18, 2                                    ; bytes in buffer, exactly 2?
-  brne l_end_%                                  ; nope, done
-  sbiw xh:xl, 1                                 ; yes, determine message length (msgLen at previous pos)
-  ld r16, X+                                    ; read payload length byte
-  inc r16                                       ; + dest addr
-  inc r16                                       ; + msg length
-  inc r16                                       ; + CRC byte
-  cpi r16, (NET_BUFFERS_SIZE-2)                 ; total msg length ok? (subtract 1 for buffer header byte)
-  brcc l_econtent_%                             ; content error (msg too long)
-  subi r16, 2                                   ; subtract bytes already received
-  std Y+UART_HW_IFACE_OFFS_READBUFLEFT, r16     ; set new number of bytes left
-  brne l_end_%                                  ; jmp if still bytes left to receive
-
-l_msgFinished_%:
-  M_UART_HW_Uart_StopRx @0                ; (R16)
-  ldi r16, NET_IFACE_OFFS_PACKETSIN_LOW
-  ldi r17, UART_HW_READMODE_MSGRECEIVED
-  rjmp l_incCounterAndEnterMode_%
-l_econtent_%:
-  ldi r16, NET_IFACE_OFFS_ERR_CONTENT_LOW
-  rjmp l_incCounterAndEnterSkipping_%
-l_overrun_%:
-  ldi r16, NET_IFACE_OFFS_ERR_NOBUF_LOW
-l_incCounterAndEnterSkipping_%:
-  M_UART_HW_Uart_StopRx @0                ; (R16)
-  ldi r17, UART_HW_READMODE_SKIPPING
-l_incCounterAndEnterMode_%:
-  rcall NET_Interface_IncCounter16              ; (R24, R25)
-  std Y+UART_HW_IFACE_OFFS_READMODE, r17        ; set read mode
-l_end_%:
-.endmacro
-; @end
-
-
-
 ; ---------------------------------------------------------------------------
 ; @macro M_UART_HW_Uart_RxCharFullDuplexIsr
 ;
@@ -324,14 +232,14 @@ l_end_%:
 
 .macro M_UART_HW_Uart_RxCharFullDuplexIsr
   ; check for errors
-  M_IO_READ r16, UCSR@0A                              ; check for errors
+  lds r16, UCSR@0A                              ; check for errors
   andi r16, (1<<FE@0) | (1<<DOR@0) | (1<<UPE@0)
   brne l_hwerr_%
   ; read char
-  M_IO_READ r16, UCSR@0A
+  lds r16, UCSR@0A
   sbrs r16, RXC@0
     rjmp l_end_%                                ; no data
-  M_IO_READ r16, USART@0_DATAREG                                ; r16=received char
+  lds r16, UDR@0                                ; r16=received char
   ; check read mode
   ldd r17, Y+UART_HW_IFACE_OFFS_READMODE
   cpi r17, UART_HW_READMODE_READING
@@ -418,7 +326,7 @@ l_end_%:
 ; @clobbers R16, R17, X
 
 .macro M_UART_HW_Uart_TxUdreIsr
-  M_IO_READ r16, UCSR@0A
+  lds r16, UCSR@0A
   sbrs r16,UDRE@0
     rjmp l_disable_irq_%                       ; not ready
 
@@ -447,7 +355,7 @@ l_end_%:
   std Y+UART_HW_IFACE_OFFS_WRITEBUFLEFT, r17
   
   ; send byte, reset write timer
-  M_IO_WRITE USART@0_DATAREG, r16
+  sts UDR@0, r16
   clr r16
   std Y+NET_IFACE_OFFS_WRITETIMER, r16     ; reset write timer
   
@@ -459,9 +367,9 @@ l_end_%:
 
 l_disable_irq_%:
   ; disable further DRE1 interrupts
-  M_IO_READ r16, UCSR@0B
+  lds r16, UCSR@0B
   cbr r16, (1<<UDRIE@0)                        ; disable TX data register empty interrupt
-  M_IO_WRITE UCSR@0B, r16
+  sts UCSR@0B, r16
 l_end_%:
 .endmacro
 ; @end
@@ -485,9 +393,9 @@ l_end_%:
   brne l_end_%
 
   ; disable further TXC1 interrupts
-  M_IO_READ r16, UCSR@0B
+  lds r16, UCSR@0B
   cbr r16, (1<<TXC@0)                          ; disable TXC1 interrupt
-  M_IO_WRITE UCSR@0B, r16
+  sts UCSR@0B, r16
 
   ; change write mode to WRITEBUFFEREMPTY
   ldi r16, UART_HW_WRITEMODE_WRITEBUFFEREMPTY
diff --git a/avr/modules/uart_hw/ttyonuart1.asm b/avr/modules/uart_hw/ttyonuart1.asm
index 2185ad2..2e436ea 100644
--- a/avr/modules/uart_hw/ttyonuart1.asm
+++ b/avr/modules/uart_hw/ttyonuart1.asm
@@ -9,7 +9,7 @@
 
 
 .equ TTYONUART1_SKIPTIME = 2
-.equ TTYONUART1_MSG_INTERVAL = 0
+.equ TTYONUART1_MSG_INTERVAL = 2
 .equ TTYONUART1_IFACENUM = 2