avr: receiving flash messages basically works.

This commit is contained in:
Martin Preuss
2025-01-22 01:10:32 +01:00
parent 19af9daea7
commit 22a5402141
3 changed files with 16 additions and 6 deletions

View File

@@ -41,6 +41,7 @@ flashDataEnd:
checkFlash:
rcall flashReadUidIntoSdram ; R16, X, Y
rcall ioRawInit ; (R16, R17)
ldi xl, LOW(flashSendBuffer)
ldi xh, HIGH(flashSendBuffer)
rcall flashProcessWriteFlashReady ; (R16, R17, R18, R19, R20, Y, Z)
@@ -83,7 +84,6 @@ flashProcess:
flashProcess_loop1:
; wait up to 10s for incoming FLASH_DATA message
ldi r16, CPRO_CMD_FLASH_DATA
ldi r20, 5 ; wait for 5s (not used!)
rcall ioWaitForGivenMsg ; (r16, r17, r18, r19, r20, r22, X)
brcc flashProcess_end ; no FLASH_DATA or FLASH_END msg
; either FLASH_DATA or FLASH_END received

View File

@@ -22,10 +22,10 @@
; @return CFLAG set if okay (packet received), cleared on error
; @return r16 code of received msg
; @param r16 command to wait for
; @param r20 time in seconds to wait for a message
; @clobbers: r16, r17, r20, X (r18, r19, r22)
ioWaitForGivenMsg:
ldi r20, 100 ; number of tries
ioWaitForGivenMsg_loop:
push r16
rcall ioRawWaitForValidMsg ; (r16, r17, r18, r19, r22, X)

View File

@@ -130,6 +130,10 @@ UART_HW_Uart1_DisableRawRecv:
; @clobbers: r16, r17, r18, r19, r22, X
UART_HW_Uart1_RawRecvPacket:
lds r19, UCSR1A
cbr r19, (1<<FE1) | (1<<DOR1) | (1<<UPE1)
sts UCSR1A, r19 ; clear errors, TODO: flush!!
; wait for data
push r16
mov r16, r18
@@ -155,7 +159,7 @@ UART_HW_Uart1_RawRecvPacket:
rjmp UART_HW_Uart1_RawRecvPacket_error
#endif
UART_HW_Uart1_RawRecvPacket_acceptAddr:
st X+, r16
st X+, r16 ; store destination addr
; read msg length
rcall uartHwUart1RawRecvByte ; (R16, R18, R22)
brcc UART_HW_Uart1_RawRecvPacket_error
@@ -164,7 +168,7 @@ UART_HW_Uart1_RawRecvPacket_acceptAddr:
tst r16
breq UART_HW_Uart1_RawRecvPacket_error
st X+, r16
inc r16
inc r16 ; account for checksum byte
mov r17, r16
; read message content
UART_HW_Uart1_RawRecvPacket_loop:
@@ -192,6 +196,13 @@ UART_HW_Uart1_RawRecvPacket_end:
; @clobbers: r16 (r18, r22)
uartHwUart1RawRecvByte:
; lds r22, UCSR1A
; sbrs r22, RXC1
; rjmp uartHwUart1RawRecvByte
; lds r16, UDR1
; sec
; ret
rcall uartHwUart1RawWaitForByte1ms ; (r18, r22)
brcc uartHwUart1RawRecvByte_error
lds r16, UCSR1A ; check for errors
@@ -201,7 +212,6 @@ uartHwUart1RawRecvByte:
sec
ret
uartHwUart1RawRecvByte_error:
ldi r16, COM2_ERROR_IOERROR
clc
ret
; @end
@@ -264,7 +274,7 @@ uartHwUart1RawWaitForByte100ms:
ldi r18, 100
uartHwUart1RawWaitForByte100ms_loop:
push r18
rcall uartHwUart1RawWaitForByte1ms
rcall uartHwUart1RawWaitForByte1ms ; (r18, r22)
pop r18
brcs uartHwUart1RawWaitForByte100ms_haveByte
dec r18