started working on AtMega8515 module C1.

This commit is contained in:
Martin Preuss
2025-05-17 10:50:09 +02:00
parent 5a46db37c1
commit 21c2c60f4f
29 changed files with 1893 additions and 422 deletions

View File

@@ -33,14 +33,19 @@ ComOnUart0_Init:
rcall comOnUart0SetAttnInput ; (none)
rcall UART_HW_Interface_Init ; (R16, R17, X)
rcall comOnUart0Init ; (R16, R17, X)
rcall comOnUart0Init ; (R16, R17, X)
ldi r16, COMONUART0_IFACENUM
std Y+NET_IFACE_OFFS_IFACENUM, r16
sbi COM_IRQ_ADDR_ATTN, COM_IRQ_BIT_ATTN ; enable pin change irq for ATTN line
in r16, GIMSK ; enable pin change irq PCIE0 or PCIE1
ori r16, (1<<COM_IRQ_GIMSK_ATTN)
out GIMSK, R16
M_IO_READ r16, COM_IRQ_ADDR_ATTN ; enable irq for ATTN line
sbr r16, COM_IRQ_BIT_ATTN
M_IO_WRITE COM_IRQ_ADDR_ATTN, r16
.ifdef COM_IRQ_GIMSK_ATTN
M_IO_READ r16, GIMSK ; enable pin change irq PCIE0 or PCIE1
sbr r16, (1<<COM_IRQ_GIMSK_ATTN)
M_IO_WRITE GIMSK, R16
.endif
ldi r16, (1<<COM_IRQ_GIFR_ATTN) ; clear pending irq by writing 1 to ATTN bit
out GIFR, r16

View File

@@ -120,7 +120,7 @@ l_loop_%:
lds r16, UCSR@0A
sbrs r16, RXC@0
rjmp l_end_%
lds r16, UDR@0
lds r16, USART@0_DATAREG
clr r16
std Y+NET_IFACE_OFFS_READTIMER, r16
rjmp l_loop_%
@@ -146,7 +146,7 @@ l_end_%:
lds r16, UCSR@0A
sbrs r16, RXC@0
rjmp l_end_% ; no data
lds r16, UDR@0 ; r16=received char
lds r16, USART@0_DATAREG ; r16=received char
; check read mode
ldd r17, Y+UART_HW_IFACE_OFFS_READMODE
cpi r17, UART_HW_READMODE_READING
@@ -239,7 +239,7 @@ l_end_%:
lds r16, UCSR@0A
sbrs r16, RXC@0
rjmp l_end_% ; no data
lds r16, UDR@0 ; r16=received char
lds r16, USART@0_DATAREG ; r16=received char
; check read mode
ldd r17, Y+UART_HW_IFACE_OFFS_READMODE
cpi r17, UART_HW_READMODE_READING
@@ -355,7 +355,7 @@ l_end_%:
std Y+UART_HW_IFACE_OFFS_WRITEBUFLEFT, r17
; send byte, reset write timer
sts UDR@0, r16
sts USART@0_DATAREG, r16
clr r16
std Y+NET_IFACE_OFFS_WRITETIMER, r16 ; reset write timer