t03: use new bootloader code.

This commit is contained in:
Martin Preuss
2025-01-19 15:49:18 +01:00
parent 7d33e451cd
commit 0d7aca0060

View File

@@ -6,7 +6,8 @@
; All definitions and changes should go into this file.
; ***************************************************************************
.equ clock=1000000 ; Define the clock frequency
;.equ clock=1000000 ; Define the clock frequency
.equ clock=8000000 ; Define the clock frequency
.nolist
.include "include/tn841def.inc" ; Define device ATtiny841
@@ -111,8 +112,38 @@ firmwareStart: rjmp main ; will be overwritten when flashing
main:
; rjmp debugStop
rjmp bootLoader ; this routine is in modules/flash/proto.asm
cli
; setup stack
.ifdef SPH ; if SPH is defined
ldi r16, High(RAMEND)
out SPH, r16 ; init MSB stack pointer
.endif
ldi r16, Low(RAMEND)
out SPL, r16 ; init LSB stack pointer
#if 1
; start by setting all ports as inputs and enable internal pull-up resistors
ldi r16, 0xff
clr r17
.ifdef PORTA
out DDRA, r17 ; all input
out PORTA, r16 ; enable pull-up on all
.endif
.ifdef PORTB
out DDRB, r17 ; all input
out PORTB, r16 ; enable pull-up on all
.endif
.ifdef PORTC
out DDRC, r17 ; all input
out PORTC, r16 ; enable pull-up on all
.endif
#endif
rcall systemSetSpeed
; rjmp debugUsart2
rjmp bootLoader ; this routine is in modules/flash/bootloader2.asm
@@ -120,26 +151,102 @@ main:
; ***************************************************************************
; includes
.include "modules/uart_bitbang/bytelevel.asm"
.include "modules/uart_bitbang/packetlevel.asm"
;.include "modules/uart_bitbang/bytelevel.asm"
;.include "modules/uart_bitbang/packetlevel.asm"
.include "modules/uart_hw/raw_uart1.asm"
.include "modules/com2/crc.asm"
.include "common/crc8.asm"
.include "common/utils_wait_fixed.asm"
.include "common/utils_copy_from_flash.asm"
.include "common/utils_copy_sdram.asm"
.include "modules/flash/bootloader.asm"
.include "modules/flash/defs.asm"
.include "modules/flash/bootloader2.asm"
.include "modules/flash/io.asm"
.include "modules/flash/io_uart1.asm"
.include "modules/flash/flash.asm"
.include "modules/flash/recv.asm"
.include "modules/flash/send.asm"
.include "modules/flash/flashprocess.asm"
;.include "modules/flash/recv.asm"
;.include "modules/flash/send.asm"
.include "modules/flash/wait.asm"
.include "modules/flash/hdl_flash_start.asm"
.include "modules/flash/hdl_flash_data.asm"
.include "modules/flash/hdl_flash_end.asm"
.include "modules/flash/flash_rsp.asm"
.include "modules/flash/flash_ready.asm"
;.include "modules/flash/hdl_flash_start.asm"
;.include "modules/flash/hdl_flash_data.asm"
;.include "modules/flash/hdl_flash_end.asm"
;include "modules/flash/flash_rsp.asm"
;include "modules/flash/flash_ready.asm"
#if 1
#if 0
debugUsart1:
sbi LED_DDR, LED_PINNUM ; out
cbi LED_PORT, LED_PINNUM ; on
ldi r16, 3 ; (19.2Kb/s at 1MHz)
ldi r17, 0
sts UBRR1H, r17
sts UBRR1L, r16
ldi r16, (3<<UCSZ10)
sts UCSR1C, r16
lds r16, UCSR1B
cbr r16, (1<<UDRIE1) ; disable DRE interrupt
sbr r16, (1<<TXEN1) ; enable transmit
sts UCSR1B, r16
; ldi r16, (1<<UDRE1)
; sts UCSR1A, r16
clr r18
debugUsart1_loop:
debugUsart1_loop2:
lds r16, UCSR1A
sbrs r16,UDRE1
rjmp debugUsart1_loop2
; sbr r16, (1<<TXC1)
; sts UCSR1A, r16
sts UDR1, r18
cpi r18, 10
brne debugUsart1_skipLed
clr r18
rcall debugWaitFor100MilliSecs
sbi LED_PIN, LED_PINNUM ; toggle
debugUsart1_skipLed:
inc r18
rjmp debugUsart1_loop
#endif
debugUsart2:
sbi LED_DDR, LED_PINNUM ; out
cbi LED_PORT, LED_PINNUM ; on
ldi r16, 2 ; (19.2Kb/s at 1MHz)
; ldi r16, 25 ; (19.2Kb/s at 8MHz)
ldi r17, 0
sts UBRR1H, r17
sts UBRR1L, r16
ldi r16, (3<<UCSZ10)
sts UCSR1C, r16
lds r16, UCSR1B
cbr r16, (1<<UDRIE1) ; disable DRE interrupt
sbr r16, (1<<TXEN1) ; enable transmit
sts UCSR1B, r16
ldi xl, LOW(flashSendBuffer)
ldi xh, HIGH(flashSendBuffer)
rcall flashProcessWriteFlashReady ; (R16, R17, R18, R19, R20, Y, Z)
debugUsart2_loop:
rcall flashRawSendMsg ; (r16, r17, X)
rcall debugWaitFor100MilliSecs
sbi LED_PIN, LED_PINNUM ; toggle
rjmp debugUsart2_loop
#if 0
debugStop:
cli
sbi LED_SIMPLE_DDR, LED_SIMPLE_PINNUM ; out
@@ -174,5 +281,38 @@ test1:
rjmp test_loop1
#endif
debugWaitFor100MilliSecs:
ldi r16, 10
debugWaitFor10MilliSecs_loop1:
ldi r17, 100
debugWaitFor10MilliSecs_loop2:
rcall Utils_WaitFor100MicroSecs ; 10ms
dec r17
brne debugWaitFor10MilliSecs_loop2
dec r16
brne debugWaitFor10MilliSecs_loop1
ret
systemSetSpeed:
.if clock == 1000000
ldi r17, 0xd8
ldi r16, (1<<CLKPS1) | (1<<CLKPS0) ; SUT=0, CLKPS=0011b
sts CCP, r17
sts CLKPR, r16
.endif
.if clock == 8000000
ldi r17, 0xd8
clr r16 ; SUT=0, CLKPS=0
sts CCP, r17
sts CLKPR, r16
.endif
ret