avr: bootloader partially works now but stops after 3 messages...

avr/modules/flash/io_bitbang.asm

@@ -0,0 +1,87 @@
+; ***************************************************************************
+; copyright   : (C) 2025 by Martin Preuss
+; email       : martin@libchipcard.de
+;
+; ***************************************************************************
+; * This file is part of the project "AqHome".                              *
+; * Please see toplevel file COPYING of that project for license details.   *
+; ***************************************************************************
+
+
+; ***************************************************************************
+; code
+
+.cseg
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawInit
+; Init raw message subsystem.
+;
+; @clobbers none
+
+ioRawInit:
+  ; setup pins and interrupts
+  cbi COM_DATA_DDR, COM_DATA_PIN          ; set DATA port as input
+  cbi COM_DATA_OUTPUT, COM_DATA_PIN       ; disable internal pullup for TXD
+
+  cbi COM_ATTN_DDR, COM_ATTN_PIN          ; set ATTN port as input
+  cbi COM_ATTN_OUTPUT, COM_ATTN_PIN       ; disable internal pullup for ATTN
+  ret
+;@end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawSendMsg
+; Send a message
+;
+; @clobbers X (R16, R17, R21, R22)
+
+ioRawSendMsg:
+ioRawSendMsg_loop:
+    ldi r16, 0xff                        ; expect ATTN high
+    ldi r17, 3
+    rcall ioWaitForAttnState100ms     ; wait for up to 300ms
+    brcs ioRawSendMsg_attnHigh
+    ret
+ioRawSendMsg_attnHigh:
+    ldi xl, LOW(flashSendBuffer)
+    ldi xh, HIGH(flashSendBuffer)
+    rcall uartBitbang_SendPacket          ; R16, R22 (R17, R21, X)
+  brcc ioRawSendMsg_loop
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawWaitForValidMsg
+; Wait for valid incoming msg
+;
+; @return CFLAG set if okay (packet received), cleared on error
+; @clobbers: 
+
+ioRawWaitForValidMsg:
+  ldi r16, 0                           ; expect ATTN low
+  ldi r17, 100
+  rcall ioWaitForAttnState100ms     ; wait for up to 10s
+  brcs ioRawWaitForValidMsg_attnLow
+  ret
+ioRawWaitForValidMsg_attnLow:
+  ldi xl, LOW(flashRecvBuffer)
+  ldi xh, HIGH(flashRecvBuffer)
+  ldi r16, COM2_MAINTENANCE_ADDR
+  ldi r17, FLASH_RECVBUFFER_MAXLEN-3
+  rcall uartBitbang_ReceivePacketIntoBuffer
+  brcs ioRawWaitForValidMsg_packetReceived
+  ret
+ioRawWaitForValidMsg_packetReceived:
+  ldi r16, 0xff                        ; expect ATTN high
+  ldi r17, 100
+  rjmp ioWaitForAttnState100ms      ; wait for up to 10s
+; @end
+
+
+