313 lines
10 KiB
PHP
Executable File
313 lines
10 KiB
PHP
Executable File
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
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;***** Created: 2011-02-09 12:04 ******* Source: ATtiny28.xml ************
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;*************************************************************************
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;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
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;*
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;* Number : AVR000
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;* File Name : "tn28def.inc"
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;* Title : Register/Bit Definitions for the ATtiny28
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;* Date : 2011-02-09
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;* Version : 2.35
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;* Support E-mail : avr@atmel.com
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;* Target MCU : ATtiny28
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;*
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;* DESCRIPTION
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;* When including this file in the assembly program file, all I/O register
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;* names and I/O register bit names appearing in the data book can be used.
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;* In addition, the six registers forming the three data pointers X, Y and
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;* Z have been assigned names XL - ZH. Highest RAM address for Internal
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;* SRAM is also defined
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;*
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;* The Register names are represented by their hexadecimal address.
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;*
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;* The Register Bit names are represented by their bit number (0-7).
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;*
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;* Please observe the difference in using the bit names with instructions
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;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
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;* (skip if bit in register set/cleared). The following example illustrates
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;* this:
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;*
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;* in r16,PORTB ;read PORTB latch
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;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
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;* out PORTB,r16 ;output to PORTB
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;*
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;* in r16,TIFR ;read the Timer Interrupt Flag Register
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;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
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;* rjmp TOV0_is_set ;jump if set
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;* ... ;otherwise do something else
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;*************************************************************************
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#ifndef _TN28DEF_INC_
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#define _TN28DEF_INC_
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#pragma partinc 0
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; ***** SPECIFY DEVICE ***************************************************
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.device ATtiny28
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#pragma AVRPART ADMIN PART_NAME ATtiny28
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.equ SIGNATURE_000 = 0x1e
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.equ SIGNATURE_001 = 0x91
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.equ SIGNATURE_002 = 0x07
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#pragma AVRPART CORE CORE_VERSION V0E
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; ***** I/O REGISTER DEFINITIONS *****************************************
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; NOTE:
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; Definitions marked "MEMORY MAPPED"are extended I/O ports
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; and cannot be used with IN/OUT instructions
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.equ SREG = 0x3f
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.equ PORTA = 0x1b
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.equ PACR = 0x1a
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.equ PINA = 0x19
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.equ PINB = 0x16
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.equ PORTD = 0x12
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.equ DDRD = 0x11
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.equ PIND = 0x10
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.equ ACSR = 0x08
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.equ MCUCS = 0x07
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.equ ICR = 0x06
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.equ IFR = 0x05
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.equ TCCR0 = 0x04
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.equ TCNT0 = 0x03
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.equ MODCR = 0x02
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.equ WDTCR = 0x01
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.equ OSCCAL = 0x00
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; ***** BIT DEFINITIONS **************************************************
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; ***** PORTD ************************
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; PORTD - Port D Data Register
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.equ PORTD0 = 0 ; Port D Data Register bit 0
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.equ PD0 = 0 ; For compatibility
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.equ PORTD1 = 1 ; Port D Data Register bit 1
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.equ PD1 = 1 ; For compatibility
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.equ PORTD2 = 2 ; Port D Data Register bit 2
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.equ PD2 = 2 ; For compatibility
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.equ PORTD3 = 3 ; Port D Data Register bit 3
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.equ PD3 = 3 ; For compatibility
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.equ PORTD4 = 4 ; Port D Data Register bit 4
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.equ PD4 = 4 ; For compatibility
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.equ PORTD5 = 5 ; Port D Data Register bit 5
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.equ PD5 = 5 ; For compatibility
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.equ PORTD6 = 6 ; Port D Data Register bit 6
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.equ PD6 = 6 ; For compatibility
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.equ PORTD7 = 7 ; Port D Data Register bit 7
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.equ PD7 = 7 ; For compatibility
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; DDRD - Port D Data Direction Register
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.equ DDD0 = 0 ; Port D Data Direction Register bit 0
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.equ DDD1 = 1 ; Port D Data Direction Register bit 1
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.equ DDD2 = 2 ; Port D Data Direction Register bit 2
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.equ DDD3 = 3 ; Port D Data Direction Register bit 3
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.equ DDD4 = 4 ; Port D Data Direction Register bit 4
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.equ DDD5 = 5 ; Port D Data Direction Register bit 5
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.equ DDD6 = 6 ; Port D Data Direction Register bit 6
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.equ DDD7 = 7 ; Port D Data Direction Register bit 7
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; PIND - Port D Input Pins
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.equ PIND0 = 0 ; Port D Input Pins bit 0
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.equ PIND1 = 1 ; Port D Input Pins bit 1
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.equ PIND2 = 2 ; Port D Input Pins bit 2
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.equ PIND3 = 3 ; Port D Input Pins bit 3
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.equ PIND4 = 4 ; Port D Input Pins bit 4
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.equ PIND5 = 5 ; Port D Input Pins bit 5
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.equ PIND6 = 6 ; Port D Input Pins bit 6
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.equ PIND7 = 7 ; Port D Input Pins bit 7
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; ***** CPU **************************
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; SREG - Status Register
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.equ SREG_C = 0 ; Carry Flag
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.equ SREG_Z = 1 ; Zero Flag
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.equ SREG_N = 2 ; Negative Flag
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.equ SREG_V = 3 ; Two's Complement Overflow Flag
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.equ SREG_S = 4 ; Sign Bit
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.equ SREG_H = 5 ; Half Carry Flag
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.equ SREG_T = 6 ; Bit Copy Storage
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.equ SREG_I = 7 ; Global Interrupt Enable
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; ICR - Interrupt Control Register
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.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0
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.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1
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.equ ICS10 = 2 ; Interrupt Sense Control 1 bit 0
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.equ ICS11 = 3 ; Interrupt Sense Control 1 bit 1
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; MCUCS - MCU Control and Status Register
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.equ PORF = 0 ; Power-On Reset Flag
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.equ EXTRF = 1 ; External Reset Flag
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.equ WDRF = 3 ; Watchdog Reset Flag
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.equ SM = 4 ; Sleep Mode
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.equ SE = 5 ; Sleep Enable
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.equ PLUPB = 7 ; Pull-up Enable Port B
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; OSCCAL - Status Register
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.equ CAL0 = 0 ; Oscillator Calibration Value Bit 0
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.equ CAL1 = 1 ; Oscillator Calibration Value Bit 1
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.equ CAL2 = 2 ; Oscillator Calibration Value Bit 2
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.equ CAL3 = 3 ; Oscillator Calibration Value Bit 3
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.equ CAL4 = 4 ; Oscillator Calibration Value Bit 4
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.equ CAL5 = 5 ; Oscillator Calibration Value Bit 5
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.equ CAL6 = 6 ; Oscillator Calibration Value Bit 6
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.equ CAL7 = 7 ; Oscillator Calibration Value Bit 7
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; ***** ANALOG_COMPARATOR ************
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; ACSR - Analog Comparator Control And Status Register
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.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
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.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
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.equ ACIE = 3 ; Analog Comparator Interrupt Enable
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.equ ACI = 4 ; Analog Comparator Interrupt Flag
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.equ ACO = 5 ; Analog Comparator Output
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.equ ACD = 7 ; Analog Comparator Disable
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; ***** TIMER_COUNTER_0 **************
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; ICR - Interrupt Control Register
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.equ TOIE0 = 4 ; Timer/Counter0 Overflow Interrupt Enable
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; IFR - Interrupt Flag register
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.equ TOV0 = 4 ; Timer/Counter0 Overflow Flag
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; TCCR0 - Timer/Counter0 Control Register
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.equ CS00 = 0 ; Clock Select0 bit 0
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.equ CS01 = 1 ; Clock Select0 bit 1
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.equ CS02 = 2 ; Clock Select0 bit 2
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.equ OOM00 = 3 ; Overflow Output Mode, Bit 0
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.equ OOM01 = 4 ; Overflow Output Mode, Bit 1
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.equ FOV0 = 7 ; Force Overflow
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; TCNT0 - Timer Counter 0
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.equ TCNT00 = 0 ; Timer Counter 0 bit 0
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.equ TCNT01 = 1 ; Timer Counter 0 bit 1
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.equ TCNT02 = 2 ; Timer Counter 0 bit 2
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.equ TCNT03 = 3 ; Timer Counter 0 bit 3
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.equ TCNT04 = 4 ; Timer Counter 0 bit 4
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.equ TCNT05 = 5 ; Timer Counter 0 bit 5
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.equ TCNT06 = 6 ; Timer Counter 0 bit 6
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.equ TCNT07 = 7 ; Timer Counter 0 bit 7
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; ***** WATCHDOG *********************
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; WDTCR - Watchdog Timer Control Register
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.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
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.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
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.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
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.equ WDE = 3 ; Watch Dog Enable
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.equ WDTOE = 4 ; RW
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.equ WDDE = WDTOE ; For compatibility
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; ***** EXTERNAL_INTERRUPT ***********
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; ICR - Interrupt Control Register
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.equ LLIE = 5 ; Low-level Input Interrupt Enable
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.equ INT0 = 6 ; External Interrupt Request 0 Enable
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.equ INT1 = 7 ; External Interrupt Request 1 Enable
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; IFR - Interrupt Flag register
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.equ INTF0 = 6 ; External Interrupt Flag 0
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.equ INTF1 = 7 ; External Interrupt Flag 1
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; ***** PORTA ************************
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; PORTA - Port A Data Register
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.equ PORTA0 = 0 ; Port A Data Register bit 0
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.equ PA0 = 0 ; For compatibility
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.equ PORTA1 = 1 ; Port A Data Register bit 1
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.equ PA1 = 1 ; For compatibility
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.equ PORTA2 = 2 ; Port A Data Register bit 2
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.equ PA2 = 2 ; For compatibility
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.equ PORTA3 = 3 ; Port A Data Register bit 3
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.equ PA3 = 3 ; For compatibility
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; PACR - Port A Control Register
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.equ DDA0 = 0 ; Data Direction Port A, bit 0
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.equ DDA1 = 1 ; Data Direction Port A, bit 1
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.equ PA2HC = 2 ; PORTA2 High Current Enable
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.equ DDA3 = 3 ; Data Direction Port A, bit 3
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; PINA - Port A Input Pins
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.equ PINA0 = 0 ; Input Pins, Port A bit 0
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.equ PINA1 = 1 ; Input Pins, Port A bit 1
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.equ PINA3 = 3 ; Input Pins, Port A bit 3
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; ***** PORTB ************************
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; PINB - Port B Input Pins
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.equ PINB0 = 0 ; Port B Input Pins bit 0
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.equ PINB1 = 1 ; Port B Input Pins bit 1
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.equ PINB2 = 2 ; Port B Input Pins bit 2
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.equ PINB3 = 3 ; Port B Input Pins bit 3
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.equ PINB4 = 4 ; Port B Input Pins bit 4
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.equ PINB5 = 5 ; Port B Input Pins bit 5
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.equ PINB6 = 6 ; Port B Input Pins bit 6
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.equ PINB7 = 7 ; Port B Input Pins bit 7
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; ***** MODULATOR ********************
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; MODCR - Modulation Control Register
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.equ MCONF0 = 0 ; Modulation Configuration Bit 0
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.equ MCONF1 = 1 ; Modulation Configuration Bit 1
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.equ MCONF2 = 2 ; Modulation Configuration Bit 2
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.equ ONTIM0 = 3 ; Modulation On-time Bit 0
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.equ ONTIM1 = 4 ; Modulation On-time Bit 1
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.equ ONTIM2 = 5 ; Modulation On-time Bit 2
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.equ OTIM3 = 6 ; Modulation On-time Bit 3
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.equ ONTIM4 = 7 ; Modulation On-time Bit 4
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; ***** LOCKSBITS ********************************************************
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.equ LB1 = 0 ; Lockbit
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.equ LB2 = 1 ; Lockbit
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; ***** FUSES ************************************************************
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; LOW fuse bits
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; ***** CPU REGISTER DEFINITIONS *****************************************
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.def XH = r27
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.def XL = r26
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.def YH = r29
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.def YL = r28
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.def ZH = r31
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.def ZL = r30
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; ***** DATA MEMORY DECLARATIONS *****************************************
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.equ FLASHEND = 0x03ff ; Note: Word address
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.equ IOEND = 0x003f
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.equ SRAM_SIZE = 0
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.equ RAMEND = 0x0000
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.equ XRAMEND = 0x0000
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.equ E2END = 0x0000
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.equ EEPROMEND = 0x0000
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#pragma AVRPART MEMORY PROG_FLASH 2048
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#pragma AVRPART MEMORY EEPROM 0
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#pragma AVRPART MEMORY INT_SRAM SIZE 0
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#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x0
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; ***** INTERRUPT VECTORS ************************************************
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.equ INT0addr = 0x0001 ; External Interrupt 0
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.equ INT1addr = 0x0002 ; External Interrupt 1
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.equ LLINTaddr = 0x0003 ; Low-level Input on Port B
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.equ OVF0addr = 0x0004 ; Timer/Counter0 Overflow
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.equ ACIaddr = 0x0005 ; Analog Comparator
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.equ INT_VECTORS_SIZE = 6 ; size in words
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#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
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#endif /* _TN28DEF_INC_ */
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; ***** END OF FILE ******************************************************
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