376 lines
12 KiB
PHP
Executable File
376 lines
12 KiB
PHP
Executable File
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
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;***** Created: 2011-02-09 12:04 ******* Source: ATtiny9.xml *************
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;*************************************************************************
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;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
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;*
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;* Number : AVR000
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;* File Name : "tn9def.inc"
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;* Title : Register/Bit Definitions for the ATtiny9
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;* Date : 2011-02-09
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;* Version : 2.35
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;* Support E-mail : avr@atmel.com
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;* Target MCU : ATtiny9
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;*
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;* DESCRIPTION
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;* When including this file in the assembly program file, all I/O register
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;* names and I/O register bit names appearing in the data book can be used.
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;* In addition, the six registers forming the three data pointers X, Y and
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;* Z have been assigned names XL - ZH. Highest RAM address for Internal
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;* SRAM is also defined
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;*
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;* The Register names are represented by their hexadecimal address.
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;*
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;* The Register Bit names are represented by their bit number (0-7).
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;*
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;* Please observe the difference in using the bit names with instructions
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;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
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;* (skip if bit in register set/cleared). The following example illustrates
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;* this:
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;*
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;* in r16,PORTB ;read PORTB latch
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;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
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;* out PORTB,r16 ;output to PORTB
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;*
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;* in r16,TIFR ;read the Timer Interrupt Flag Register
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;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
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;* rjmp TOV0_is_set ;jump if set
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;* ... ;otherwise do something else
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;*************************************************************************
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#ifndef _TN9DEF_INC_
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#define _TN9DEF_INC_
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#pragma partinc 0
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; ***** SPECIFY DEVICE ***************************************************
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.device ATtiny9
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#pragma AVRPART ADMIN PART_NAME ATtiny9
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.equ SIGNATURE_000 = 0x1e
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.equ SIGNATURE_001 = 0x90
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.equ SIGNATURE_002 = 0x08
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#pragma AVRPART CORE CORE_VERSION AVR8L_0
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; ***** I/O REGISTER DEFINITIONS *****************************************
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; NOTE:
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; Definitions marked "MEMORY MAPPED"are extended I/O ports
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; and cannot be used with IN/OUT instructions
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.equ SREG = 0x3f
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.equ SPL = 0x3d
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.equ SPH = 0x3e
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.equ CCP = 0x3c
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.equ RSTFLR = 0x3b
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.equ SMCR = 0x3a
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.equ OSCCAL = 0x39
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.equ CLKMSR = 0x37
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.equ CLKPSR = 0x36
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.equ PRR = 0x35
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.equ VLMCSR = 0x34
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.equ NVMCMD = 0x33
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.equ NVMCSR = 0x32
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.equ WDTCSR = 0x31
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.equ GTCCR = 0x2f
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.equ TCCR0A = 0x2e
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.equ TCCR0B = 0x2d
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.equ TCCR0C = 0x2c
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.equ TIMSK0 = 0x2b
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.equ TIFR0 = 0x2a
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.equ TCNT0L = 0x28
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.equ TCNT0H = 0x29
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.equ OCR0AL = 0x26
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.equ OCR0AH = 0x27
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.equ OCR0BL = 0x24
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.equ OCR0BH = 0x25
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.equ ICR0L = 0x22
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.equ ICR0H = 0x23
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.equ ACSR = 0x1f
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.equ DIDR0 = 0x17
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.equ EICRA = 0x15
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.equ EIFR = 0x14
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.equ EIMSK = 0x13
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.equ PCICR = 0x12
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.equ PCIFR = 0x11
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.equ PCMSK = 0x10
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.equ PORTCR = 0x0c
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.equ PUEB = 0x03
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.equ PORTB = 0x02
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.equ DDRB = 0x01
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.equ PINB = 0x00
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; ***** BIT DEFINITIONS **************************************************
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; ***** ANALOG_COMPARATOR ************
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; ACSR - Analog Comparator Control And Status Register
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.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
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.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
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.equ ACIC = 2 ; Analog Comparator Input Capture Enable
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.equ ACIE = 3 ; Analog Comparator Interrupt Enable
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.equ ACI = 4 ; Analog Comparator Interrupt Flag
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.equ ACO = 5 ; Analog Compare Output
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.equ ACD = 7 ; Analog Comparator Disable
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; DIDR0 -
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.equ AIN0D = 0 ; AIN0 Digital Input Disable
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.equ AIN1D = 1 ; AIN1 Digital Input Disable
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; ***** CPU **************************
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; CCP - Configuration Change Protection
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.equ CCP0 = 0 ; Configuration Change Protection bit 0
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.equ CCP1 = 1 ; Configuration Change Protection bit 1
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.equ CCP2 = 2 ; Configuration Change Protection bit 2
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.equ CCP3 = 3 ; Configuration Change Protection bit 3
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.equ CCP4 = 4 ; Configuration Change Protection bit 4
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.equ CCP5 = 5 ; Configuration Change Protection bit 5
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.equ CCP6 = 6 ; Configuration Change Protection bit 6
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.equ CCP7 = 7 ; Configuration Change Protection bit 7
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; SREG - Status Register
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.equ SREG_C = 0 ; Carry Flag
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.equ SREG_Z = 1 ; Zero Flag
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.equ SREG_N = 2 ; Negative Flag
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.equ SREG_V = 3 ; Two's Complement Overflow Flag
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.equ SREG_S = 4 ; Sign Bit
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.equ SREG_H = 5 ; Half Carry Flag
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.equ SREG_T = 6 ; Bit Copy Storage
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.equ SREG_I = 7 ; Global Interrupt Enable
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; CLKMSR - Clock Main Settings Register
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.equ CLKMS0 = 0 ; Clock Main Select Bit 0
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.equ CLKMS1 = 1 ; Clock Main Select Bit 1
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; CLKPSR - Clock Prescale Register
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.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0
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.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1
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.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2
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.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3
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; OSCCAL - Oscillator Calibration Value
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.equ CAL0 = 0 ; Oscillator Calibration Value Bit0
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.equ CAL1 = 1 ; Oscillator Calibration Value Bit1
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.equ CAL2 = 2 ; Oscillator Calibration Value Bit2
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.equ CAL3 = 3 ; Oscillator Calibration Value Bit3
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.equ CAL4 = 4 ; Oscillator Calibration Value Bit4
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.equ CAL5 = 5 ; Oscillator Calibration Value Bit5
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.equ CAL6 = 6 ; Oscillator Calibration Value Bit6
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.equ CAL7 = 7 ; Oscillator Calibration Value Bit7
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; SMCR - Sleep Mode Control Register
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.equ SE = 0 ; Sleep Enable
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.equ SM0 = 1 ; Sleep Mode Select Bit 0
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.equ SM1 = 2 ; Sleep Mode Select Bit 1
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.equ SM2 = 3 ; Sleep Mode Select Bit 2
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; PRR - Power Reduction Register
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.equ PRTIM0 = 0 ; Power Reduction Timer/Counter0
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.equ PRADC = 1 ; Power Reduction ADC
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; VLMCSR - Vcc Level Monitoring Control and Status Register
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.equ VLM0 = 0 ; Trigger Level of Voltage Level Monitor bit 0
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.equ VLM1 = 1 ; Trigger Level of Voltage Level Monitor bit 1
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.equ VLM2 = 2 ; Trigger Level of Voltage Level Monitor bit 2
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.equ VLMIE = 6 ; VLM Interrupt Enable
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.equ VLMF = 7 ; VLM Flag
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; RSTFLR - Reset Flag Register
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.equ PORF = 0 ; Power-on Reset Flag
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.equ EXTRF = 1 ; External Reset Flag
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.equ WDRF = 3 ; Watchdog Reset Flag
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; NVMCSR - Non-Volatile Memory Control and Status Register
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.equ NVMBSY = 7 ; Non-Volatile Memory Busy
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; NVMCMD - Non-Volatile Memory Command
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.equ NVMCMD0 = 0 ;
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.equ NVMCMD1 = 1 ;
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.equ NVMCMD2 = 2 ;
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.equ NVMCMD3 = 3 ;
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.equ NVMCMD4 = 4 ;
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.equ NVMCMD5 = 5 ;
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; ***** PORTB ************************
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; PORTCR - Port Control Register
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.equ BBMB = 1 ; Break-Before-Make Mode Enable
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; PUEB - Pull-up Enable Control Register
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.equ PUEB0 = 0 ;
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.equ PUEB1 = 1 ;
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.equ PUEB2 = 2 ;
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.equ PUEB3 = 3 ;
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; PORTB - Input Pins, Port B
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.equ PORTB0 = 0 ;
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.equ PB0 = 0 ; For compatibility
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.equ PORTB1 = 1 ;
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.equ PB1 = 1 ; For compatibility
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.equ PORTB2 = 2 ;
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.equ PB2 = 2 ; For compatibility
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.equ PORTB3 = 3 ;
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.equ PB3 = 3 ; For compatibility
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; DDRB - Data Direction Register, Port B
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.equ DDB0 = 0 ;
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.equ DDB1 = 1 ;
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.equ DDB2 = 2 ;
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.equ DDB3 = 3 ;
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; PINB - Port B Data register
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.equ PINB0 = 0 ;
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.equ PINB1 = 1 ;
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.equ PINB2 = 2 ;
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.equ PINB3 = 3 ;
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; ***** EXTERNAL_INTERRUPT ***********
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; EICRA - External Interrupt Control Register A
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.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0
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.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1
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; EIMSK - External Interrupt Mask register
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.equ INT0 = 0 ; External Interrupt Request 0 Enable
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; EIFR - External Interrupt Flag register
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.equ INTF0 = 0 ; External Interrupt Flag 0
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; PCICR - Pin Change Interrupt Control Register
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.equ PCIE0 = 0 ; Pin Change Interrupt Enable 0
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; PCIFR - Pin Change Interrupt Flag Register
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.equ PCIF0 = 0 ; Pin Change Interrupt Flag 0
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; PCMSK - Pin Change Mask Register
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.equ PCINT0 = 0 ; Pin Change Enable Mask 0
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.equ PCINT1 = 1 ; Pin Change Enable Mask 1
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.equ PCINT2 = 2 ; Pin Change Enable Mask 2
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.equ PCINT3 = 3 ; Pin Change Enable Mask 3
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; ***** TIMER_COUNTER_0 **************
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; TCCR0A - Timer/Counter 0 Control Register A
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.equ WGM00 = 0 ; Waveform Generation Mode
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.equ WGM01 = 1 ; Waveform Generation Mode
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.equ COM0B0 = 4 ; Compare Output Mode for Channel B bit 0
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.equ COM0B1 = 5 ; Compare Output Mode for Channel B bit 1
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.equ COM0A0 = 6 ; Compare Output Mode for Channel A bit 0
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.equ COM0A1 = 7 ; Compare Output Mode for Channel A bit 1
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; TCCR0B - Timer/Counter 0 Control Register B
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.equ CS00 = 0 ; Clock Select
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.equ CS01 = 1 ; Clock Select
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.equ CS02 = 2 ; Clock Select
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.equ WGM02 = 3 ; Waveform Generation Mode
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.equ WGM03 = 4 ; Waveform Generation Mode
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.equ ICES0 = 6 ; Input Capture Edge Select
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.equ ICNC0 = 7 ; Input Capture Noise Canceler
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; TCCR0C - Timer/Counter 0 Control Register C
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.equ FOC0B = 6 ; Force Output Compare for Channel B
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.equ FOC0A = 7 ; Force Output Compare for Channel A
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; TIMSK0 - Timer Interrupt Mask Register 0
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.equ TOIE0 = 0 ; Overflow Interrupt Enable
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.equ OCIE0A = 1 ; Output Compare A Match Interrupt Enable
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.equ OCIE0B = 2 ; Output Compare B Match Interrupt Enable
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.equ ICIE0 = 5 ; Input Capture Interrupt Enable
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; TIFR0 - Overflow Interrupt Enable
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.equ TOV0 = 0 ; Timer Overflow Flag
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.equ OCF0A = 1 ; Timer Output Compare Flag 0A
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.equ OCF0B = 2 ; Timer Output Compare Flag 0B
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.equ ICF0 = 5 ; Input Capture Flag
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; GTCCR - General Timer/Counter Control Register
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.equ PSR = 0 ; Prescaler Reset
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.equ TSM = 7 ; Timer Synchronization Mode
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; ***** WATCHDOG *********************
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; WDTCSR - Watchdog Timer Control and Status Register
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.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
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.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
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.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
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.equ WDE = 3 ; Watch Dog Enable
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.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3
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.equ WDIE = 6 ; Watchdog Timer Interrupt Enable
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.equ WDIF = 7 ; Watchdog Timer Interrupt Flag
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; ***** LOCKSBITS ********************************************************
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.equ LB1 = 0 ; Lockbit
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.equ LB2 = 1 ; Lockbit
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; ***** FUSES ************************************************************
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; BYTE0 fuse bits
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.equ RSTDISBL = 0 ; Disable external reset
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.equ WDTON = 1 ; Watch dog timer always on
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.equ CKOUT = 2 ; Output external clock
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; ***** CPU REGISTER DEFINITIONS *****************************************
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.def XH = r27
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.def XL = r26
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.def YH = r29
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.def YL = r28
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.def ZH = r31
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.def ZL = r30
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; ***** DATA MEMORY DECLARATIONS *****************************************
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.equ FLASHEND = 0x01ff ; Note: Word address
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.equ IOEND = 0x003f
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.equ SRAM_START = 0x0040
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.equ SRAM_SIZE = 32
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.equ RAMEND = 0x005f
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.equ XRAMEND = 0x0000
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.equ E2END = 0x0000
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.equ EEPROMEND = 0x0000
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; ***** MEMORY MAPPED NVM ************************************************
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.equ MAPPED_FLASH_START = 0x4000
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.equ MAPPED_LOCKBITS_0 = 0x3f00
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.equ MAPPED_CONFIG_0 = 0x3f40
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.equ MAPPED_CALIB_0 = 0x3f80
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.equ MAPPED_SIGN_0 = 0x3fc0
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.equ MAPPED_SIGN_1 = 0x3fc1
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.equ MAPPED_SIGN_2 = 0x3fc2
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.equ MAPPED_FLASH_SIZE = 0x0400
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.equ MAPPED_FLASH_END = 0x43ff
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#pragma AVRPART MEMORY PROG_FLASH 1024
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#pragma AVRPART MEMORY EEPROM 0
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#pragma AVRPART MEMORY INT_SRAM SIZE 32
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#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x40
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; ***** BOOTLOADER DECLARATIONS ******************************************
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.equ PAGESIZE = 16
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; ***** INTERRUPT VECTORS ************************************************
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.equ INT0addr = 0x0001 ; External Interrupt Request 0
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.equ PCI0addr = 0x0002 ; Pin Change Interrupt Request 0
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.equ ICP0addr = 0x0003 ; Timer/Counter0 Input Capture
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.equ OVF0addr = 0x0004 ; Timer/Counter0 Overflow
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.equ OC0Aaddr = 0x0005 ; Timer/Counter Compare Match A
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.equ OC0Baddr = 0x0006 ; Timer/Counter Compare Match B
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.equ ACIaddr = 0x0007 ; Analog Comparator
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.equ WDTaddr = 0x0008 ; Watchdog Time-out
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.equ VLMaddr = 0x0009 ; Vcc Voltage Level Monitor
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.equ INT_VECTORS_SIZE = 10 ; size in words
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#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
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#endif /* _TN9DEF_INC_ */
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; ***** END OF FILE ******************************************************
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