392 lines
8.5 KiB
NASM
392 lines
8.5 KiB
NASM
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; ***************************************************************************
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; macros
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; ---------------------------------------------------------------------------
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; Utils_WaitNanoSecs waittime_in_ns , cyles_already_used , waitcount_register
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;
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; cycles already used will be subtracted from the delay
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; the waittime resolution is 1 cycle (delay from exact to +1 cycle)
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; the maximum delay at 20MHz (50ns/clock) is 38350ns
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; waitcount register must specify an immediate register
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; taken from https://www.mikrocontroller.net/articles/AVR_Assembler_Makros#Verz%C3%B6gerung_um_X_Nanosekunden
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;
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.set Osc_Hz = clock ; 1 MHz
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.set cycle_time_ns = (1000000000 / Osc_Hz) ; clock duration
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.macro Utils_WaitNanoSecs
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.set cycles = ((@0 + cycle_time_ns - 1) / cycle_time_ns - @1)
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.if (cycles > (255 * 3 + 2))
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.error "MACRO Utils_WaitNanoSecs - too many cycles to burn"
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.else
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.if (cycles > 6)
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.set loop_cycles = (cycles / 3)
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ldi @2,loop_cycles
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dec @2
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brne pc-1
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.set cycles = (cycles - (loop_cycles * 3))
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.endif
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.if (cycles > 0)
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.if (cycles & 4)
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rjmp pc+1
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rjmp pc+1
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.endif
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.if (cycles & 2)
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rjmp pc+1
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.endif
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.if (cycles & 1)
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nop
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.endif
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.endif
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.endif
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.endmacro
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; ***************************************************************************
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; data
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.dseg
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utilsDataBegin:
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utilsSeed: .byte 2
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utilsDataEnd:
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; ***************************************************************************
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; code
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.cseg
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utilsDateString: .db "%YEAR%-%MONTH%-%DAY%-%HOUR%:%MINUTE%", 0, 0
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; ---------------------------------------------------------------------------
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; Utils_Init
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;
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; IN:
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; OUT:
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; - CFLAG: set if okay, clear on error
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; USED: R16, R17, R18, X, Y
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Utils_Init:
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; preset SRAM data area
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ldi xh, HIGH(utilsDataBegin)
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ldi xl, LOW(utilsDataBegin)
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clr r16
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ldi r17, (utilsDataEnd-utilsDataBegin)
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rcall Utils_FillSram
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; generate initial seed from compile date string
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ldi zl, LOW(utilsDateString*2)
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ldi zh, HIGH(utilsDateString*2)
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ldi r18, 0xe1
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ldi r19, 0xac
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Utils_Init_l1:
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lpm r16, Z+
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tst r16
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breq Utils_Init_l2
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eor r18, r16
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lsl r18
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rol r19
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rjmp Utils_Init_l1
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Utils_Init_l2:
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sts utilsSeed, r18
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sts utilsSeed+1, r19
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sec
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ret
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; ---------------------------------------------------------------------------
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; Utils_Fini
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;
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; IN:
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; OUT:
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; - CFLAG: set if okay, clear on error
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; USED: R16, R17, R18, X, Y
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Utils_Fini:
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sec
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ret
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; ---------------------------------------------------------------------------
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; Utils_FillSram
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;
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; IN:
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; - x: pointer to SRAM to fill
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; - r16: value to fill the SRAM with
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; - r17: size of area to fill
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; OUT:
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; - nothing
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; MODIFIED REGISTERS: r17, x
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Utils_FillSram:
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tst r17
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breq Utils_FillSram_end
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Utils_FillSram_loop:
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st x+, r16
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dec r17
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brne Utils_FillSram_loop
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Utils_FillSram_end:
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ret
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#if 0
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; ---------------------------------------------------------------------------
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; Increment a 32 bit counter at the address given by X.
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; IN:
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; - X: Address of the 4 byte counter (1. byte is LSB)
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; OUT:
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; - nothing
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; MODIFIED REGISTERS: r18, r19, r20, r21, 22
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Utils_IncrementCounter32:
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ld r18, x+
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ld r19, x+
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ld r20, x+
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ld r21, x
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ldi r22, 1
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add r18, r22
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clr r22 ; doesn't affect carry flag
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adc r19, r22
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adc r20, r22
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adc r21, r22
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st x, r21
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st -x, r20
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st -x, r19
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st -x, r18
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ret
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#endif
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; ---------------------------------------------------------------------------
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; Increment a 16 bit counter at the address given by X.
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; IN:
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; - X: Address of the 2 byte counter (1. byte is LSB)
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; OUT:
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; - nothing
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; MODIFIED REGISTERS: r18, r19, 22
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Utils_IncrementCounter16:
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ld r18, x+
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ld r19, x
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ldi r22, 1
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add r18, r22
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clr r22 ; doesn't affect carry flag
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adc r19, r22
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st x, r19
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st -x, r18
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ret
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; ---------------------------------------------------------------------------
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; Utils_ReadEeprom
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;
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; Read a byte from EEPROM (see example in ATtiny24/44/84 manual p.19).
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;
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; IN:
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; - X: EEPROM Address to read from
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; OUT:
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; - R16: byte read
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; MODIFIED REGISTERS: R16
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Utils_ReadEeprom:
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sbic EECR, EEPE ; wait for previous write to complete (if any)
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rjmp Utils_ReadEeprom
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out EEARH, xh ; set EEPROM address
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out EEARL, xl
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sbi EECR, EERE ; start EEPROM read by writing EERE
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in r16, EEDR ; read data from data register
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ret
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; ---------------------------------------------------------------------------
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; Utils_WriteEeprom
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;
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; Write a byte to EEPROM (see example in ATtiny24/44/84 manual p.18).
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;
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; IN:
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; - R16: byte to write
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; - X: EEPROM Address to read from
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; OUT:
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; - nothing
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; MODIFIED REGISTERS: R17
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Utils_WriteEeprom:
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sbic EECR, EEPE ; wait for previous write to complete (if any)
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rjmp Utils_WriteEeprom
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ldi r17, (0<<EEPM1) | (0<<EEPM0) ; set programming mode
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out EECR, r17
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out EEARH, xh ; set EEPROM address
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out EEARL, xl
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out EEDR, r16 ; write data to data register
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sbi EECR, EEMPE ; write logical one to EEMPE
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sbi EECR, EEPE ; start EEPROM write by setting EEPE
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ret
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; ---------------------------------------------------------------------------
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; Utils_PseudoRandom
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;
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; Generate a pseudo random number.
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; (see https://www.avrfreaks.net/s/topic/a5C3l000000URNfEAO/t119045?comment=P-1021038)
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;
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; IN:
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; OUT:
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; - R16: 8 bit pseudo random number
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; REGS: R16, R17, R18, R19
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Utils_PseudoRandom:
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lds r16, utilsSeed
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lds r17, utilsSeed+1
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ldi r18, 0x9c
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ldi r19, 8
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Utils_PseudoRandom_step:
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lsr r17
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ror r16
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brcc Utils_PseudoRandom_nomask
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eor r17, r18
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Utils_PseudoRandom_nomask:
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dec r19
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brne Utils_PseudoRandom_step
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sts utilsSeed, r16
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sts utilsSeed+1, r17
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ret ; result in r16
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; ---------------------------------------------------------------------------
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; Utils_ReadUid
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;
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; Read UID from EEPROM.
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;
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; IN:
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; OUT:
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; - R18:R19:R20:R21: UID
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; REGS: R16, X
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Utils_ReadUid:
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push r15
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in r15, SREG
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cli
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ldi xl, LOW(EEPROM_OFFS_UUID)
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ldi xh, HIGH(EEPROM_OFFS_UUID)
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rcall Utils_ReadEeprom ; (R16)
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mov r18, r16
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adiw xh:xl, 1
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rcall Utils_ReadEeprom ; (R16)
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mov r19, r16
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adiw xh:xl, 1
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rcall Utils_ReadEeprom ; (R16)
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mov r20, r16
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adiw xh:xl, 1
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rcall Utils_ReadEeprom ; (R16)
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mov r21, r16
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pop r15
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out SREG, r15
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ret
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; ---------------------------------------------------------------------------
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; Utils_SetupUid
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;
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; Reads UID from EEPROM. If not set generate a new one and store it in EEPROM.
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;
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; IN:
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; OUT:
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; - CFLAG set if new generated, cleared if there already was one.
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; REGS: R15, R16, R18, R19, R20, R21, X
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Utils_SetupUid:
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in r15, SREG
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cli
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rcall Utils_ReadUid ; R16, X
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mov r16, r18 ; all 0x00?
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or r16, r19
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or r16, r20
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or r16, r21
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breq Utils_SetupUid_generate ; yep, go generate one
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mov r16, r18 ; all 0xff?
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and r16, r19
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and r16, r20
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and r16, r21
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inc r16
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breq Utils_SetupUid_generate ; yep, go generate one
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out SREG, r15
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clc
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ret
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Utils_SetupUid_generate:
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ldi xl, LOW(EEPROM_OFFS_UUID)
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ldi xh, HIGH(EEPROM_OFFS_UUID)
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rcall Utils_PseudoRandom ; byte 0 (R16, R17, R18, R19)
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inc r16
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rcall Utils_WriteEeprom ; (R17)
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adiw xh:xl, 1
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rcall Utils_PseudoRandom ; byte 1
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rcall Utils_WriteEeprom
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adiw xh:xl, 1
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rcall Utils_PseudoRandom ; byte 2
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rcall Utils_WriteEeprom
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adiw xh:xl, 1
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rcall Utils_PseudoRandom ; byte 3
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rcall Utils_WriteEeprom
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adiw xh:xl, 1
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out SREG, r15
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sec
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ret
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; ---------------------------------------------------------------------------
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; Get offset and mask for a given bit in a bitfield
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; IN:
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; - R16: bit to request position for
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; OUT:
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; - R1: offset into the bitfield to the byte containing the given bit
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; - R2: mask for given id (apply to r1)
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; USED REGISTERS: r1, r2, r17, Z
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Utils_GetPosAndMaskInBitField:
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mov r1, r16 ; divide by 8 to get the offset to the byte containing the given module id
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lsr r1
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lsr r1
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lsr r1 ; r1=offset of the byte holding the given bit
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mov r2, r16 ; get bit mask for bit position in table byte
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ldi r17, 7 ; keep lower 3 bits
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and r2, r17
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ldi zh, HIGH(utilsModuleBitNumToMaskMap*2)
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ldi zl, LOW(utilsModuleBitNumToMaskMap*2)
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add zl, r2
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brcc Utils_GetPosAndMaskInBitField_noOverflow
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inc zh
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Utils_GetPosAndMaskInBitField_noOverflow:
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lpm r2, z ; r2=mask for bit in byte from bitfield
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ret
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utilsModuleBitNumToMaskMap:
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.db 1, 2, 4, 8, 16, 32, 64, 128
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