951 lines
32 KiB
PHP
Executable File
951 lines
32 KiB
PHP
Executable File
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
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;***** Created: 2011-02-09 12:03 ******* Source: ATmega64HVE.xml *********
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;*************************************************************************
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;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
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;*
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;* Number : AVR000
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;* File Name : "m64HVEdef.inc"
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;* Title : Register/Bit Definitions for the ATmega64HVE
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;* Date : 2011-02-09
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;* Version : 2.35
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;* Support E-mail : avr@atmel.com
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;* Target MCU : ATmega64HVE
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;*
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;* DESCRIPTION
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;* When including this file in the assembly program file, all I/O register
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;* names and I/O register bit names appearing in the data book can be used.
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;* In addition, the six registers forming the three data pointers X, Y and
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;* Z have been assigned names XL - ZH. Highest RAM address for Internal
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;* SRAM is also defined
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;*
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;* The Register names are represented by their hexadecimal address.
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;*
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;* The Register Bit names are represented by their bit number (0-7).
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;*
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;* Please observe the difference in using the bit names with instructions
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;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
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;* (skip if bit in register set/cleared). The following example illustrates
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;* this:
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;*
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;* in r16,PORTB ;read PORTB latch
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;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
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;* out PORTB,r16 ;output to PORTB
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;*
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;* in r16,TIFR ;read the Timer Interrupt Flag Register
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;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
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;* rjmp TOV0_is_set ;jump if set
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;* ... ;otherwise do something else
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;*************************************************************************
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#ifndef _M64HVEDEF_INC_
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#define _M64HVEDEF_INC_
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#pragma partinc 0
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; ***** SPECIFY DEVICE ***************************************************
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.device ATmega64HVE
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#pragma AVRPART ADMIN PART_NAME ATmega64HVE
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.equ SIGNATURE_000 = 0x1e
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.equ SIGNATURE_001 = 0x96
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.equ SIGNATURE_002 = 0x10
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#pragma AVRPART CORE CORE_VERSION V2E
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#pragma AVRPART CORE EXTENSIONS MEXT 1
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; ***** I/O REGISTER DEFINITIONS *****************************************
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; NOTE:
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; Definitions marked "MEMORY MAPPED"are extended I/O ports
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; and cannot be used with IN/OUT instructions
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.equ VADAC3 = 0xf6 ; MEMORY MAPPED
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.equ VADAC2 = 0xf5 ; MEMORY MAPPED
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.equ VADAC1 = 0xf4 ; MEMORY MAPPED
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.equ VADAC0 = 0xf3 ; MEMORY MAPPED
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.equ VADICL = 0xf1 ; MEMORY MAPPED
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.equ VADICH = 0xf2 ; MEMORY MAPPED
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.equ CADAC3 = 0xf0 ; MEMORY MAPPED
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.equ CADAC2 = 0xef ; MEMORY MAPPED
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.equ CADAC1 = 0xee ; MEMORY MAPPED
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.equ CADAC0 = 0xed ; MEMORY MAPPED
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.equ CADICL = 0xeb ; MEMORY MAPPED
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.equ CADICH = 0xec ; MEMORY MAPPED
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.equ CADRCLH = 0xea ; MEMORY MAPPED
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.equ CADRCLL = 0xe9 ; MEMORY MAPPED
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.equ ADIMR = 0xe8 ; MEMORY MAPPED
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.equ ADIFR = 0xe7 ; MEMORY MAPPED
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.equ ADCRE = 0xe6 ; MEMORY MAPPED
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.equ ADCRD = 0xe5 ; MEMORY MAPPED
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.equ ADCRC = 0xe4 ; MEMORY MAPPED
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.equ ADCRB = 0xe3 ; MEMORY MAPPED
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.equ ADCRA = 0xe2 ; MEMORY MAPPED
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.equ ADSCSRB = 0xe1 ; MEMORY MAPPED
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.equ ADSCSRA = 0xe0 ; MEMORY MAPPED
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.equ PBOV = 0xdc ; MEMORY MAPPED
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.equ PLLCSR = 0xd8 ; MEMORY MAPPED
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.equ BGLR = 0xd4 ; MEMORY MAPPED
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.equ BGCRA = 0xd3 ; MEMORY MAPPED
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.equ BGCRB = 0xd2 ; MEMORY MAPPED
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.equ BGCSRA = 0xd1 ; MEMORY MAPPED
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.equ LINDAT = 0xca ; MEMORY MAPPED
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.equ LINSEL = 0xc9 ; MEMORY MAPPED
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.equ LINIDR = 0xc8 ; MEMORY MAPPED
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.equ LINDLR = 0xc7 ; MEMORY MAPPED
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.equ LINBRRH = 0xc6 ; MEMORY MAPPED
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.equ LINBRRL = 0xc5 ; MEMORY MAPPED
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.equ LINBTR = 0xc4 ; MEMORY MAPPED
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.equ LINERR = 0xc3 ; MEMORY MAPPED
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.equ LINENIR = 0xc2 ; MEMORY MAPPED
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.equ LINSIR = 0xc1 ; MEMORY MAPPED
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.equ LINCR = 0xc0 ; MEMORY MAPPED
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.equ OCR1B = 0x89 ; MEMORY MAPPED
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.equ OCR1A = 0x88 ; MEMORY MAPPED
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.equ TCNT1L = 0x84 ; MEMORY MAPPED
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.equ TCNT1H = 0x85 ; MEMORY MAPPED
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.equ TCCR1C = 0x82 ; MEMORY MAPPED
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.equ TCCR1B = 0x81 ; MEMORY MAPPED
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.equ TCCR1A = 0x80 ; MEMORY MAPPED
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.equ DIDR0 = 0x7e ; MEMORY MAPPED
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.equ TIMSK1 = 0x6f ; MEMORY MAPPED
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.equ TIMSK0 = 0x6e ; MEMORY MAPPED
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.equ PCMSK1 = 0x6c ; MEMORY MAPPED
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.equ PCMSK0 = 0x6b ; MEMORY MAPPED
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.equ EICRA = 0x69 ; MEMORY MAPPED
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.equ PCICR = 0x68 ; MEMORY MAPPED
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.equ SOSCCALB = 0x67 ; MEMORY MAPPED
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.equ SOSCCALA = 0x66 ; MEMORY MAPPED
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.equ PRR0 = 0x64 ; MEMORY MAPPED
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.equ WDTCLR = 0x63 ; MEMORY MAPPED
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.equ WUTCSR = 0x62 ; MEMORY MAPPED
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.equ CLKPR = 0x61 ; MEMORY MAPPED
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.equ WDTCSR = 0x60 ; MEMORY MAPPED
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.equ SREG = 0x3f
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.equ SPL = 0x3d
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.equ SPH = 0x3e
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.equ SPMCSR = 0x37
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.equ MCUCR = 0x35
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.equ MCUSR = 0x34
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.equ SMCR = 0x33
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.equ OCDR = 0x31
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.equ TCCR0C = 0x2f
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.equ SPDR = 0x2e
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.equ SPSR = 0x2d
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.equ SPCR = 0x2c
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.equ GPIOR2 = 0x2b
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.equ GPIOR1 = 0x2a
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.equ OCR0B = 0x29
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.equ OCR0A = 0x28
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.equ TCNT0L = 0x26
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.equ TCNT0H = 0x27
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.equ TCCR0B = 0x25
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.equ TCCR0A = 0x24
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.equ GTCCR = 0x23
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.equ EEARL = 0x21
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.equ EEARH = 0x22
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.equ EEDR = 0x20
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.equ EECR = 0x1f
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.equ GPIOR0 = 0x1e
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.equ EIMSK = 0x1d
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.equ EIFR = 0x1c
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.equ PCIFR = 0x1b
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.equ TIFR1 = 0x16
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.equ TIFR0 = 0x15
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.equ PORTB = 0x05
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.equ DDRB = 0x04
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.equ PINB = 0x03
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.equ PORTA = 0x02
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.equ DDRA = 0x01
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.equ PINA = 0x00
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; ***** BIT DEFINITIONS **************************************************
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; ***** SPI **************************
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; SPDR - SPI Data Register
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.equ SPDR0 = 0 ; SPI Data Register bit 0
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.equ SPDR1 = 1 ; SPI Data Register bit 1
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.equ SPDR2 = 2 ; SPI Data Register bit 2
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.equ SPDR3 = 3 ; SPI Data Register bit 3
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.equ SPDR4 = 4 ; SPI Data Register bit 4
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.equ SPDR5 = 5 ; SPI Data Register bit 5
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.equ SPDR6 = 6 ; SPI Data Register bit 6
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.equ SPDR7 = 7 ; SPI Data Register bit 7
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; SPSR - SPI Status Register
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.equ SPI2X = 0 ; Double SPI Speed Bit
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.equ WCOL = 6 ; Write Collision Flag
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.equ SPIF = 7 ; SPI Interrupt Flag
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; SPCR - SPI Control Register
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.equ SPR0 = 0 ; SPI Clock Rate Select 0
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.equ SPR1 = 1 ; SPI Clock Rate Select 1
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.equ CPHA = 2 ; Clock Phase
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.equ CPOL = 3 ; Clock polarity
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.equ MSTR = 4 ; Master/Slave Select
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.equ DORD = 5 ; Data Order
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.equ SPE = 6 ; SPI Enable
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.equ SPIE = 7 ; SPI Interrupt Enable
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; ***** EEPROM ***********************
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; EEDR - EEPROM Data Register
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.equ EEDR0 = 0 ; EEPROM Data Register bit 0
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.equ EEDR1 = 1 ; EEPROM Data Register bit 1
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.equ EEDR2 = 2 ; EEPROM Data Register bit 2
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.equ EEDR3 = 3 ; EEPROM Data Register bit 3
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.equ EEDR4 = 4 ; EEPROM Data Register bit 4
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.equ EEDR5 = 5 ; EEPROM Data Register bit 5
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.equ EEDR6 = 6 ; EEPROM Data Register bit 6
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.equ EEDR7 = 7 ; EEPROM Data Register bit 7
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; EECR - EEPROM Control Register
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.equ EERE = 0 ; EEPROM Read Enable
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.equ EEPE = 1 ; EEPROM Write Enable
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.equ EEWE = EEPE ; For compatibility
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.equ EEMPE = 2 ; EEPROM Master Write Enable
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.equ EEMWE = EEMPE ; For compatibility
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.equ EERIE = 3 ; EEProm Ready Interrupt Enable
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.equ EEPM0 = 4 ;
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.equ EEPM1 = 5 ;
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; ***** TIMER_COUNTER_1 **************
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; TCCR1A - Timer/Counter 1 Control Register A
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.equ WGM10 = 0 ; Waveform Generation Mode
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.equ ICS1 = 3 ; Input Capture Select
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.equ ICES1 = 4 ; Input Capture Edge Select
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.equ ICNC1 = 5 ; Input Capture Noise Canceler
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.equ ICEN1 = 6 ; Input Capture Mode Enable
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.equ TCW1 = 7 ; Timer/Counter Width
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; TCCR1B - Timer/Counter1 Control Register B
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.equ CS10 = 0 ; Clock Select1 bit 0
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.equ CS11 = 1 ; Clock Select1 bit 1
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.equ CS12 = 2 ; Clock Select1 bit 2
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; OCR1A - Output Compare Register 1A
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.equ OCR1A0 = 0 ;
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.equ OCR1A1 = 1 ;
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.equ OCR1A2 = 2 ;
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.equ OCR1A3 = 3 ;
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.equ OCR1A4 = 4 ;
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.equ OCR1A5 = 5 ;
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.equ OCR1A6 = 6 ;
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.equ OCR1A7 = 7 ;
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; OCR1B - Output Compare Register B
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.equ OCR1B0 = 0 ;
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.equ OCR1B1 = 1 ;
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.equ OCR1B2 = 2 ;
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.equ OCR1B3 = 3 ;
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.equ OCR1B4 = 4 ;
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.equ OCR1B5 = 5 ;
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.equ OCR1B6 = 6 ;
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.equ OCR1B7 = 7 ;
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; TIMSK1 - Timer/Counter Interrupt Mask Register
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.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable
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.equ OCIE1A = 1 ; Timer/Counter1 Output Compare A Interrupt Enable
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.equ OCIE1B = 2 ; Timer/Counter1 Output Compare B Interrupt Enable
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.equ ICIE1 = 3 ; Timer/Counter n Input Capture Interrupt Enable
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; TIFR1 - Timer/Counter Interrupt Flag register
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.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag
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.equ OCF1A = 1 ; Timer/Counter1 Output Compare Flag A
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.equ OCF1B = 2 ; Timer/Counter1 Output Compare Flag B
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.equ ICF1 = 3 ; Timer/Counter 1 Input Capture Flag
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; GTCCR - General Timer/Counter Control Register
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.equ PSRSYNC = 0 ; Prescaler Reset
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.equ TSM = 7 ; Timer/Counter Synchronization Mode
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; ***** PORTB ************************
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; PORTB - Port B Data Register
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.equ PORTB0 = 0 ; Port B Data Register bit 0
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.equ PB0 = 0 ; For compatibility
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.equ PORTB1 = 1 ; Port B Data Register bit 1
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.equ PB1 = 1 ; For compatibility
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.equ PORTB2 = 2 ; Port B Data Register bit 2
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.equ PB2 = 2 ; For compatibility
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.equ PORTB3 = 3 ; Port B Data Register bit 3
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.equ PB3 = 3 ; For compatibility
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.equ PORTB4 = 4 ; Port B Data Register bit 4
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.equ PB4 = 4 ; For compatibility
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.equ PORTB5 = 5 ; Port B Data Register bit 5
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.equ PB5 = 5 ; For compatibility
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.equ PORTB6 = 6 ; Port B Data Register bit 6
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.equ PB6 = 6 ; For compatibility
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.equ PORTB7 = 7 ; Port B Data Register bit 7
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.equ PB7 = 7 ; For compatibility
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; DDRB - Port B Data Direction Register
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.equ DDB0 = 0 ; Port B Data Direction Register bit 0
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.equ DDB1 = 1 ; Port B Data Direction Register bit 1
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.equ DDB2 = 2 ; Port B Data Direction Register bit 2
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.equ DDB3 = 3 ; Port B Data Direction Register bit 3
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.equ DDB4 = 4 ; Port B Data Direction Register bit 4
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.equ DDB5 = 5 ; Port B Data Direction Register bit 5
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.equ DDB6 = 6 ; Port B Data Direction Register bit 6
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.equ DDB7 = 7 ; Port B Data Direction Register bit 7
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; PINB - Port B Input Pins
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.equ PINB0 = 0 ; Port B Input Pins bit 0
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.equ PINB1 = 1 ; Port B Input Pins bit 1
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.equ PINB2 = 2 ; Port B Input Pins bit 2
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.equ PINB3 = 3 ; Port B Input Pins bit 3
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.equ PINB4 = 4 ; Port B Input Pins bit 4
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.equ PINB5 = 5 ; Port B Input Pins bit 5
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.equ PINB6 = 6 ; Port B Input Pins bit 6
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.equ PINB7 = 7 ; Port B Input Pins bit 7
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; PBOV - Port B Override
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.equ PBOE0 = 0 ; Port B Override Enable 0
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.equ PBOE3 = 3 ; Port B Override Enable 3
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.equ PBOVCE = 7 ; Port B Override Change Enable
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; ***** TIMER_COUNTER_0 **************
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; TCCR0A - Timer/Counter 0 Control Register A
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.equ WGM00 = 0 ; Waveform Generation Mode
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.equ ICS0 = 3 ; Input Capture Select
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.equ ICES0 = 4 ; Input Capture Edge Select
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.equ ICNC0 = 5 ; Input Capture Noise Canceler
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.equ ICEN0 = 6 ; Input Capture Mode Enable
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.equ TCW0 = 7 ; Timer/Counter Width
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; TCCR0B - Timer/Counter0 Control Register B
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.equ CS00 = 0 ; Clock Select0 bit 0
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.equ CS01 = 1 ; Clock Select0 bit 1
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.equ CS02 = 2 ; Clock Select0 bit 2
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; OCR0A - Output Compare Register 0A
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.equ OCR0A0 = 0 ;
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.equ OCR0A1 = 1 ;
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.equ OCR0A2 = 2 ;
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.equ OCR0A3 = 3 ;
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.equ OCR0A4 = 4 ;
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.equ OCR0A5 = 5 ;
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.equ OCR0A6 = 6 ;
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.equ OCR0A7 = 7 ;
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; OCR0B - Output Compare Register B
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.equ OCR0B0 = 0 ;
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.equ OCR0B1 = 1 ;
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.equ OCR0B2 = 2 ;
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.equ OCR0B3 = 3 ;
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.equ OCR0B4 = 4 ;
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.equ OCR0B5 = 5 ;
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.equ OCR0B6 = 6 ;
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.equ OCR0B7 = 7 ;
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; TIMSK0 - Timer/Counter Interrupt Mask Register
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.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
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.equ OCIE0A = 1 ; Timer/Counter0 Output Compare A Interrupt Enable
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.equ OCIE0B = 2 ; Timer/Counter0 Output Compare B Interrupt Enable
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.equ ICIE0 = 3 ; Timer/Counter n Input Capture Interrupt Enable
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; TIFR0 - Timer/Counter Interrupt Flag register
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.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
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.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag A
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.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag B
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.equ ICF0 = 3 ; Timer/Counter 0 Input Capture Flag
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; GTCCR - General Timer/Counter Control Register
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;.equ PSRSYNC = 0 ; Prescaler Reset
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;.equ TSM = 7 ; Timer/Counter Synchronization Mode
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; ***** BOOT_LOAD ********************
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; SPMCSR - Store Program Memory Control and Status Register
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.equ SPMEN = 0 ; Store Program Memory Enable
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.equ PGERS = 1 ; Page Erase
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.equ PGWRT = 2 ; Page Write
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.equ LBSET = 3 ; Lock Bit Set
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.equ RWWSRE = 4 ; Read-While-Write Section Read Enable
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.equ SIGRD = 5 ; Signature Row Read
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.equ RWWSB = 6 ; Read-While-Write Section Busy
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.equ SPMIE = 7 ; SPM Interrupt Enable
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; ***** AD_CONVERTER *****************
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; ADSCSRA - ADC Synchronization Control and Status Register
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.equ SCMD0 = 0 ; Synchronization Command
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.equ SCMD1 = 1 ; Synchronization Command
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.equ SBSY = 2 ; Synchronization Busy
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; ADSCSRB - ADC Synchronization Control and Status Register
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.equ CADICRB = 0 ; CADIC Data Read Out Busy
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.equ CADACRB = 1 ; CADAC Data Read Out Busy
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.equ CADICPS = 2 ; C-ADC Instantaneous Conversion Polarity Status
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.equ VADICRB = 4 ; VADIC Data Read Out Busy
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.equ VADACRB = 5 ; VADAC Data Read Out Busy
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.equ VADICPS = 6 ; V-ADC Instantaneous Conversion Polarity Status
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; ADCRA - ADC Control Register A
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.equ CKSEL = 0 ; Sampling Clock Select
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.equ ADCMS0 = 1 ; C-ADC Chopper Mode Select
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.equ ADCMS1 = 2 ; C-ADC Chopper Mode Select
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.equ ADPSEL = 3 ; ADC Polarity Select
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; ADCRB - ADC Control Register B
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.equ ADADES0 = 0 ; Accumulated Decimation Ratio Select
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.equ ADADES1 = 1 ; Accumulated Decimation Ratio Select
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.equ ADADES2 = 2 ; Accumulated Decimation Ratio Select
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.equ ADIDES0 = 3 ; Instantaneous Decimation Ratio Select
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.equ ADIDES1 = 4 ; Instantaneous Decimation Ratio Select
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; ADCRC - ADC Control Register B
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.equ CADRCT0 = 0 ; C-ADC Regular Current Count Threshold
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.equ CADRCT1 = 1 ; C-ADC Regular Current Count Threshold
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.equ CADRCT2 = 2 ; C-ADC Regular Current Count Threshold
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.equ CADRCT3 = 3 ; C-ADC Regular Current Count Threshold
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.equ CADRCM0 = 4 ; C-ADC Regular Current Comparator Mode
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.equ CADRCM1 = 5 ; C-ADC Regular Current Comparator Mode
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.equ CADEN = 7 ; C-ADC Enable
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; ADCRD - ADC Control Register D
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.equ CADDSEL = 0 ; C-ADC Diagnostics Channel Select
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.equ CADPDM0 = 1 ; C-ADC Pin Diagnostics Mode
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.equ CADPDM1 = 2 ; C-ADC Pin Diagnostics Mode
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.equ CADG0 = 3 ; C-ADC Gain
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.equ CADG1 = 4 ; C-ADC Gain
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.equ CADG2 = 5 ; C-ADC Gain
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; ADCRE - ADC Control Register E
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.equ VADMUX0 = 0 ; V-ADC Channel Select
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.equ VADMUX1 = 1 ; V-ADC Channel Select
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.equ VADMUX2 = 2 ; V-ADC Channel Select
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.equ VADPDM0 = 3 ; V-ADC Pin Diagnostics Mode
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.equ VADPDM1 = 4 ; V-ADC Pin Diagnostics Mode
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.equ VADREFS = 5 ; V-ADC Reference Select
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.equ VADEN = 7 ; V-ADC Enable
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; ADIFR - ADC Interrupt Flag Register
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.equ CADICIF = 0 ; C-ADC Instantaneous Current Interrupt Flag
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.equ CADACIF = 1 ; C-ADC Accumulated Current Interrupt Flag
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.equ CADRCIF = 2 ; C-ADC Regulator Current Interrupt Flag
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.equ VADICIF = 4 ; V-DAC Instantaneous Voltage Interrupt Flag
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.equ VADACIF = 5 ; V-ADC Accumulated Voltage Interrupt Flag
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; ADIMR - ADC Interrupt Mask Register
|
|
.equ CADICIE = 0 ; C-ADC Instantaneous Current Interrupt Enable
|
|
.equ CADACIE = 1 ; C-ADC Accumulated Current Interrupt Enable
|
|
.equ CADRCIE = 2 ; C-ADC Regulator Current Interrupt Enable
|
|
.equ VADICIE = 4 ; V-DAC Instantaneous Voltage Interrupt Enable
|
|
.equ VADACIE = 5 ; V-ADC Accumulated Voltage Interrupt Enable
|
|
|
|
; CADRCLH - CC-ADC Regulator Current Comparator Threshold Level
|
|
.equ CADRCL8 = 0 ;
|
|
.equ CADRCL9 = 1 ;
|
|
.equ CADRCL10 = 2 ;
|
|
.equ CADRCL11 = 3 ;
|
|
.equ CADRCL12 = 4 ;
|
|
.equ CADRCL13 = 5 ;
|
|
.equ CADRCL14 = 6 ;
|
|
.equ CADRCL15 = 7 ;
|
|
|
|
; CADRCLL - CC-ADC Regulator Current Comparator Threshold Level
|
|
.equ CADRCL0 = 0 ;
|
|
.equ CADRCL1 = 1 ;
|
|
.equ CADRCL2 = 2 ;
|
|
.equ CADRCL3 = 3 ;
|
|
.equ CADRCL4 = 4 ;
|
|
.equ CADRCL5 = 5 ;
|
|
.equ CADRCL6 = 6 ;
|
|
.equ CADRCL7 = 7 ;
|
|
|
|
; VADAC3 - V-ADC Accumulated Conversion Result
|
|
.equ VADAC24 = 0 ;
|
|
.equ VADAC25 = 1 ;
|
|
.equ VADAC26 = 2 ;
|
|
.equ VADAC27 = 3 ;
|
|
.equ VADAC28 = 4 ;
|
|
.equ VADAC29 = 5 ;
|
|
.equ VADAC30 = 6 ;
|
|
.equ VADAC31 = 7 ;
|
|
|
|
; VADAC2 - V-ADC Accumulated Conversion Result
|
|
.equ VADAC16 = 0 ;
|
|
.equ VADAC17 = 1 ;
|
|
.equ VADAC18 = 2 ;
|
|
.equ VADAC19 = 3 ;
|
|
.equ VADAC20 = 4 ;
|
|
.equ VADAC21 = 5 ;
|
|
.equ VADAC22 = 6 ;
|
|
.equ VADAC23 = 7 ;
|
|
|
|
; VADAC1 - V-ADC Accumulated Conversion Result
|
|
.equ VADAC08 = 0 ;
|
|
.equ VADAC09 = 1 ;
|
|
.equ VADAC10 = 2 ;
|
|
.equ VADAC11 = 3 ;
|
|
.equ VADAC12 = 4 ;
|
|
.equ VADAC13 = 5 ;
|
|
.equ VADAC14 = 6 ;
|
|
.equ VADAC15 = 7 ;
|
|
|
|
; VADAC0 - V-ADC Accumulated Conversion Result
|
|
.equ VADAC00 = 0 ;
|
|
.equ VADAC01 = 1 ;
|
|
.equ VADAC02 = 2 ;
|
|
.equ VADAC03 = 3 ;
|
|
.equ VADAC04 = 4 ;
|
|
.equ VADAC05 = 5 ;
|
|
.equ VADAC06 = 6 ;
|
|
.equ VADAC07 = 7 ;
|
|
|
|
; CADAC3 - C-ADC Accumulated Conversion Result
|
|
.equ CADAC24 = 0 ;
|
|
.equ CADAC25 = 1 ;
|
|
.equ CADAC26 = 2 ;
|
|
.equ CADAC27 = 3 ;
|
|
.equ CADAC28 = 4 ;
|
|
.equ CADAC29 = 5 ;
|
|
.equ CADAC30 = 6 ;
|
|
.equ CADAC31 = 7 ;
|
|
|
|
; CADAC2 - C-ADC Accumulated Conversion Result
|
|
.equ CADAC16 = 0 ;
|
|
.equ CADAC17 = 1 ;
|
|
.equ CADAC18 = 2 ;
|
|
.equ CADAC19 = 3 ;
|
|
.equ CADAC20 = 4 ;
|
|
.equ CADAC21 = 5 ;
|
|
.equ CADAC22 = 6 ;
|
|
.equ CADAC23 = 7 ;
|
|
|
|
; CADAC1 - C-ADC Accumulated Conversion Result
|
|
.equ CADAC08 = 0 ;
|
|
.equ CADAC09 = 1 ;
|
|
.equ CADAC10 = 2 ;
|
|
.equ CADAC11 = 3 ;
|
|
.equ CADAC12 = 4 ;
|
|
.equ CADAC13 = 5 ;
|
|
.equ CADAC14 = 6 ;
|
|
.equ CADAC15 = 7 ;
|
|
|
|
; CADAC0 - C-ADC Accumulated Conversion Result
|
|
.equ CADAC00 = 0 ;
|
|
.equ CADAC01 = 1 ;
|
|
.equ CADAC02 = 2 ;
|
|
.equ CADAC03 = 3 ;
|
|
.equ CADAC04 = 4 ;
|
|
.equ CADAC05 = 5 ;
|
|
.equ CADAC06 = 6 ;
|
|
.equ CADAC07 = 7 ;
|
|
|
|
|
|
; ***** PORTA ************************
|
|
; PORTA - Port A Data Register
|
|
.equ PORTA0 = 0 ; Port A Data Register bit 0
|
|
.equ PA0 = 0 ; For compatibility
|
|
.equ PORTA1 = 1 ; Port A Data Register bit 1
|
|
.equ PA1 = 1 ; For compatibility
|
|
|
|
; DDRA - Port A Data Direction Register
|
|
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
|
|
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
|
|
|
|
; PINA - Port A Input Pins
|
|
.equ PINA0 = 0 ; Input Pins, Port A bit 0
|
|
.equ PINA1 = 1 ; Input Pins, Port A bit 1
|
|
|
|
|
|
; ***** BANDGAP **********************
|
|
; BGCSRA - Bandgap Control and Status Register A
|
|
.equ BGSC0 = 0 ; Band Gap Sample Configuration
|
|
.equ BGSC1 = 1 ; Band Gap Sample Configuration
|
|
.equ BGSC2 = 2 ; Band Gap Sample Configuration
|
|
|
|
; BGCRA - Band Gap Calibration Register A
|
|
.equ BGCN0 = 0 ; Band Gap Calibration Nominal
|
|
.equ BGCN1 = 1 ; Band Gap Calibration Nominal
|
|
.equ BGCN2 = 2 ; Band Gap Calibration Nominal
|
|
.equ BGCN3 = 3 ; Band Gap Calibration Nominal
|
|
.equ BGCN4 = 4 ; Band Gap Calibration Nominal
|
|
.equ BGCN5 = 5 ; Band Gap Calibration Nominal
|
|
.equ BGCN6 = 6 ; Band Gap Calibration Nominal
|
|
.equ BGCN7 = 7 ; Band Gap Calibration Nominal
|
|
|
|
; BGCRB - Band Gap Calibration Register B
|
|
.equ BGCL0 = 0 ; Band Gap Calibration Linear
|
|
.equ BGCL1 = 1 ; Band Gap Calibration Linear
|
|
.equ BGCL2 = 2 ; Band Gap Calibration Linear
|
|
.equ BGCL3 = 3 ; Band Gap Calibration Linear
|
|
.equ BGCL4 = 4 ; Band Gap Calibration Linear
|
|
.equ BGCL5 = 5 ; Band Gap Calibration Linear
|
|
.equ BGCL6 = 6 ; Band Gap Calibration Linear
|
|
.equ BGCL7 = 7 ; Band Gap Calibration Linear
|
|
|
|
; BGLR - Band Gap Lock Register
|
|
.equ BGPL = 0 ; Band Gap Lock
|
|
.equ BGPLE = 1 ; Band Gap Lock Enable
|
|
|
|
|
|
; ***** LINUART **********************
|
|
; LINCR - LIN Control Register
|
|
.equ LCMD0 = 0 ; LIN Command and Mode bit 0
|
|
.equ LCMD1 = 1 ; LIN Command and Mode bit 1
|
|
.equ LCMD2 = 2 ; LIN Command and Mode bit 2
|
|
.equ LENA = 3 ; LIN or UART Enable
|
|
.equ LCONF0 = 4 ; LIN Configuration bit 0
|
|
.equ LCONF1 = 5 ; LIN Configuration bit 1
|
|
.equ LIN13 = 6 ; LIN Standard
|
|
.equ LSWRES = 7 ; Software Reset
|
|
|
|
; LINSIR - LIN Status and Interrupt Register
|
|
.equ LRXOK = 0 ; Receive Performed Interrupt
|
|
.equ LTXOK = 1 ; Transmit Performed Interrupt
|
|
.equ LIDOK = 2 ; Identifier Interrupt
|
|
.equ LERR = 3 ; Error Interrupt
|
|
.equ LBUSY = 4 ; Busy Signal
|
|
.equ LIDST0 = 5 ; Identifier Status bit 0
|
|
.equ LIDST1 = 6 ; Identifier Status bit 1
|
|
.equ LIDST2 = 7 ; Identifier Status bit 2
|
|
|
|
; LINENIR - LIN Enable Interrupt Register
|
|
.equ LENRXOK = 0 ; Enable Receive Performed Interrupt
|
|
.equ LENTXOK = 1 ; Enable Transmit Performed Interrupt
|
|
.equ LENIDOK = 2 ; Enable Identifier Interrupt
|
|
.equ LENERR = 3 ; Enable Error Interrupt
|
|
|
|
; LINERR - LIN Error Register
|
|
.equ LBERR = 0 ; Bit Error Flag
|
|
.equ LCERR = 1 ; Checksum Error Flag
|
|
.equ LPERR = 2 ; Parity Error Flag
|
|
.equ LSERR = 3 ; Synchronization Error Flag
|
|
.equ LFERR = 4 ; Framing Error Flag
|
|
.equ LOVERR = 5 ; Overrun Error Flag
|
|
.equ LTOERR = 6 ; Frame Time Out Error Flag
|
|
.equ LABORT = 7 ; Abort Flag
|
|
|
|
; LINBTR - LIN Bit Timing Register
|
|
.equ LBT0 = 0 ; LIN Bit Timing bit 0
|
|
.equ LBT1 = 1 ; LIN Bit Timing bit 1
|
|
.equ LBT2 = 2 ; LIN Bit Timing bit 2
|
|
.equ LBT3 = 3 ; LIN Bit Timing bit 3
|
|
.equ LBT4 = 4 ; LIN Bit Timing bit 4
|
|
.equ LBT5 = 5 ; LIN Bit Timing bit 5
|
|
.equ LDISR = 7 ; Disable Bit Timing Resynchronization
|
|
|
|
; LINBRRL - LIN Baud Rate Low Register
|
|
.equ LDIV0 = 0 ;
|
|
.equ LDIV1 = 1 ;
|
|
.equ LDIV2 = 2 ;
|
|
.equ LDIV3 = 3 ;
|
|
.equ LDIV4 = 4 ;
|
|
.equ LDIV5 = 5 ;
|
|
.equ LDIV6 = 6 ;
|
|
.equ LDIV7 = 7 ;
|
|
|
|
; LINBRRH - LIN Baud Rate High Register
|
|
.equ LDIV8 = 0 ;
|
|
.equ LDIV9 = 1 ;
|
|
.equ LDIV10 = 2 ;
|
|
.equ LDIV11 = 3 ;
|
|
|
|
; LINDLR - LIN Data Length Register
|
|
.equ LRXDL0 = 0 ; LIN Receive Data Length bit 0
|
|
.equ LRXDL1 = 1 ; LIN Receive Data Length bit 1
|
|
.equ LRXDL2 = 2 ; LIN Receive Data Length bit 2
|
|
.equ LRXDL3 = 3 ; LIN Receive Data Length bit 3
|
|
.equ LTXDL0 = 4 ; LIN Transmit Data Length bit 0
|
|
.equ LTXDL1 = 5 ; LIN Transmit Data Length bit 1
|
|
.equ LTXDL2 = 6 ; LIN Transmit Data Length bit 2
|
|
.equ LTXDL3 = 7 ; LIN Transmit Data Length bit 3
|
|
|
|
; LINIDR - LIN Identifier Register
|
|
.equ LID0 = 0 ; Identifier bit 0
|
|
.equ LID1 = 1 ; Identifier bit 1
|
|
.equ LID2 = 2 ; Identifier bit 2
|
|
.equ LID3 = 3 ; Identifier bit 3
|
|
.equ LID4 = 4 ; Identifier bit 4 or Data Length bit 0
|
|
.equ LID5 = 5 ; Identifier bit 5 or Data Length bit 1
|
|
.equ LP0 = 6 ; Parity bit 0
|
|
.equ LP1 = 7 ; Parity bit 1
|
|
|
|
; LINSEL - LIN Data Buffer Selection Register
|
|
.equ LINDX0 = 0 ; FIFO LIN Data Buffer Index bit 0
|
|
.equ LINDX1 = 1 ; FIFO LIN Data Buffer Index bit 1
|
|
.equ LINDX2 = 2 ; FIFO LIN Data Buffer Index bit 2
|
|
.equ LAINC = 3 ; Auto Increment of Data Buffer Index (Active Low)
|
|
|
|
; LINDAT - LIN Data Register
|
|
.equ LDATA0 = 0 ;
|
|
.equ LDATA1 = 1 ;
|
|
.equ LDATA2 = 2 ;
|
|
.equ LDATA3 = 3 ;
|
|
.equ LDATA4 = 4 ;
|
|
.equ LDATA5 = 5 ;
|
|
.equ LDATA6 = 6 ;
|
|
.equ LDATA7 = 7 ;
|
|
|
|
|
|
; ***** CPU **************************
|
|
; SREG - Status Register
|
|
.equ SREG_C = 0 ; Carry Flag
|
|
.equ SREG_Z = 1 ; Zero Flag
|
|
.equ SREG_N = 2 ; Negative Flag
|
|
.equ SREG_V = 3 ; Two's Complement Overflow Flag
|
|
.equ SREG_S = 4 ; Sign Bit
|
|
.equ SREG_H = 5 ; Half Carry Flag
|
|
.equ SREG_T = 6 ; Bit Copy Storage
|
|
.equ SREG_I = 7 ; Global Interrupt Enable
|
|
|
|
; MCUCR - MCU Control Register
|
|
.equ IVCE = 0 ; Interrupt Vector Change Enable
|
|
.equ IVSEL = 1 ; Interrupt Vector Select
|
|
.equ PUD = 4 ; Pull-up disable
|
|
.equ CKOE = 5 ; Clock Output Enable
|
|
|
|
; MCUSR - MCU Status Register
|
|
.equ PORF = 0 ; Power-on reset flag
|
|
.equ EXTRF = 1 ; External Reset Flag
|
|
.equ BODRF = 2 ; Brown-out Reset Flag
|
|
.equ WDRF = 3 ; Watchdog Reset Flag
|
|
.equ OCDRF = 4 ; OCD Reset Flag
|
|
|
|
; SOSCCALA - Slow Oscillator Calibration Register A
|
|
.equ SCALA0 = 0 ; Oscillator Calibration Value Bit0
|
|
.equ SCALA1 = 1 ; Oscillator Calibration Value Bit1
|
|
.equ SCALA2 = 2 ; Oscillator Calibration Value Bit2
|
|
.equ SCALA3 = 3 ; Oscillator Calibration Value Bit3
|
|
.equ SCALA4 = 4 ; Oscillator Calibration Value Bit4
|
|
.equ SCALA5 = 5 ; Oscillator Calibration Value Bit5
|
|
.equ SCALA6 = 6 ; Oscillator Calibration Value Bit6
|
|
.equ SCALA7 = 7 ; Oscillator Calibration Value Bit7
|
|
|
|
; SOSCCALB - Oscillator Calibration Register B
|
|
.equ SCALB0 = 0 ; Oscillator Calibration Value Bit0
|
|
.equ SCALB1 = 1 ; Oscillator Calibration Value Bit1
|
|
.equ SCALB2 = 2 ; Oscillator Calibration Value Bit2
|
|
.equ SCALB3 = 3 ; Oscillator Calibration Value Bit3
|
|
.equ SCALB4 = 4 ; Oscillator Calibration Value Bit4
|
|
.equ SCALB5 = 5 ; Oscillator Calibration Value Bit5
|
|
.equ SCALB6 = 6 ; Oscillator Calibration Value Bit6
|
|
.equ SCALB7 = 7 ; Oscillator Calibration Value Bit7
|
|
|
|
; PLLCSR - PLL Control and Status Register
|
|
.equ PLLCIE = 0 ; PLL Lock Change Interrupt Enable
|
|
.equ PLLCIF = 1 ; PLL Lock Change Interrupt Flag
|
|
.equ LOCK = 4 ; PLL Lock
|
|
.equ SWEN = 5 ; PLL Software Enable
|
|
|
|
; SMCR - Sleep Mode Control Register
|
|
.equ SE = 0 ; Sleep Enable
|
|
.equ SM0 = 1 ; Sleep Mode Select bit 0
|
|
.equ SM1 = 2 ; Sleep Mode Select bit 1
|
|
.equ SM2 = 3 ; Sleep Mode Select bit 2
|
|
|
|
; GPIOR2 - General Purpose IO Register 2
|
|
.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0
|
|
.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1
|
|
.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2
|
|
.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3
|
|
.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4
|
|
.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5
|
|
.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6
|
|
.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7
|
|
|
|
; GPIOR1 - General Purpose IO Register 1
|
|
.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0
|
|
.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1
|
|
.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2
|
|
.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3
|
|
.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4
|
|
.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5
|
|
.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6
|
|
.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7
|
|
|
|
; GPIOR0 - General Purpose IO Register 0
|
|
.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0
|
|
.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1
|
|
.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2
|
|
.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3
|
|
.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4
|
|
.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5
|
|
.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6
|
|
.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7
|
|
|
|
; DIDR0 - Digital Input Disable Register
|
|
.equ PA0DID = 0 ; When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.
|
|
.equ PA1DID = 1 ; When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.
|
|
|
|
; PRR0 - Power Reduction Register 0
|
|
.equ PRTIM0 = 0 ; Power Reduction Timer/Counter0
|
|
.equ PRTIM1 = 1 ; Power Reduction Timer/Counter1
|
|
.equ PRSPI = 2 ; Power reduction SPI
|
|
.equ PRLIN = 3 ; Power Reduction LIN UART Interface
|
|
|
|
; CLKPR - Clock Prescale Register
|
|
.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0
|
|
.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1
|
|
.equ CLKPCE = 7 ; Clock Prescaler Change Enable
|
|
|
|
|
|
; ***** EXTERNAL_INTERRUPT ***********
|
|
; EICRA - External Interrupt Control Register
|
|
.equ ISC00 = 0 ; External Interrupt Sense Control 0 Bit 0
|
|
.equ ISC01 = 1 ; External Interrupt Sense Control 0 Bit 1
|
|
|
|
; EIMSK - External Interrupt Mask Register
|
|
.equ INT0 = 0 ; External Interrupt Request 0 Enable
|
|
|
|
; EIFR - External Interrupt Flag Register
|
|
.equ INTF0 = 0 ; External Interrupt Flag 0
|
|
|
|
; PCICR - Pin Change Interrupt Control Register
|
|
.equ PCIE0 = 0 ; Pin Change Interrupt Enable 0
|
|
.equ PCIE1 = 1 ; Pin Change Interrupt Enable 1
|
|
|
|
; PCIFR - Pin Change Interrupt Flag Register
|
|
.equ PCIF0 = 0 ; Pin Change Interrupt Flag 1
|
|
.equ PCIF1 = 1 ; Pin Change Interrupt Flag 1
|
|
|
|
; PCMSK1 - Pin Change Enable Mask Register 1
|
|
.equ PCINT2 = 0 ; Pin Change Enable Mask 2
|
|
.equ PCINT3 = 1 ; Pin Change Enable Mask 3
|
|
.equ PCINT4 = 2 ; Pin Change Enable Mask 4
|
|
.equ PCINT5 = 3 ; Pin Change Enable Mask 5
|
|
.equ PCINT6 = 4 ; Pin Change Enable Mask 6
|
|
.equ PCINT7 = 5 ; Pin Change Enable Mask 7
|
|
.equ PCINT8 = 6 ; Pin Change Enable Mask 8
|
|
.equ PCINT9 = 7 ; Pin Change Enable Mask 9
|
|
|
|
; PCMSK0 - Pin Change Enable Mask Register 0
|
|
.equ PCINT0 = 0 ; Pin Change Enable Mask 0
|
|
.equ PCINT1 = 1 ; Pin Change Enable Mask 1
|
|
|
|
|
|
; ***** WATCHDOG *********************
|
|
; WDTCSR - Watchdog Timer Control Register
|
|
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
|
|
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
|
|
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
|
|
.equ WDE = 3 ; Watch Dog Enable
|
|
.equ WDCE = 4 ; Watchdog Change Enable
|
|
.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3
|
|
.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable
|
|
.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag
|
|
|
|
; WDTCLR - Watchdog Timer Configuration Lock Register
|
|
.equ WDCLE = 0 ; Watchdog Timer Comfiguration Lock Enable
|
|
.equ WDCL0 = 1 ; Watchdog Timer Comfiguration Lock bit 0
|
|
.equ WDCL1 = 2 ; Watchdog Timer Comfiguration Lock bit 1
|
|
|
|
|
|
; ***** WAKEUP_TIMER *****************
|
|
; WUTCSR - Wake-up Timer Control and Status Register
|
|
.equ WUTP0 = 0 ; Wake-up Timer Prescaler Bit 0
|
|
.equ WUTP1 = 1 ; Wake-up Timer Prescaler Bit 1
|
|
.equ WUTP2 = 2 ; Wake-up Timer Prescaler Bit 2
|
|
.equ WUTE = 3 ; Wake-up Timer Enable
|
|
.equ WUTR = 4 ; Wake-up Timer Reset
|
|
.equ WUTIE = 6 ; Wake-up Timer Interrupt Enable
|
|
.equ WUTIF = 7 ; Wake-up Timer Interrupt Flag
|
|
|
|
|
|
|
|
; ***** LOCKSBITS ********************************************************
|
|
.equ LB1 = 0 ; Lock bit
|
|
.equ LB2 = 1 ; Lock bit
|
|
.equ BLB01 = 2 ; Boot Lock bit
|
|
.equ BLB02 = 3 ; Boot Lock bit
|
|
.equ BLB11 = 4 ; Boot lock bit
|
|
.equ BLB12 = 5 ; Boot lock bit
|
|
|
|
|
|
; ***** FUSES ************************************************************
|
|
; LOW fuse bits
|
|
.equ OSCSEL0 = 0 ; Oscillator Select
|
|
.equ SUT0 = 1 ; Select start-up time
|
|
.equ SUT1 = 2 ; Select start-up time
|
|
.equ CKDIV8 = 3 ; Divide clock by 8
|
|
.equ BODEN = 4 ; Enable BOD
|
|
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading
|
|
.equ EESAVE = 6 ; EEPROM memory is preserved through chip erase
|
|
.equ WDTON = 7 ; Watchdog Timer Always On
|
|
|
|
; HIGH fuse bits
|
|
.equ BOOTRST = 0 ; Select Reset Vector
|
|
.equ BOOTSZ0 = 1 ; Select Boot Size
|
|
.equ BOOTSZ1 = 2 ; Select Boot Size
|
|
.equ DWEN = 3 ; Enable debugWire
|
|
|
|
|
|
|
|
; ***** CPU REGISTER DEFINITIONS *****************************************
|
|
.def XH = r27
|
|
.def XL = r26
|
|
.def YH = r29
|
|
.def YL = r28
|
|
.def ZH = r31
|
|
.def ZL = r30
|
|
|
|
|
|
|
|
; ***** DATA MEMORY DECLARATIONS *****************************************
|
|
.equ FLASHEND = 0x7fff ; Note: Word address
|
|
.equ IOEND = 0x00ff
|
|
.equ SRAM_START = 0x0100
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.equ SRAM_SIZE = 4096
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.equ RAMEND = 0x10ff
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.equ XRAMEND = 0x0000
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.equ E2END = 0x03ff
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.equ EEPROMEND = 0x03ff
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.equ EEADRBITS = 10
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#pragma AVRPART MEMORY PROG_FLASH 65536
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#pragma AVRPART MEMORY EEPROM 1024
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#pragma AVRPART MEMORY INT_SRAM SIZE 4096
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#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100
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; ***** BOOTLOADER DECLARATIONS ******************************************
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.equ NRWW_START_ADDR = 0x7000
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.equ NRWW_STOP_ADDR = 0x7fff
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.equ RWW_START_ADDR = 0x0
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.equ RWW_STOP_ADDR = 0x6fff
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.equ PAGESIZE = 64
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.equ FIRSTBOOTSTART = 0x7e00
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.equ SECONDBOOTSTART = 0x7c00
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.equ THIRDBOOTSTART = 0x7800
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.equ FOURTHBOOTSTART = 0x7000
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.equ SMALLBOOTSTART = FIRSTBOOTSTART
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.equ LARGEBOOTSTART = FOURTHBOOTSTART
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; ***** INTERRUPT VECTORS ************************************************
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.equ INT0addr = 0x0002 ; External Interrupt 0
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.equ PCI0addr = 0x0004 ; Pin Change Interrupt 0
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.equ PCI1addr = 0x0006 ; Pin Change Interrupt 1
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.equ WDTaddr = 0x0008 ; Watchdog Timeout Interrupt
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.equ WUTaddr = 0x000a ; Wakeup Timer Overflow
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.equ ICP1addr = 0x000c ; Timer 1 Input capture
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.equ OC1Aaddr = 0x000e ; Timer 1 Compare Match A
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.equ OC1Baddr = 0x0010 ; Timer 1 Compare Match B
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.equ OVF1addr = 0x0012 ; Timer 1 overflow
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.equ ICP0addr = 0x0014 ; Timer 0 Input Capture
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.equ OC0Aaddr = 0x0016 ; Timer 0 Comapre Match A
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.equ OC0Baddr = 0x0018 ; Timer 0 Compare Match B
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.equ OVF0addr = 0x001a ; Timer 0 Overflow
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.equ LIN_STATUSaddr = 0x001c ; LIN Status Interrupt
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.equ LIN_ERRORaddr = 0x001e ; LIN Error Interrupt
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.equ SPIaddr = 0x0020 ; SPI Serial transfer complete
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.equ VADCaddr = 0x0022 ; Voltage ADC Instantaneous Conversion Complete
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.equ VADC_ACCaddr = 0x0024 ; Voltage ADC Accumulated Conversion Complete
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.equ CADICaddr = 0x0026 ; C-ADC Instantaneous Conversion Complete
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.equ CADRCaddr = 0x0028 ; C-ADC Regular Current
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.equ CADACaddr = 0x002a ; C-ADC Accumulated Conversion Complete
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.equ ERDYaddr = 0x002c ; EEPROM Ready
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.equ SPMRaddr = 0x002e ; SPM Ready
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.equ PLLaddr = 0x0030 ; PLL Lock Change Interrupt
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.equ INT_VECTORS_SIZE = 50 ; size in words
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#endif /* _M64HVEDEF_INC_ */
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; ***** END OF FILE ******************************************************
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