704 lines
22 KiB
PHP
Executable File
704 lines
22 KiB
PHP
Executable File
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
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;***** Created: 2011-02-09 12:03 ******* Source: ATtiny20.xml ************
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;*************************************************************************
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;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
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;*
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;* Number : AVR000
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;* File Name : "tn20def.inc"
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;* Title : Register/Bit Definitions for the ATtiny20
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;* Date : 2011-02-09
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;* Version : 2.35
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;* Support E-mail : avr@atmel.com
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;* Target MCU : ATtiny20
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;*
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;* DESCRIPTION
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;* When including this file in the assembly program file, all I/O register
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;* names and I/O register bit names appearing in the data book can be used.
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;* In addition, the six registers forming the three data pointers X, Y and
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;* Z have been assigned names XL - ZH. Highest RAM address for Internal
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;* SRAM is also defined
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;*
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;* The Register names are represented by their hexadecimal address.
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;*
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;* The Register Bit names are represented by their bit number (0-7).
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;*
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;* Please observe the difference in using the bit names with instructions
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;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
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;* (skip if bit in register set/cleared). The following example illustrates
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;* this:
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;*
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;* in r16,PORTB ;read PORTB latch
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;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
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;* out PORTB,r16 ;output to PORTB
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;*
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;* in r16,TIFR ;read the Timer Interrupt Flag Register
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;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
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;* rjmp TOV0_is_set ;jump if set
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;* ... ;otherwise do something else
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;*************************************************************************
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#ifndef _TN20DEF_INC_
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#define _TN20DEF_INC_
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#pragma partinc 0
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; ***** SPECIFY DEVICE ***************************************************
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.device ATtiny20
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#pragma AVRPART ADMIN PART_NAME ATtiny20
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.equ SIGNATURE_000 = 0x1e
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.equ SIGNATURE_001 = 0x91
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.equ SIGNATURE_002 = 0x0f
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#pragma AVRPART CORE CORE_VERSION AVR8L_0
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; ***** I/O REGISTER DEFINITIONS *****************************************
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; NOTE:
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; Definitions marked "MEMORY MAPPED"are extended I/O ports
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; and cannot be used with IN/OUT instructions
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.equ SREG = 0x3f
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.equ SPL = 0x3d
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.equ SPH = 0x3e
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.equ CCP = 0x3c
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.equ RSTFLR = 0x3b
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.equ MCUCR = 0x3a
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.equ OSCCAL = 0x39
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.equ CLKMSR = 0x37
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.equ CLKPSR = 0x36
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.equ PRR = 0x35
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.equ QTCSR = 0x34
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.equ NVMCMD = 0x33
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.equ NVMCSR = 0x32
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.equ WDTCSR = 0x31
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.equ SPCR = 0x30
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.equ SPSR = 0x2f
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.equ SPDR = 0x2e
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.equ TWSCRA = 0x2d
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.equ TWSCRB = 0x2c
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.equ TWSSRA = 0x2b
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.equ TWSA = 0x2a
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.equ TWSAM = 0x29
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.equ TWSD = 0x28
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.equ GTCCR = 0x27
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.equ TIMSK = 0x26
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.equ TIFR = 0x25
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.equ TCCR1A = 0x24
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.equ TCCR1B = 0x23
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.equ TCCR1C = 0x22
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.equ TCNT1H = 0x21
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.equ TCNT1L = 0x20
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.equ OCR1AL = 0x1e
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.equ OCR1AH = 0x1f
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.equ OCR1BL = 0x1c
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.equ OCR1BH = 0x1d
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.equ ICR1L = 0x1a
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.equ ICR1H = 0x1b
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.equ TCCR0A = 0x19
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.equ TCCR0B = 0x18
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.equ TCNT0 = 0x17
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.equ OCR0A = 0x16
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.equ OCR0B = 0x15
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.equ ACSRA = 0x14
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.equ ACSRB = 0x13
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.equ ADCSRA = 0x12
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.equ ADCSRB = 0x11
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.equ ADMUX = 0x10
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.equ ADCH = 0x0f
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.equ ADCL = 0x0e
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.equ DIDR0 = 0x0d
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.equ GIMSK = 0x0c
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.equ GIFR = 0x0b
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.equ PCMSK1 = 0x0a
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.equ PCMSK0 = 0x09
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.equ PORTCR = 0x08
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.equ PUEB = 0x07
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.equ PORTB = 0x06
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.equ DDRB = 0x05
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.equ PINB = 0x04
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.equ PUEA = 0x03
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.equ PORTA = 0x02
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.equ DDRA = 0x01
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.equ PINA = 0x00
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; ***** BIT DEFINITIONS **************************************************
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; ***** PORTB ************************
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; PORTCR - Port Control Register
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.equ BBMB = 1 ; Break-Before-Make Mode Enable
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; PUEB - Pull-up Enable Control Register
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.equ PUEB0 = 0 ;
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.equ PUEB1 = 1 ;
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.equ PUEB2 = 2 ;
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.equ PUEB3 = 3 ;
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; PORTB - Input Pins, Port B
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.equ PORTB0 = 0 ;
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.equ PB0 = 0 ; For compatibility
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.equ PORTB1 = 1 ;
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.equ PB1 = 1 ; For compatibility
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.equ PORTB2 = 2 ;
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.equ PB2 = 2 ; For compatibility
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.equ PORTB3 = 3 ;
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.equ PB3 = 3 ; For compatibility
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; DDRB - Data Direction Register, Port B
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.equ DDB0 = 0 ;
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.equ DDB1 = 1 ;
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.equ DDB2 = 2 ;
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.equ DDB3 = 3 ;
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; PINB - Port B Data register
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.equ PINB0 = 0 ;
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.equ PINB1 = 1 ;
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.equ PINB2 = 2 ;
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.equ PINB3 = 3 ;
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; ***** WATCHDOG *********************
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; WDTCSR - Watchdog Timer Control and Status Register
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.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
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.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
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.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
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.equ WDE = 3 ; Watch Dog Enable
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.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3
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.equ WDIE = 6 ; Watchdog Timer Interrupt Enable
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.equ WDIF = 7 ; Watchdog Timer Interrupt Flag
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; ***** AD_CONVERTER *****************
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; ADMUX - The ADC multiplexer Selection Register
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.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
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.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
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.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits
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.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits
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.equ REFS = 6 ; Reference Selection Bit
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; ADCSRA - The ADC Control and Status register
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.equ ADPS0 = 0 ; ADC Prescaler Select Bits
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.equ ADPS1 = 1 ; ADC Prescaler Select Bits
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.equ ADPS2 = 2 ; ADC Prescaler Select Bits
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.equ ADIE = 3 ; ADC Interrupt Enable
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.equ ADIF = 4 ; ADC Interrupt Flag
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.equ ADATE = 5 ; ADC Auto Trigger Enable
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.equ ADSC = 6 ; ADC Start Conversion
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.equ ADEN = 7 ; ADC Enable
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; ADCH - ADC Data Register High Byte
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.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0
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.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1
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.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2
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.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3
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.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4
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.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5
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.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6
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.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7
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; ADCL - ADC Data Register Low Byte
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.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0
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.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1
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.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2
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.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3
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.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4
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.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5
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.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6
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.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7
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; ADCSRB - ADC Control and Status Register B
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.equ ADTS0 = 0 ; ADC Auto Trigger Source 0
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.equ ADTS1 = 1 ; ADC Auto Trigger Source 1
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.equ ADTS2 = 2 ; ADC Auto Trigger Source 2
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.equ ADLAR = 3 ;
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; DIDR0 - Digital Input Disable Register 0
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.equ ADC0D = 0 ; ADC0 Digital input Disable
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.equ ADC1D = 1 ; ADC1 Digital input Disable
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.equ ADC2D = 2 ; ADC2 Digital input Disable
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.equ ADC3D = 3 ; AREF Digital Input Disable
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.equ ADC4D = 4 ; ADC3 Digital input Disable
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.equ ADC5D = 5 ; ADC4 Digital input Disable
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.equ ADC6D = 6 ; ADC5 Digital input Disable
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.equ ADC7D = 7 ; ADC6 Digital input Disable
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; ***** ANALOG_COMPARATOR ************
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; ACSRA - Analog Comparator Control And Status Register A
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.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
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.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
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.equ ACIC = 2 ; Analog Comparator Input Capture Enable
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.equ ACIE = 3 ; Analog Comparator Interrupt Enable
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.equ ACI = 4 ; Analog Comparator Interrupt Flag
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.equ ACO = 5 ; Analog Compare Output
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.equ ACBG = 6 ; Analog Comparator Bandgap Select
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.equ ACD = 7 ; Analog Comparator Disable
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; ACSRB - Analog Comparator Control And Status Register B
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.equ ACME = 2 ; Analog Comparator Multiplexer Enable
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.equ HLEV = 6 ; Hysteresis Level
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.equ HSEL = 7 ; Hysteresis Select
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; ***** CPU **************************
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; CCP - Configuration Change Protection
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.equ CCP0 = 0 ; Configuration Change Protection bit 0
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.equ CCP1 = 1 ; Configuration Change Protection bit 1
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.equ CCP2 = 2 ; Configuration Change Protection bit 2
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.equ CCP3 = 3 ; Configuration Change Protection bit 3
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.equ CCP4 = 4 ; Configuration Change Protection bit 4
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.equ CCP5 = 5 ; Configuration Change Protection bit 5
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.equ CCP6 = 6 ; Configuration Change Protection bit 6
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.equ CCP7 = 7 ; Configuration Change Protection bit 7
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; SREG - Status Register
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.equ SREG_C = 0 ; Carry Flag
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.equ SREG_Z = 1 ; Zero Flag
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.equ SREG_N = 2 ; Negative Flag
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.equ SREG_V = 3 ; Two's Complement Overflow Flag
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.equ SREG_S = 4 ; Sign Bit
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.equ SREG_H = 5 ; Half Carry Flag
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.equ SREG_T = 6 ; Bit Copy Storage
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.equ SREG_I = 7 ; Global Interrupt Enable
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; CLKMSR - Clock Main Settings Register
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.equ CLKMS0 = 0 ; Clock Main Select Bit 0
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.equ CLKMS1 = 1 ; Clock Main Select Bit 1
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; CLKPSR - Clock Prescale Register
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.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0
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.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1
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.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2
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.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3
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; OSCCAL - Oscillator Calibration Value
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.equ CAL0 = 0 ; Oscillator Calibration Value Bit0
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.equ CAL1 = 1 ; Oscillator Calibration Value Bit1
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.equ CAL2 = 2 ; Oscillator Calibration Value Bit2
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.equ CAL3 = 3 ; Oscillator Calibration Value Bit3
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.equ CAL4 = 4 ; Oscillator Calibration Value Bit4
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.equ CAL5 = 5 ; Oscillator Calibration Value Bit5
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.equ CAL6 = 6 ; Oscillator Calibration Value Bit6
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.equ CAL7 = 7 ; Oscillator Calibration Value Bit7
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; PRR - Power Reduction Register
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.equ PRADC = 0 ; Power Reduction ADC
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.equ PRTIM0 = 1 ; Power Reduction Timer/Counter0
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.equ PRTIM1 = 2 ; Power Reduction Timer/Counter1
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.equ PRSPI = 3 ; Power Reduction Serial Peripheral Interface
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.equ PRTWI = 4 ; Power Reduction TWI
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; RSTFLR - Reset Flag Register
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.equ PORF = 0 ; Power-on Reset Flag
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.equ EXTRF = 1 ; External Reset Flag
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.equ WDRF = 3 ; Watchdog Reset Flag
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; NVMCSR - Non-Volatile Memory Control and Status Register
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.equ NVMBSY = 7 ; Non-Volatile Memory Busy
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; NVMCMD - Non-Volatile Memory Command
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.equ NVMCMD0 = 0 ;
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.equ NVMCMD1 = 1 ;
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.equ NVMCMD2 = 2 ;
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.equ NVMCMD3 = 3 ;
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.equ NVMCMD4 = 4 ;
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.equ NVMCMD5 = 5 ;
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; MCUCR - MCU Control Register
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.equ SE = 0 ;
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.equ SM0 = 1 ;
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.equ SM1 = 2 ;
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.equ SM2 = 3 ;
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.equ BODS = 4 ;
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.equ ISC00 = 6 ;
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.equ ISC01 = 7 ;
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; ***** EXTERNAL_INTERRUPT ***********
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; PCMSK1 - Pin Change Mask Register 1
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.equ PCINT8 = 0 ; Pin Change Enable Mask 8
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.equ PCINT9 = 1 ; Pin Change Enable Mask 9
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.equ PCINT10 = 2 ; Pin Change Enable Mask 10
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.equ PCINT11 = 3 ; Pin Change Enable Mask 11
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; PCMSK0 - Pin Change Mask Register 0
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.equ PCINT0 = 0 ; Pin Change Enable Mask 0
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.equ PCINT1 = 1 ; Pin Change Enable Mask 1
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.equ PCINT2 = 2 ; Pin Change Enable Mask 2
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.equ PCINT3 = 3 ; Pin Change Enable Mask 3
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.equ PCINT4 = 4 ; Pin Change Enable Mask 4
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.equ PCINT5 = 5 ; Pin Change Enable Mask 5
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.equ PCINT6 = 6 ; Pin Change Enable Mask 6
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.equ PCINT7 = 7 ; Pin Change Enable Mask 7
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; GIFR - General Interrupt Flag Register
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.equ INTF0 = 0 ; External Interrupt Flag 0
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.equ PCIF0 = 4 ; Pin Change Interrupt Flag 0
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.equ PCIF1 = 5 ; Pin Change Interrupt Flag 1
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; GIMSK - General Interrupt Mask Register
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.equ INT0 = 0 ; External Interrupt Request 0 Enable
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.equ PCIE0 = 4 ; Pin Change Interrupt Enable 0
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.equ PCIE1 = 5 ; Pin Change Interrupt Enable 1
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; ***** TIMER_COUNTER_0 **************
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; TCCR0A - Timer/Counter 0 Control Register A
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.equ WGM00 = 0 ; Waveform Generation Mode
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.equ WGM01 = 1 ; Waveform Generation Mode
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.equ COM0B0 = 4 ; Compare Output Mode for Channel B bit 0
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.equ COM0B1 = 5 ; Compare Output Mode for Channel B bit 1
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.equ COM0A0 = 6 ; Compare Output Mode for Channel A bit 0
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.equ COM0A1 = 7 ; Compare Output Mode for Channel A bit 1
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; TCCR0B - Timer/Counter 0 Control Register B
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.equ CS00 = 0 ; Clock Select
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.equ CS01 = 1 ; Clock Select
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.equ CS02 = 2 ; Clock Select
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.equ WGM02 = 3 ; Waveform Generation Mode
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.equ FOC0B = 6 ; Force Output Compare B
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.equ FOC0A = 7 ; Force Output Compare A
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; TIMSK - Timer Interrupt Mask Register
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.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
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.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable
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.equ OCIE0B = 2 ; Timer/Counter Output Compare Match B Interrupt Enable
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.equ TOIE1 = 3 ; Overflow Interrupt Enable
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.equ OCIE1A = 4 ; Output Compare A Match Interrupt Enable
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.equ OCIE1B = 5 ; Output Compare B Match Interrupt Enable
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.equ ICIE1 = 7 ; Input Capture Interrupt Enable
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; TIFR - Overflow Interrupt Enable
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.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
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.equ OCF0A = 1 ; Output Compare Flag 0 A
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.equ OCF0B = 2 ; Output Compare Flag 0 B
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.equ TOV1 = 3 ; Timer Overflow Flag
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.equ OCF1A = 4 ; Timer Output Compare Flag 1A
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.equ OCF1B = 5 ; Timer Output Compare Flag 1B
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.equ ICF1 = 7 ; Input Capture Flag
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; GTCCR - General Timer/Counter Control Register
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.equ PSR = 0 ; Prescaler Reset
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.equ TSM = 7 ; Timer Synchronization Mode
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; TCNT0 - Timer/Counter0
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.equ TCNT0_0 = 0 ;
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.equ TCNT0_1 = 1 ;
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.equ TCNT0_2 = 2 ;
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.equ TCNT0_3 = 3 ;
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.equ TCNT0_4 = 4 ;
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.equ TCNT0_5 = 5 ;
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.equ TCNT0_6 = 6 ;
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.equ TCNT0_7 = 7 ;
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; OCR0A - Timer/Counter0 Output Compare Register
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.equ OCR0_0 = 0 ;
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.equ OCR0_1 = 1 ;
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.equ OCR0_2 = 2 ;
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.equ OCR0_3 = 3 ;
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.equ OCR0_4 = 4 ;
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.equ OCR0_5 = 5 ;
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.equ OCR0_6 = 6 ;
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.equ OCR0_7 = 7 ;
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; OCR0B - Timer/Counter0 Output Compare Register
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.equ OCR0B_0 = 0 ;
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.equ OCR0B_1 = 1 ;
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.equ OCR0B_2 = 2 ;
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.equ OCR0B_3 = 3 ;
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.equ OCR0B_4 = 4 ;
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.equ OCR0B_5 = 5 ;
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.equ OCR0B_6 = 6 ;
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.equ OCR0B_7 = 7 ;
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; ***** TWI **************************
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; TWSCRA - TWI Slave Control Register A
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.equ TWSME = 0 ; TWI Smart Mode Enable
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.equ TWPME = 1 ; TWI Promiscuous Mode Enable
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.equ TWSIE = 2 ; TWI Stop Interrupt Enable
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.equ TWEN = 3 ; Two-Wire Interface Enable
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.equ TWASIE = 4 ; TWI Address/Stop Interrupt Enable
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.equ TWDIE = 5 ; TWI Data Interrupt Enable
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.equ TWSHE = 7 ; TWI SDA Hold Time Enable
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; TWSCRB - TWI Slave Control Register B
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.equ TWCMD0 = 0 ;
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.equ TWCMD1 = 1 ;
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.equ TWAA = 2 ; TWI Acknowledge Action
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; TWSSRA - TWI Slave Status Register A
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.equ TWAS = 0 ; TWI Address or Stop
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.equ TWDIR = 1 ; TWI Read/Write Direction
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.equ TWBE = 2 ; TWI Bus Error
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.equ TWC = 3 ; TWI Collision
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.equ TWRA = 4 ; TWI Receive Acknowledge
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.equ TWCH = 5 ; TWI Clock Hold
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.equ TWASIF = 6 ; TWI Address/Stop Interrupt Flag
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.equ TWDIF = 7 ; TWI Data Interrupt Flag.
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; TWSA - TWI Slave Address Register
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.equ TWSA0 = 0 ; TWI slave address bit
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.equ TWSA1 = 1 ; TWI slave address bit
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.equ TWSA2 = 2 ; TWI slave address bit
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.equ TWSA3 = 3 ; TWI slave address bit
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.equ TWSA4 = 4 ; TWI slave address bit
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.equ TWSA5 = 5 ; TWI slave address bit
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.equ TWSA6 = 6 ; TWI slave address bit
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.equ TWSA7 = 7 ; TWI slave address bit
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; TWSD - TWI Slave Data Register
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.equ TWSD0 = 0 ; TWI slave data bit
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.equ TWSD1 = 1 ; TWI slave data bit
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.equ TWSD2 = 2 ; TWI slave data bit
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.equ TWSD3 = 3 ; TWI slave data bit
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.equ TWSD4 = 4 ; TWI slave data bit
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.equ TWSD5 = 5 ; TWI slave data bit
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.equ TWSD6 = 6 ; TWI slave data bit
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.equ TWSD7 = 7 ; TWI slave data bit
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; TWSAM - TWI Slave Address Mask Register
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.equ TWAE = 0 ; TWI Address Enable
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.equ TWSAM1 = 1 ; TWI Address Mask Bit 1
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.equ TWSAM2 = 2 ; TWI Address Mask Bit 2
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.equ TWSAM3 = 3 ; TWI Address Mask Bit 3
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.equ TWSAM4 = 4 ; TWI Address Mask Bit 4
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.equ TWSAM5 = 5 ; TWI Address Mask Bit 5
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.equ TWSAM6 = 6 ; TWI Address Mask Bit 6
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.equ TWSAM7 = 7 ; TWI Address Mask Bit 7
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|
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; ***** PORTA ************************
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; PORTCR - Port Control Register
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.equ BBMA = 0 ; Break-Before-Make Mode Enable
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; PUEA - Pull-up Enable Control Register
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.equ PUEA0 = 0 ;
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.equ PUEA1 = 1 ;
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.equ PUEA2 = 2 ;
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.equ PUEA3 = 3 ;
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.equ PUEA4 = 4 ;
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.equ PUEA5 = 5 ;
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.equ PUEA6 = 6 ;
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.equ PUEA7 = 7 ;
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; PORTA - Port A Data Register
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.equ PORTA0 = 0 ;
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.equ PA0 = 0 ; For compatibility
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.equ PORTA1 = 1 ;
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.equ PA1 = 1 ; For compatibility
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.equ PORTA2 = 2 ;
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.equ PA2 = 2 ; For compatibility
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.equ PORTA3 = 3 ;
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.equ PA3 = 3 ; For compatibility
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.equ PORTA4 = 4 ;
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.equ PA4 = 4 ; For compatibility
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.equ PORTA5 = 5 ;
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.equ PA5 = 5 ; For compatibility
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.equ PORTA6 = 6 ;
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.equ PA6 = 6 ; For compatibility
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.equ PORTA7 = 7 ;
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.equ PA7 = 7 ; For compatibility
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|
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; DDRA - Data Direction Register, Port A
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.equ DDA0 = 0 ;
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.equ DDA1 = 1 ;
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.equ DDA2 = 2 ;
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.equ DDA3 = 3 ;
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.equ DDA4 = 4 ;
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.equ DDA5 = 5 ;
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.equ DDA6 = 6 ;
|
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.equ DDA7 = 7 ;
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|
|
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; PINA - Port A Input Pins
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.equ PINA0 = 0 ;
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.equ PINA1 = 1 ;
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.equ PINA2 = 2 ;
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.equ PINA3 = 3 ;
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.equ PINA4 = 4 ;
|
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.equ PINA5 = 5 ;
|
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.equ PINA6 = 6 ;
|
|
.equ PINA7 = 7 ;
|
|
|
|
|
|
; ***** TIMER_COUNTER_1 **************
|
|
; TCCR1A - Timer/Counter1 Control Register A
|
|
.equ WGM10 = 0 ; Waveform Generation Mode Bit 0
|
|
.equ PWM10 = WGM10 ; For compatibility
|
|
.equ WGM11 = 1 ; Waveform Generation Mode Bit 1
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.equ PWM11 = WGM11 ; For compatibility
|
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.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0
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.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
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.equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0
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.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
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|
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; TCCR1B - Timer/Counter1 Control Register B
|
|
.equ CS10 = 0 ; Clock Select bit 0
|
|
.equ CS11 = 1 ; Clock Select 1 bit 1
|
|
.equ CS12 = 2 ; Clock Select1 bit 2
|
|
.equ WGM12 = 3 ; Waveform Generation Mode
|
|
.equ CTC10 = WGM12 ; For compatibility
|
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.equ WGM13 = 4 ; Waveform Generation Mode
|
|
.equ CTC11 = WGM13 ; For compatibility
|
|
.equ ICES1 = 6 ; Input Capture 1 Edge Select
|
|
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
|
|
|
|
; TCCR1C - Timer/Counter1 Control Register C
|
|
.equ FOC1B = 6 ; Force Output Compare for channel B
|
|
.equ FOC1A = 7 ; Force Output Compare for channel A
|
|
|
|
; TCNT1H - Timer/Counter1 High
|
|
.equ TCNT1_8 = 0 ;
|
|
.equ TCNT1_9 = 1 ;
|
|
.equ TCNT1_10 = 2 ;
|
|
.equ TCNT1_11 = 3 ;
|
|
.equ TCNT1_12 = 4 ;
|
|
.equ TCNT1_13 = 5 ;
|
|
.equ TCNT1_14 = 6 ;
|
|
.equ TCNT1_15 = 7 ;
|
|
|
|
; TCNT1L - Timer/Counter1 Low
|
|
.equ TCNT1_0 = 0 ;
|
|
.equ TCNT1_1 = 1 ;
|
|
.equ TCNT1_2 = 2 ;
|
|
.equ TCNT1_3 = 3 ;
|
|
.equ TCNT1_4 = 4 ;
|
|
.equ TCNT1_5 = 5 ;
|
|
.equ TCNT1_6 = 6 ;
|
|
.equ TCNT1_7 = 7 ;
|
|
|
|
; TIMSK - Timer Interrupt Mask Register
|
|
;.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
|
|
;.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable
|
|
;.equ OCIE0B = 2 ; Timer/Counter Output Compare Match B Interrupt Enable
|
|
;.equ TOIE1 = 3 ; Overflow Interrupt Enable
|
|
;.equ OCIE1A = 4 ; Output Compare A Match Interrupt Enable
|
|
;.equ OCIE1B = 5 ; Output Compare B Match Interrupt Enable
|
|
;.equ ICIE1 = 7 ; Input Capture Interrupt Enable
|
|
|
|
; TIFR - Overflow Interrupt Enable
|
|
;.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
|
|
;.equ OCF0A = 1 ; Output Compare Flag 0 A
|
|
;.equ OCF0B = 2 ; Output Compare Flag 0 B
|
|
;.equ TOV1 = 3 ; Timer Overflow Flag
|
|
;.equ OCF1A = 4 ; Timer Output Compare Flag 1A
|
|
;.equ OCF1B = 5 ; Timer Output Compare Flag 1B
|
|
;.equ ICF1 = 7 ; Input Capture Flag
|
|
|
|
; GTCCR - General Timer/Counter Control Register
|
|
;.equ PSR = 0 ; Prescaler Reset
|
|
;.equ TSM = 7 ; Timer Synchronization Mode
|
|
|
|
|
|
; ***** SPI **************************
|
|
; SPDR - SPI Data Register
|
|
.equ SPDR0 = 0 ; SPI Data Register bit 0
|
|
.equ SPDR1 = 1 ; SPI Data Register bit 1
|
|
.equ SPDR2 = 2 ; SPI Data Register bit 2
|
|
.equ SPDR3 = 3 ; SPI Data Register bit 3
|
|
.equ SPDR4 = 4 ; SPI Data Register bit 4
|
|
.equ SPDR5 = 5 ; SPI Data Register bit 5
|
|
.equ SPDR6 = 6 ; SPI Data Register bit 6
|
|
.equ SPDR7 = 7 ; SPI Data Register bit 7
|
|
|
|
; SPSR - SPI Status Register
|
|
.equ SPI2X = 0 ; Double SPI Speed Bit
|
|
.equ WCOL = 6 ; Write Collision Flag
|
|
.equ SPIF = 7 ; SPI Interrupt Flag
|
|
|
|
; SPCR - SPI Control Register
|
|
.equ SPR0 = 0 ; SPI Clock Rate Select 0
|
|
.equ SPR1 = 1 ; SPI Clock Rate Select 1
|
|
.equ CPHA = 2 ; Clock Phase
|
|
.equ CPOL = 3 ; Clock polarity
|
|
.equ MSTR = 4 ; Master/Slave Select
|
|
.equ DORD = 5 ; Data Order
|
|
.equ SPE = 6 ; SPI Enable
|
|
.equ SPIE = 7 ; SPI Interrupt Enable
|
|
|
|
|
|
|
|
; ***** LOCKSBITS ********************************************************
|
|
.equ LB1 = 0 ; Lockbit
|
|
.equ LB2 = 1 ; Lockbit
|
|
|
|
|
|
; ***** FUSES ************************************************************
|
|
; BYTE0 fuse bits
|
|
.equ RSTDISBL = 0 ; Disable external reset
|
|
.equ WDTON = 1 ; Watch dog timer always on
|
|
.equ CKOUT = 2 ; Output external clock
|
|
.equ BODLEVEL0 = 4 ; Brown-out Detector trigger level
|
|
.equ BODLEVEL1 = 5 ; Brown-out Detector trigger level
|
|
.equ BODLEVEL2 = 6 ; Brown-out Detector trigger level
|
|
|
|
|
|
|
|
; ***** CPU REGISTER DEFINITIONS *****************************************
|
|
.def XH = r27
|
|
.def XL = r26
|
|
.def YH = r29
|
|
.def YL = r28
|
|
.def ZH = r31
|
|
.def ZL = r30
|
|
|
|
|
|
|
|
; ***** DATA MEMORY DECLARATIONS *****************************************
|
|
.equ FLASHEND = 0x03ff ; Note: Word address
|
|
.equ IOEND = 0x003f
|
|
.equ SRAM_START = 0x0040
|
|
.equ SRAM_SIZE = 128
|
|
.equ RAMEND = 0x00bf
|
|
.equ XRAMEND = 0x0000
|
|
.equ E2END = 0x0000
|
|
.equ EEPROMEND = 0x0000
|
|
|
|
; ***** MEMORY MAPPED NVM ************************************************
|
|
.equ MAPPED_FLASH_START = 0x4000
|
|
.equ MAPPED_LOCKBITS_0 = 0x3f00
|
|
.equ MAPPED_CONFIG_0 = 0x3f40
|
|
.equ MAPPED_CALIB_0 = 0x3f80
|
|
.equ MAPPED_SIGN_0 = 0x3fc0
|
|
.equ MAPPED_SIGN_1 = 0x3fc1
|
|
.equ MAPPED_SIGN_2 = 0x3fc2
|
|
.equ MAPPED_FLASH_SIZE = 0x0800
|
|
.equ MAPPED_FLASH_END = 0x47ff
|
|
#pragma AVRPART MEMORY PROG_FLASH 2048
|
|
#pragma AVRPART MEMORY EEPROM 0
|
|
#pragma AVRPART MEMORY INT_SRAM SIZE 128
|
|
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x40
|
|
|
|
|
|
|
|
; ***** BOOTLOADER DECLARATIONS ******************************************
|
|
.equ PAGESIZE = 32
|
|
|
|
|
|
|
|
; ***** INTERRUPT VECTORS ************************************************
|
|
.equ INT0addr = 0x0001 ; External Interrupt Request 0
|
|
.equ PCI0addr = 0x0002 ; Pin Change Interrupt Request 0
|
|
.equ PCI1addr = 0x0003 ; Pin Change Interrupt Request 1
|
|
.equ WDTaddr = 0x0004 ; Watchdog Time-out
|
|
.equ ICP1addr = 0x0005 ; Timer/Counter1 Input Capture
|
|
.equ OC1Aaddr = 0x0006 ; Timer/Counter1 Compare Match A
|
|
.equ OC1Baddr = 0x0007 ; Timer/Counter1 Compare Match B
|
|
.equ OVF1addr = 0x0008 ; Timer/Counter1 Overflow
|
|
.equ OC0Aaddr = 0x0009 ; Timer/Counter0 Compare Match A
|
|
.equ OC0Baddr = 0x000a ; Timer/Counter0 Compare Match B
|
|
.equ OVF0addr = 0x000b ; Timer/Counter0 Overflow
|
|
.equ ACIaddr = 0x000c ; Analog Comparator
|
|
.equ ADCCaddr = 0x000d ; Conversion Complete
|
|
.equ TWIaddr = 0x000e ; Two-Wire Interface
|
|
.equ SPIaddr = 0x000f ; Serial Peripheral Interface
|
|
.equ QTRIPaddr = 0x0010 ; Touch Sensing
|
|
|
|
.equ INT_VECTORS_SIZE = 17 ; size in words
|
|
|
|
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
|
|
|
|
#endif /* _TN20DEF_INC_ */
|
|
|
|
; ***** END OF FILE ******************************************************
|