1000 lines
32 KiB
PHP
Executable File
1000 lines
32 KiB
PHP
Executable File
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
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;***** Created: 2011-02-09 12:03 ******* Source: ATmega8U2.xml ***********
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;*************************************************************************
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;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
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;*
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;* Number : AVR000
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;* File Name : "m8U2def.inc"
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;* Title : Register/Bit Definitions for the ATmega8U2
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;* Date : 2011-02-09
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;* Version : 2.35
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;* Support E-mail : avr@atmel.com
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;* Target MCU : ATmega8U2
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;*
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;* DESCRIPTION
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;* When including this file in the assembly program file, all I/O register
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;* names and I/O register bit names appearing in the data book can be used.
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;* In addition, the six registers forming the three data pointers X, Y and
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;* Z have been assigned names XL - ZH. Highest RAM address for Internal
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;* SRAM is also defined
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;*
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;* The Register names are represented by their hexadecimal address.
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;*
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;* The Register Bit names are represented by their bit number (0-7).
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;*
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;* Please observe the difference in using the bit names with instructions
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;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
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;* (skip if bit in register set/cleared). The following example illustrates
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;* this:
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;*
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;* in r16,PORTB ;read PORTB latch
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;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
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;* out PORTB,r16 ;output to PORTB
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;*
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;* in r16,TIFR ;read the Timer Interrupt Flag Register
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;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
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;* rjmp TOV0_is_set ;jump if set
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;* ... ;otherwise do something else
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;*************************************************************************
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#ifndef _M8U2DEF_INC_
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#define _M8U2DEF_INC_
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#pragma partinc 0
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; ***** SPECIFY DEVICE ***************************************************
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.device ATmega8U2
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#pragma AVRPART ADMIN PART_NAME ATmega8U2
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.equ SIGNATURE_000 = 0x1e
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.equ SIGNATURE_001 = 0x93
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.equ SIGNATURE_002 = 0x89
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#pragma AVRPART CORE CORE_VERSION V3
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; ***** I/O REGISTER DEFINITIONS *****************************************
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; NOTE:
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; Definitions marked "MEMORY MAPPED"are extended I/O ports
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; and cannot be used with IN/OUT instructions
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.equ CLKSTA = 0xd2 ; MEMORY MAPPED
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.equ CLKSEL1 = 0xd1 ; MEMORY MAPPED
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.equ CLKSEL0 = 0xd0 ; MEMORY MAPPED
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.equ PLLCSR = 0x29
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.equ UEINT = 0xf4 ; MEMORY MAPPED
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.equ UEBCLX = 0xf2 ; MEMORY MAPPED
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.equ UEDATX = 0xf1 ; MEMORY MAPPED
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.equ UEIENX = 0xf0 ; MEMORY MAPPED
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.equ UESTA1X = 0xef ; MEMORY MAPPED
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.equ UESTA0X = 0xee ; MEMORY MAPPED
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.equ UECFG1X = 0xed ; MEMORY MAPPED
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.equ UECFG0X = 0xec ; MEMORY MAPPED
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.equ UECONX = 0xeb ; MEMORY MAPPED
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.equ UERST = 0xea ; MEMORY MAPPED
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.equ UENUM = 0xe9 ; MEMORY MAPPED
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.equ UEINTX = 0xe8 ; MEMORY MAPPED
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.equ UDMFN = 0xe6 ; MEMORY MAPPED
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.equ UDFNUMH = 0xe5 ; MEMORY MAPPED
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.equ UDFNUML = 0xe4 ; MEMORY MAPPED
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.equ UDADDR = 0xe3 ; MEMORY MAPPED
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.equ UDIEN = 0xe2 ; MEMORY MAPPED
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.equ UDINT = 0xe1 ; MEMORY MAPPED
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.equ UDCON = 0xe0 ; MEMORY MAPPED
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.equ USBCON = 0xd8 ; MEMORY MAPPED
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.equ REGCR = 0x63 ; MEMORY MAPPED
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.equ UDR1 = 0xce ; MEMORY MAPPED
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.equ UBRR1L = 0xcc ; MEMORY MAPPED
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.equ UBRR1H = 0xcd ; MEMORY MAPPED
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.equ UCSR1D = 0xcb ; MEMORY MAPPED
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.equ UCSR1C = 0xca ; MEMORY MAPPED
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.equ UCSR1B = 0xc9 ; MEMORY MAPPED
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.equ UCSR1A = 0xc8 ; MEMORY MAPPED
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.equ OCR1CL = 0x8c ; MEMORY MAPPED
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.equ OCR1CH = 0x8d ; MEMORY MAPPED
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.equ OCR1BL = 0x8a ; MEMORY MAPPED
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.equ OCR1BH = 0x8b ; MEMORY MAPPED
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.equ OCR1AL = 0x88 ; MEMORY MAPPED
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.equ OCR1AH = 0x89 ; MEMORY MAPPED
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.equ ICR1L = 0x86 ; MEMORY MAPPED
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.equ ICR1H = 0x87 ; MEMORY MAPPED
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.equ TCNT1L = 0x84 ; MEMORY MAPPED
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.equ TCNT1H = 0x85 ; MEMORY MAPPED
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.equ TCCR1C = 0x82 ; MEMORY MAPPED
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.equ TCCR1B = 0x81 ; MEMORY MAPPED
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.equ TCCR1A = 0x80 ; MEMORY MAPPED
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.equ DIDR1 = 0x7f ; MEMORY MAPPED
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.equ TIMSK1 = 0x6f ; MEMORY MAPPED
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.equ TIMSK0 = 0x6e ; MEMORY MAPPED
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.equ PCMSK1 = 0x6c ; MEMORY MAPPED
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.equ PCMSK0 = 0x6b ; MEMORY MAPPED
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.equ EICRB = 0x6a ; MEMORY MAPPED
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.equ EICRA = 0x69 ; MEMORY MAPPED
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.equ PCICR = 0x68 ; MEMORY MAPPED
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.equ OSCCAL = 0x66 ; MEMORY MAPPED
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.equ PRR1 = 0x65 ; MEMORY MAPPED
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.equ PRR0 = 0x64 ; MEMORY MAPPED
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.equ CLKPR = 0x61 ; MEMORY MAPPED
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.equ WDTCSR = 0x60 ; MEMORY MAPPED
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.equ WDTCKD = 0x62 ; MEMORY MAPPED
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.equ SREG = 0x3f
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.equ SPL = 0x3d
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.equ SPH = 0x3e
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.equ EIND = 0x3c
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.equ SPMCSR = 0x37
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.equ DWDR = 0x31
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.equ MCUCR = 0x35
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.equ MCUSR = 0x34
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.equ SMCR = 0x33
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.equ ACSR = 0x30
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.equ SPDR = 0x2e
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.equ SPSR = 0x2d
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.equ SPCR = 0x2c
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.equ GPIOR2 = 0x2b
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.equ GPIOR1 = 0x2a
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.equ OCR0B = 0x28
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.equ OCR0A = 0x27
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.equ TCNT0 = 0x26
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.equ TCCR0B = 0x25
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.equ TCCR0A = 0x24
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.equ GTCCR = 0x23
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.equ EEARH = 0x22
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.equ EEARL = 0x21
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.equ EEDR = 0x20
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.equ EECR = 0x1f
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.equ GPIOR0 = 0x1e
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.equ EIMSK = 0x1d
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.equ EIFR = 0x1c
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.equ PCIFR = 0x1b
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.equ TIFR1 = 0x16
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.equ TIFR0 = 0x15
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.equ PORTD = 0x0b
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.equ DDRD = 0x0a
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.equ PIND = 0x09
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.equ PORTC = 0x08
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.equ DDRC = 0x07
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.equ PINC = 0x06
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.equ PORTB = 0x05
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.equ DDRB = 0x04
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.equ PINB = 0x03
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; ***** BIT DEFINITIONS **************************************************
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; ***** PORTB ************************
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; PORTB - Port B Data Register
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.equ PORTB0 = 0 ; Port B Data Register bit 0
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.equ PB0 = 0 ; For compatibility
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.equ PORTB1 = 1 ; Port B Data Register bit 1
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.equ PB1 = 1 ; For compatibility
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.equ PORTB2 = 2 ; Port B Data Register bit 2
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.equ PB2 = 2 ; For compatibility
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.equ PORTB3 = 3 ; Port B Data Register bit 3
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.equ PB3 = 3 ; For compatibility
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.equ PORTB4 = 4 ; Port B Data Register bit 4
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.equ PB4 = 4 ; For compatibility
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.equ PORTB5 = 5 ; Port B Data Register bit 5
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.equ PB5 = 5 ; For compatibility
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.equ PORTB6 = 6 ; Port B Data Register bit 6
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.equ PB6 = 6 ; For compatibility
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.equ PORTB7 = 7 ; Port B Data Register bit 7
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.equ PB7 = 7 ; For compatibility
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; DDRB - Port B Data Direction Register
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.equ DDB0 = 0 ; Port B Data Direction Register bit 0
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.equ DDB1 = 1 ; Port B Data Direction Register bit 1
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.equ DDB2 = 2 ; Port B Data Direction Register bit 2
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.equ DDB3 = 3 ; Port B Data Direction Register bit 3
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.equ DDB4 = 4 ; Port B Data Direction Register bit 4
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.equ DDB5 = 5 ; Port B Data Direction Register bit 5
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.equ DDB6 = 6 ; Port B Data Direction Register bit 6
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.equ DDB7 = 7 ; Port B Data Direction Register bit 7
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; PINB - Port B Input Pins
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.equ PINB0 = 0 ; Port B Input Pins bit 0
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.equ PINB1 = 1 ; Port B Input Pins bit 1
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.equ PINB2 = 2 ; Port B Input Pins bit 2
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.equ PINB3 = 3 ; Port B Input Pins bit 3
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.equ PINB4 = 4 ; Port B Input Pins bit 4
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.equ PINB5 = 5 ; Port B Input Pins bit 5
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.equ PINB6 = 6 ; Port B Input Pins bit 6
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.equ PINB7 = 7 ; Port B Input Pins bit 7
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; ***** PORTD ************************
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; PORTD - Port D Data Register
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.equ PORTD0 = 0 ; Port D Data Register bit 0
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.equ PD0 = 0 ; For compatibility
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.equ PORTD1 = 1 ; Port D Data Register bit 1
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.equ PD1 = 1 ; For compatibility
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.equ PORTD2 = 2 ; Port D Data Register bit 2
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.equ PD2 = 2 ; For compatibility
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.equ PORTD3 = 3 ; Port D Data Register bit 3
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.equ PD3 = 3 ; For compatibility
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.equ PORTD4 = 4 ; Port D Data Register bit 4
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.equ PD4 = 4 ; For compatibility
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.equ PORTD5 = 5 ; Port D Data Register bit 5
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.equ PD5 = 5 ; For compatibility
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.equ PORTD6 = 6 ; Port D Data Register bit 6
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.equ PD6 = 6 ; For compatibility
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.equ PORTD7 = 7 ; Port D Data Register bit 7
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.equ PD7 = 7 ; For compatibility
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; DDRD - Port D Data Direction Register
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.equ DDD0 = 0 ; Port D Data Direction Register bit 0
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.equ DDD1 = 1 ; Port D Data Direction Register bit 1
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.equ DDD2 = 2 ; Port D Data Direction Register bit 2
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.equ DDD3 = 3 ; Port D Data Direction Register bit 3
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.equ DDD4 = 4 ; Port D Data Direction Register bit 4
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.equ DDD5 = 5 ; Port D Data Direction Register bit 5
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.equ DDD6 = 6 ; Port D Data Direction Register bit 6
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.equ DDD7 = 7 ; Port D Data Direction Register bit 7
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; PIND - Port D Input Pins
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.equ PIND0 = 0 ; Port D Input Pins bit 0
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.equ PIND1 = 1 ; Port D Input Pins bit 1
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.equ PIND2 = 2 ; Port D Input Pins bit 2
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.equ PIND3 = 3 ; Port D Input Pins bit 3
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.equ PIND4 = 4 ; Port D Input Pins bit 4
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.equ PIND5 = 5 ; Port D Input Pins bit 5
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.equ PIND6 = 6 ; Port D Input Pins bit 6
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.equ PIND7 = 7 ; Port D Input Pins bit 7
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; ***** SPI **************************
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; SPDR - SPI Data Register
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.equ SPDR0 = 0 ; SPI Data Register bit 0
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.equ SPDR1 = 1 ; SPI Data Register bit 1
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.equ SPDR2 = 2 ; SPI Data Register bit 2
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.equ SPDR3 = 3 ; SPI Data Register bit 3
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.equ SPDR4 = 4 ; SPI Data Register bit 4
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.equ SPDR5 = 5 ; SPI Data Register bit 5
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.equ SPDR6 = 6 ; SPI Data Register bit 6
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.equ SPDR7 = 7 ; SPI Data Register bit 7
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; SPSR - SPI Status Register
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.equ SPI2X = 0 ; Double SPI Speed Bit
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.equ WCOL = 6 ; Write Collision Flag
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.equ SPIF = 7 ; SPI Interrupt Flag
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; SPCR - SPI Control Register
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.equ SPR0 = 0 ; SPI Clock Rate Select 0
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.equ SPR1 = 1 ; SPI Clock Rate Select 1
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.equ CPHA = 2 ; Clock Phase
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.equ CPOL = 3 ; Clock polarity
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.equ MSTR = 4 ; Master/Slave Select
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.equ DORD = 5 ; Data Order
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.equ SPE = 6 ; SPI Enable
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.equ SPIE = 7 ; SPI Interrupt Enable
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; ***** BOOT_LOAD ********************
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; SPMCSR - Store Program Memory Control Register
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.equ SPMEN = 0 ; Store Program Memory Enable
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.equ PGERS = 1 ; Page Erase
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.equ PGWRT = 2 ; Page Write
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.equ BLBSET = 3 ; Boot Lock Bit Set
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.equ RWWSRE = 4 ; Read While Write section read enable
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.equ SIGRD = 5 ; Signature Row Read
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.equ RWWSB = 6 ; Read While Write Section Busy
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.equ SPMIE = 7 ; SPM Interrupt Enable
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; ***** EEPROM ***********************
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; EEARH - EEPROM Address Register Low Byte
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.equ EEAR8 = 0 ; EEPROM Read/Write Access Bit 8
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.equ EEAR9 = 1 ; EEPROM Read/Write Access Bit 9
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.equ EEAR10 = 2 ; EEPROM Read/Write Access Bit 10
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.equ EEAR11 = 3 ; EEPROM Read/Write Access Bit 11
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; EEARL - EEPROM Address Register Low Byte
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.equ EEAR0 = 0 ; EEPROM Read/Write Access Bit 0
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.equ EEAR1 = 1 ; EEPROM Read/Write Access Bit 1
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.equ EEAR2 = 2 ; EEPROM Read/Write Access Bit 2
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.equ EEAR3 = 3 ; EEPROM Read/Write Access Bit 3
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.equ EEAR4 = 4 ; EEPROM Read/Write Access Bit 4
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.equ EEAR5 = 5 ; EEPROM Read/Write Access Bit 5
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.equ EEAR6 = 6 ; EEPROM Read/Write Access Bit 6
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.equ EEAR7 = 7 ; EEPROM Read/Write Access Bit 7
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; EEDR - EEPROM Data Register
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.equ EEDR0 = 0 ; EEPROM Data Register bit 0
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.equ EEDR1 = 1 ; EEPROM Data Register bit 1
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.equ EEDR2 = 2 ; EEPROM Data Register bit 2
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.equ EEDR3 = 3 ; EEPROM Data Register bit 3
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.equ EEDR4 = 4 ; EEPROM Data Register bit 4
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.equ EEDR5 = 5 ; EEPROM Data Register bit 5
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.equ EEDR6 = 6 ; EEPROM Data Register bit 6
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.equ EEDR7 = 7 ; EEPROM Data Register bit 7
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; EECR - EEPROM Control Register
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.equ EERE = 0 ; EEPROM Read Enable
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.equ EEPE = 1 ; EEPROM Write Enable
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.equ EEMPE = 2 ; EEPROM Master Write Enable
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.equ EERIE = 3 ; EEPROM Ready Interrupt Enable
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.equ EEPM0 = 4 ; EEPROM Programming Mode Bit 0
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.equ EEPM1 = 5 ; EEPROM Programming Mode Bit 1
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; ***** TIMER_COUNTER_0 **************
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; TIMSK0 - Timer/Counter0 Interrupt Mask Register
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.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
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.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable
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.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable
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; TIFR0 - Timer/Counter0 Interrupt Flag register
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.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
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.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0A
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.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B
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; TCCR0A - Timer/Counter Control Register A
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.equ WGM00 = 0 ; Waveform Generation Mode
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.equ WGM01 = 1 ; Waveform Generation Mode
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.equ COM0B0 = 4 ; Compare Output Mode, Fast PWm
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.equ COM0B1 = 5 ; Compare Output Mode, Fast PWm
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.equ COM0A0 = 6 ; Compare Output Mode, Phase Correct PWM Mode
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.equ COM0A1 = 7 ; Compare Output Mode, Phase Correct PWM Mode
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; TCCR0B - Timer/Counter Control Register B
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.equ CS00 = 0 ; Clock Select
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.equ CS01 = 1 ; Clock Select
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.equ CS02 = 2 ; Clock Select
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.equ WGM02 = 3 ;
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.equ FOC0B = 6 ; Force Output Compare B
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.equ FOC0A = 7 ; Force Output Compare A
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; TCNT0 - Timer/Counter0
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.equ TCNT0_0 = 0 ;
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.equ TCNT0_1 = 1 ;
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.equ TCNT0_2 = 2 ;
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.equ TCNT0_3 = 3 ;
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.equ TCNT0_4 = 4 ;
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.equ TCNT0_5 = 5 ;
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.equ TCNT0_6 = 6 ;
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.equ TCNT0_7 = 7 ;
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; OCR0A - Timer/Counter0 Output Compare Register
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.equ OCR0A_0 = 0 ;
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.equ OCR0A_1 = 1 ;
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.equ OCR0A_2 = 2 ;
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.equ OCR0A_3 = 3 ;
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.equ OCR0A_4 = 4 ;
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.equ OCR0A_5 = 5 ;
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.equ OCR0A_6 = 6 ;
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.equ OCR0A_7 = 7 ;
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; OCR0B - Timer/Counter0 Output Compare Register
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.equ OCR0B_0 = 0 ;
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.equ OCR0B_1 = 1 ;
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.equ OCR0B_2 = 2 ;
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.equ OCR0B_3 = 3 ;
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.equ OCR0B_4 = 4 ;
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.equ OCR0B_5 = 5 ;
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.equ OCR0B_6 = 6 ;
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.equ OCR0B_7 = 7 ;
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; GTCCR - General Timer/Counter Control Register
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.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0
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.equ PSR10 = PSRSYNC ; For compatibility
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.equ TSM = 7 ; Timer/Counter Synchronization Mode
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; ***** TIMER_COUNTER_1 **************
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; TIMSK1 - Timer/Counter1 Interrupt Mask Register
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.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable
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.equ OCIE1A = 1 ; Timer/Counter1 Output Compare A Match Interrupt Enable
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.equ OCIE1B = 2 ; Timer/Counter1 Output Compare B Match Interrupt Enable
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.equ OCIE1C = 3 ; Timer/Counter1 Output Compare C Match Interrupt Enable
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.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable
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; TIFR1 - Timer/Counter1 Interrupt Flag register
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.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag
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.equ OCF1A = 1 ; Output Compare Flag 1A
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.equ OCF1B = 2 ; Output Compare Flag 1B
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.equ OCF1C = 3 ; Output Compare Flag 1C
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.equ ICF1 = 5 ; Input Capture Flag 1
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; TCCR1A - Timer/Counter1 Control Register A
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.equ WGM10 = 0 ; Waveform Generation Mode
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.equ WGM11 = 1 ; Waveform Generation Mode
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.equ COM1C0 = 2 ; Compare Output Mode 1C, bit 0
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.equ COM1C1 = 3 ; Compare Output Mode 1C, bit 1
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.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0
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.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
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.equ COM1A0 = 6 ; Compare Output Mode 1A, bit 0
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.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
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; TCCR1B - Timer/Counter1 Control Register B
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.equ CS10 = 0 ; Prescaler source of Timer/Counter 1
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.equ CS11 = 1 ; Prescaler source of Timer/Counter 1
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.equ CS12 = 2 ; Prescaler source of Timer/Counter 1
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.equ WGM12 = 3 ; Waveform Generation Mode
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.equ WGM13 = 4 ; Waveform Generation Mode
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.equ ICES1 = 6 ; Input Capture 1 Edge Select
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.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
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; TCCR1C - Timer/Counter 1 Control Register C
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.equ FOC1C = 5 ; Force Output Compare 1C
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.equ FOC1B = 6 ; Force Output Compare 1B
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.equ FOC1A = 7 ; Force Output Compare 1A
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; ***** PLL **************************
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; PLLCSR - PLL Status and Control register
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.equ PLOCK = 0 ; PLL Lock Status Bit
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.equ PLLE = 1 ; PLL Enable Bit
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.equ PLLP0 = 2 ; PLL prescaler Bit 0
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|
.equ PLLP1 = 3 ; PLL prescaler Bit 1
|
|
.equ PLLP2 = 4 ; PLL prescaler Bit 2
|
|
|
|
|
|
; ***** USB_DEVICE *******************
|
|
; USBCON - USB General Control Register
|
|
.equ FRZCLK = 5 ;
|
|
.equ USBE = 7 ;
|
|
|
|
; UDCON -
|
|
.equ DETACH = 0 ;
|
|
.equ RMWKUP = 1 ;
|
|
.equ RSTCPU = 2 ;
|
|
|
|
; UDINT -
|
|
.equ SUSPI = 0 ;
|
|
.equ SOFI = 2 ;
|
|
.equ EORSTI = 3 ;
|
|
.equ WAKEUPI = 4 ;
|
|
.equ EORSMI = 5 ;
|
|
.equ UPRSMI = 6 ;
|
|
|
|
; UDIEN -
|
|
.equ SUSPE = 0 ;
|
|
.equ SOFE = 2 ;
|
|
.equ EORSTE = 3 ;
|
|
.equ WAKEUPE = 4 ;
|
|
.equ EORSME = 5 ;
|
|
.equ UPRSME = 6 ;
|
|
|
|
; UDADDR -
|
|
.equ UADD0 = 0 ;
|
|
.equ UADD1 = 1 ;
|
|
.equ UADD2 = 2 ;
|
|
.equ UADD3 = 3 ;
|
|
.equ UADD4 = 4 ;
|
|
.equ UADD5 = 5 ;
|
|
.equ UADD6 = 6 ;
|
|
.equ ADDEN = 7 ;
|
|
|
|
; UDFNUML -
|
|
.equ FNUM0 = 0 ;
|
|
.equ FNUM1 = 1 ;
|
|
.equ FNUM2 = 2 ;
|
|
.equ FNUM3 = 3 ;
|
|
.equ FNUM4 = 4 ;
|
|
.equ FNUM5 = 5 ;
|
|
.equ FNUM6 = 6 ;
|
|
.equ FNUM7 = 7 ;
|
|
|
|
; UDFNUMH -
|
|
.equ FNUM8 = 0 ;
|
|
.equ FNUM9 = 1 ;
|
|
.equ FNUM10 = 2 ;
|
|
|
|
; UDMFN -
|
|
.equ FNCERR = 4 ;
|
|
|
|
; UEINTX -
|
|
.equ TXINI = 0 ;
|
|
.equ STALLEDI = 1 ;
|
|
.equ RXOUTI = 2 ;
|
|
.equ RXSTPI = 3 ;
|
|
.equ NAKOUTI = 4 ;
|
|
.equ RWAL = 5 ;
|
|
.equ NAKINI = 6 ;
|
|
.equ FIFOCON = 7 ;
|
|
|
|
; UENUM -
|
|
.equ EPNUM0 = 0 ;
|
|
.equ EPNUM1 = 1 ;
|
|
.equ EPNUM2 = 2 ;
|
|
|
|
; UERST -
|
|
.equ EPRST0 = 0 ;
|
|
.equ EPRST1 = 1 ;
|
|
.equ EPRST2 = 2 ;
|
|
.equ EPRST3 = 3 ;
|
|
.equ EPRST4 = 4 ;
|
|
|
|
; UECONX -
|
|
.equ EPEN = 0 ;
|
|
.equ RSTDT = 3 ;
|
|
.equ STALLRQC = 4 ;
|
|
.equ STALLRQ = 5 ;
|
|
|
|
; UECFG0X -
|
|
.equ EPDIR = 0 ;
|
|
.equ EPTYPE0 = 6 ;
|
|
.equ EPTYPE1 = 7 ;
|
|
|
|
; UECFG1X -
|
|
.equ ALLOC = 1 ;
|
|
.equ EPBK0 = 2 ;
|
|
.equ EPBK1 = 3 ;
|
|
.equ EPSIZE0 = 4 ;
|
|
.equ EPSIZE1 = 5 ;
|
|
.equ EPSIZE2 = 6 ;
|
|
|
|
; UESTA0X -
|
|
.equ NBUSYBK0 = 0 ;
|
|
.equ NBUSYBK1 = 1 ;
|
|
.equ DTSEQ0 = 2 ;
|
|
.equ DTSEQ1 = 3 ;
|
|
.equ UNDERFI = 5 ;
|
|
.equ OVERFI = 6 ;
|
|
.equ CFGOK = 7 ;
|
|
|
|
; UESTA1X -
|
|
.equ CURRBK0 = 0 ;
|
|
.equ CURRBK1 = 1 ;
|
|
.equ CTRLDIR = 2 ;
|
|
|
|
; UEIENX -
|
|
.equ TXINE = 0 ;
|
|
.equ STALLEDE = 1 ;
|
|
.equ RXOUTE = 2 ;
|
|
.equ RXSTPE = 3 ;
|
|
.equ NAKOUTE = 4 ;
|
|
.equ NAKINE = 6 ;
|
|
.equ FLERRE = 7 ;
|
|
|
|
; UEDATX -
|
|
.equ DAT0 = 0 ;
|
|
.equ DAT1 = 1 ;
|
|
.equ DAT2 = 2 ;
|
|
.equ DAT3 = 3 ;
|
|
.equ DAT4 = 4 ;
|
|
.equ DAT5 = 5 ;
|
|
.equ DAT6 = 6 ;
|
|
.equ DAT7 = 7 ;
|
|
|
|
; UEBCLX -
|
|
.equ BYCT0 = 0 ;
|
|
.equ BYCT1 = 1 ;
|
|
.equ BYCT2 = 2 ;
|
|
.equ BYCT3 = 3 ;
|
|
.equ BYCT4 = 4 ;
|
|
.equ BYCT5 = 5 ;
|
|
.equ BYCT6 = 6 ;
|
|
.equ BYCT7 = 7 ;
|
|
|
|
; UEINT -
|
|
.equ EPINT0 = 0 ;
|
|
.equ EPINT1 = 1 ;
|
|
.equ EPINT2 = 2 ;
|
|
.equ EPINT3 = 3 ;
|
|
.equ EPINT4 = 4 ;
|
|
|
|
; REGCR - Regulator Control Register
|
|
.equ REGDIS = 0 ;
|
|
|
|
|
|
; ***** CPU **************************
|
|
; SREG - Status Register
|
|
.equ SREG_C = 0 ; Carry Flag
|
|
.equ SREG_Z = 1 ; Zero Flag
|
|
.equ SREG_N = 2 ; Negative Flag
|
|
.equ SREG_V = 3 ; Two's Complement Overflow Flag
|
|
.equ SREG_S = 4 ; Sign Bit
|
|
.equ SREG_H = 5 ; Half Carry Flag
|
|
.equ SREG_T = 6 ; Bit Copy Storage
|
|
.equ SREG_I = 7 ; Global Interrupt Enable
|
|
|
|
; MCUCR - MCU Control Register
|
|
.equ IVCE = 0 ; Interrupt Vector Change Enable
|
|
.equ IVSEL = 1 ; Interrupt Vector Select
|
|
.equ PUD = 4 ; Pull-up disable
|
|
|
|
; MCUSR - MCU Status Register
|
|
.equ PORF = 0 ; Power-on reset flag
|
|
.equ EXTRF = 1 ; External Reset Flag
|
|
.equ BORF = 2 ; Brown-out Reset Flag
|
|
.equ WDRF = 3 ; Watchdog Reset Flag
|
|
.equ USBRF = 5 ; USB reset flag
|
|
|
|
; OSCCAL - Oscillator Calibration Value
|
|
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0
|
|
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1
|
|
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2
|
|
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3
|
|
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4
|
|
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5
|
|
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6
|
|
.equ CAL7 = 7 ; Oscillator Calibration Value Bit7
|
|
|
|
; CLKPR -
|
|
.equ CLKPS0 = 0 ;
|
|
.equ CLKPS1 = 1 ;
|
|
.equ CLKPS2 = 2 ;
|
|
.equ CLKPS3 = 3 ;
|
|
.equ CLKPCE = 7 ;
|
|
|
|
; SMCR - Sleep Mode Control Register
|
|
.equ SE = 0 ; Sleep Enable
|
|
.equ SM0 = 1 ; Sleep Mode Select bit 0
|
|
.equ SM1 = 2 ; Sleep Mode Select bit 1
|
|
.equ SM2 = 3 ; Sleep Mode Select bit 2
|
|
|
|
; EIND - Extended Indirect Register
|
|
.equ EIND0 = 0 ; Bit 0
|
|
|
|
; GPIOR2 - General Purpose IO Register 2
|
|
.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0
|
|
.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1
|
|
.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2
|
|
.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3
|
|
.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4
|
|
.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5
|
|
.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6
|
|
.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7
|
|
|
|
; GPIOR1 - General Purpose IO Register 1
|
|
.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0
|
|
.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1
|
|
.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2
|
|
.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3
|
|
.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4
|
|
.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5
|
|
.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6
|
|
.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7
|
|
|
|
; GPIOR0 - General Purpose IO Register 0
|
|
.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0
|
|
.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1
|
|
.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2
|
|
.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3
|
|
.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4
|
|
.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5
|
|
.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6
|
|
.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7
|
|
|
|
; PRR1 - Power Reduction Register1
|
|
.equ PRUSART1 = 0 ; Power Reduction USART1
|
|
.equ PRUSB = 7 ; Power Reduction USB
|
|
|
|
; PRR0 - Power Reduction Register0
|
|
.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface
|
|
.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1
|
|
.equ PRTIM0 = 5 ; Power Reduction Timer/Counter0
|
|
|
|
; CLKSTA -
|
|
.equ EXTON = 0 ;
|
|
.equ RCON = 1 ;
|
|
|
|
; CLKSEL1 -
|
|
.equ EXCKSEL0 = 0 ;
|
|
.equ EXCKSEL1 = 1 ;
|
|
.equ EXCKSEL2 = 2 ;
|
|
.equ EXCKSEL3 = 3 ;
|
|
.equ RCCKSEL0 = 4 ;
|
|
.equ RCCKSEL1 = 5 ;
|
|
.equ RCCKSEL2 = 6 ;
|
|
.equ RCCKSEL3 = 7 ;
|
|
|
|
; CLKSEL0 -
|
|
.equ CLKS = 0 ;
|
|
.equ EXTE = 2 ;
|
|
.equ RCE = 3 ;
|
|
.equ EXSUT0 = 4 ;
|
|
.equ EXSUT1 = 5 ;
|
|
.equ RCSUT0 = 6 ;
|
|
.equ RCSUT1 = 7 ;
|
|
|
|
; DWDR - debugWire communication register
|
|
.equ DWDR0 = 0 ;
|
|
.equ DWDR1 = 1 ;
|
|
.equ DWDR2 = 2 ;
|
|
.equ DWDR3 = 3 ;
|
|
.equ DWDR4 = 4 ;
|
|
.equ DWDR5 = 5 ;
|
|
.equ DWDR6 = 6 ;
|
|
.equ DWDR7 = 7 ;
|
|
|
|
|
|
; ***** EXTERNAL_INTERRUPT ***********
|
|
; EICRA - External Interrupt Control Register A
|
|
.equ ISC00 = 0 ; External Interrupt Sense Control Bit
|
|
.equ ISC01 = 1 ; External Interrupt Sense Control Bit
|
|
.equ ISC10 = 2 ; External Interrupt Sense Control Bit
|
|
.equ ISC11 = 3 ; External Interrupt Sense Control Bit
|
|
.equ ISC20 = 4 ; External Interrupt Sense Control Bit
|
|
.equ ISC21 = 5 ; External Interrupt Sense Control Bit
|
|
.equ ISC30 = 6 ; External Interrupt Sense Control Bit
|
|
.equ ISC31 = 7 ; External Interrupt Sense Control Bit
|
|
|
|
; EICRB - External Interrupt Control Register B
|
|
.equ ISC40 = 0 ; External Interrupt 7-4 Sense Control Bit
|
|
.equ ISC41 = 1 ; External Interrupt 7-4 Sense Control Bit
|
|
.equ ISC50 = 2 ; External Interrupt 7-4 Sense Control Bit
|
|
.equ ISC51 = 3 ; External Interrupt 7-4 Sense Control Bit
|
|
.equ ISC60 = 4 ; External Interrupt 7-4 Sense Control Bit
|
|
.equ ISC61 = 5 ; External Interrupt 7-4 Sense Control Bit
|
|
.equ ISC70 = 6 ; External Interrupt 7-4 Sense Control Bit
|
|
.equ ISC71 = 7 ; External Interrupt 7-4 Sense Control Bit
|
|
|
|
; EIMSK - External Interrupt Mask Register
|
|
.equ INT0 = 0 ; External Interrupt Request 0 Enable
|
|
.equ INT1 = 1 ; External Interrupt Request 1 Enable
|
|
.equ INT2 = 2 ; External Interrupt Request 2 Enable
|
|
.equ INT3 = 3 ; External Interrupt Request 3 Enable
|
|
.equ INT4 = 4 ; External Interrupt Request 4 Enable
|
|
.equ INT5 = 5 ; External Interrupt Request 5 Enable
|
|
.equ INT6 = 6 ; External Interrupt Request 6 Enable
|
|
.equ INT7 = 7 ; External Interrupt Request 7 Enable
|
|
|
|
; EIFR - External Interrupt Flag Register
|
|
.equ INTF0 = 0 ; External Interrupt Flag 0
|
|
.equ INTF1 = 1 ; External Interrupt Flag 1
|
|
.equ INTF2 = 2 ; External Interrupt Flag 2
|
|
.equ INTF3 = 3 ; External Interrupt Flag 3
|
|
.equ INTF4 = 4 ; External Interrupt Flag 4
|
|
.equ INTF5 = 5 ; External Interrupt Flag 5
|
|
.equ INTF6 = 6 ; External Interrupt Flag 6
|
|
.equ INTF7 = 7 ; External Interrupt Flag 7
|
|
|
|
; PCICR - Pin Change Interrupt Control Register
|
|
.equ PCIE0 = 0 ; Pin Change Interrupt Enable 0
|
|
.equ PCIE1 = 1 ; Pin Change Interrupt Enable 1
|
|
|
|
; PCIFR - Pin Change Interrupt Flag Register
|
|
.equ PCIF0 = 0 ; Pin Change Interrupt Flag 0
|
|
.equ PCIF1 = 1 ; Pin Change Interrupt Flag 1
|
|
|
|
; PCMSK0 - Pin Change Mask Register 0
|
|
.equ PCINT0 = 0 ; Pin Change Enable Mask 0
|
|
.equ PCINT1 = 1 ; Pin Change Enable Mask 1
|
|
.equ PCINT2 = 2 ; Pin Change Enable Mask 2
|
|
.equ PCINT3 = 3 ; Pin Change Enable Mask 3
|
|
.equ PCINT4 = 4 ; Pin Change Enable Mask 4
|
|
.equ PCINT5 = 5 ; Pin Change Enable Mask 5
|
|
.equ PCINT6 = 6 ; Pin Change Enable Mask 6
|
|
.equ PCINT7 = 7 ; Pin Change Enable Mask 7
|
|
|
|
; PCMSK1 - Pin Change Mask Register 1
|
|
.equ PCINT8 = 0 ;
|
|
.equ PCINT9 = 1 ;
|
|
.equ PCINT10 = 2 ;
|
|
.equ PCINT11 = 3 ;
|
|
.equ PCINT12 = 4 ;
|
|
|
|
|
|
; ***** USART1 ***********************
|
|
; UDR1 - USART I/O Data Register
|
|
.equ UDR1_0 = 0 ; USART I/O Data Register bit 0
|
|
.equ UDR1_1 = 1 ; USART I/O Data Register bit 1
|
|
.equ UDR1_2 = 2 ; USART I/O Data Register bit 2
|
|
.equ UDR1_3 = 3 ; USART I/O Data Register bit 3
|
|
.equ UDR1_4 = 4 ; USART I/O Data Register bit 4
|
|
.equ UDR1_5 = 5 ; USART I/O Data Register bit 5
|
|
.equ UDR1_6 = 6 ; USART I/O Data Register bit 6
|
|
.equ UDR1_7 = 7 ; USART I/O Data Register bit 7
|
|
|
|
; UCSR1A - USART Control and Status Register A
|
|
.equ MPCM1 = 0 ; Multi-processor Communication Mode
|
|
.equ U2X1 = 1 ; Double the USART transmission speed
|
|
.equ UPE1 = 2 ; Parity Error
|
|
.equ DOR1 = 3 ; Data overRun
|
|
.equ FE1 = 4 ; Framing Error
|
|
.equ UDRE1 = 5 ; USART Data Register Empty
|
|
.equ TXC1 = 6 ; USART Transmitt Complete
|
|
.equ RXC1 = 7 ; USART Receive Complete
|
|
|
|
; UCSR1B - USART Control and Status Register B
|
|
.equ TXB81 = 0 ; Transmit Data Bit 8
|
|
.equ RXB81 = 1 ; Receive Data Bit 8
|
|
.equ UCSZ12 = 2 ; Character Size
|
|
.equ TXEN1 = 3 ; Transmitter Enable
|
|
.equ RXEN1 = 4 ; Receiver Enable
|
|
.equ UDRIE1 = 5 ; USART Data register Empty Interrupt Enable
|
|
.equ TXCIE1 = 6 ; TX Complete Interrupt Enable
|
|
.equ RXCIE1 = 7 ; RX Complete Interrupt Enable
|
|
|
|
; UCSR1C - USART Control and Status Register C
|
|
.equ UCPOL1 = 0 ; Clock Polarity
|
|
.equ UCSZ10 = 1 ; Character Size
|
|
.equ UCSZ11 = 2 ; Character Size
|
|
.equ USBS1 = 3 ; Stop Bit Select
|
|
.equ UPM10 = 4 ; Parity Mode Bit 0
|
|
.equ UPM11 = 5 ; Parity Mode Bit 1
|
|
.equ UMSEL10 = 6 ; USART Mode Select
|
|
.equ UMSEL11 = 7 ; USART Mode Select
|
|
|
|
; UCSR1D - USART Control and Status Register D
|
|
.equ RTSEN = 0 ; RTS Enable
|
|
.equ CTSEN = 1 ; CTS Enable
|
|
|
|
|
|
; ***** WATCHDOG *********************
|
|
; WDTCSR - Watchdog Timer Control Register
|
|
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
|
|
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
|
|
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
|
|
.equ WDE = 3 ; Watch Dog Enable
|
|
.equ WDCE = 4 ; Watchdog Change Enable
|
|
.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3
|
|
.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable
|
|
.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag
|
|
|
|
; WDTCKD - Watchdog Timer Clock Divider
|
|
.equ WCLKD0 = 0 ; Watchdog Timer Clock Divider 0
|
|
.equ WCLKD1 = 1 ; Watchdog Timer Clock Divider 1
|
|
.equ WDEWIE = 2 ; Watchdog Early Warning Interrupt Enable
|
|
.equ WDEWIF = 3 ; Watchdog Early Warning Interrupt Flag
|
|
|
|
|
|
; ***** ANALOG_COMPARATOR ************
|
|
; ACSR - Analog Comparator Control And Status Register
|
|
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
|
|
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
|
|
.equ ACIC = 2 ; Analog Comparator Input Capture Enable
|
|
.equ ACIE = 3 ; Analog Comparator Interrupt Enable
|
|
.equ ACI = 4 ; Analog Comparator Interrupt Flag
|
|
.equ ACO = 5 ; Analog Compare Output
|
|
.equ ACBG = 6 ; Analog Comparator Bandgap Select
|
|
.equ ACD = 7 ; Analog Comparator Disable
|
|
|
|
; DIDR1 -
|
|
.equ AIN0D = 0 ; AIN0 Digital Input Disable
|
|
.equ AIN1D = 1 ; AIN1 Digital Input Disable
|
|
|
|
|
|
; ***** PORTC ************************
|
|
; PORTC - Port C Data Register
|
|
.equ PORTC0 = 0 ; Port C Data Register bit 0
|
|
.equ PC0 = 0 ; For compatibility
|
|
.equ PORTC1 = 1 ; Port C Data Register bit 1
|
|
.equ PC1 = 1 ; For compatibility
|
|
.equ PORTC2 = 2 ; Port C Data Register bit 2
|
|
.equ PC2 = 2 ; For compatibility
|
|
.equ PORTC4 = 4 ; Port C Data Register bit 4
|
|
.equ PC4 = 4 ; For compatibility
|
|
.equ PORTC5 = 5 ; Port C Data Register bit 5
|
|
.equ PC5 = 5 ; For compatibility
|
|
.equ PORTC6 = 6 ; Port C Data Register bit 6
|
|
.equ PC6 = 6 ; For compatibility
|
|
.equ PORTC7 = 7 ; Port C Data Register bit 7
|
|
.equ PC7 = 7 ; For compatibility
|
|
|
|
; DDRC - Port C Data Direction Register
|
|
.equ DDC0 = 0 ; Port C Data Direction Register bit 0
|
|
.equ DDC1 = 1 ; Port C Data Direction Register bit 1
|
|
.equ DDC2 = 2 ; Port C Data Direction Register bit 2
|
|
.equ DDC4 = 4 ; Port C Data Direction Register bit 4
|
|
.equ DDC5 = 5 ; Port C Data Direction Register bit 5
|
|
.equ DDC6 = 6 ; Port C Data Direction Register bit 6
|
|
.equ DDC7 = 7 ; Port C Data Direction Register bit 7
|
|
|
|
; PINC - Port C Input Pins
|
|
.equ PINC0 = 0 ; Port C Input Pins bit 0
|
|
.equ PINC1 = 1 ; Port C Input Pins bit 1
|
|
.equ PINC2 = 2 ; Port C Input Pins bit 2
|
|
.equ PINC4 = 4 ; Port C Input Pins bit 4
|
|
.equ PINC5 = 5 ; Port C Input Pins bit 5
|
|
.equ PINC6 = 6 ; Port C Input Pins bit 6
|
|
.equ PINC7 = 7 ; Port C Input Pins bit 7
|
|
|
|
|
|
|
|
; ***** LOCKSBITS ********************************************************
|
|
.equ LB1 = 0 ; Lock bit
|
|
.equ LB2 = 1 ; Lock bit
|
|
.equ BLB01 = 2 ; Boot Lock bit
|
|
.equ BLB02 = 3 ; Boot Lock bit
|
|
.equ BLB11 = 4 ; Boot lock bit
|
|
.equ BLB12 = 5 ; Boot lock bit
|
|
|
|
|
|
; ***** FUSES ************************************************************
|
|
; LOW fuse bits
|
|
.equ CKSEL0 = 0 ; Select Clock Source
|
|
.equ CKSEL1 = 1 ; Select Clock Source
|
|
.equ CKSEL2 = 2 ; Select Clock Source
|
|
.equ CKSEL3 = 3 ; Select Clock Source
|
|
.equ SUT0 = 4 ; Select start-up time
|
|
.equ SUT1 = 5 ; Select start-up time
|
|
.equ CKOUT = 6 ; Oscillator options
|
|
.equ CKDIV8 = 7 ; Divide clock by 8
|
|
|
|
; HIGH fuse bits
|
|
.equ BOOTRST = 0 ; Select Reset Vector
|
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.equ BOOTSZ0 = 1 ; Select Boot Size
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.equ BOOTSZ1 = 2 ; Select Boot Size
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.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase
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.equ WDTON = 4 ; Watchdog timer always on
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.equ SPIEN = 5 ; Enable Serial programming and Data Downloading
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.equ RSTDISBL = 6 ; External Reset Disable
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.equ DWEN = 7 ; dwbugWIRE Enable
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; EXTENDED fuse bits
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.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level
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.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level
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.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level
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.equ HWBE = 3 ; Hardware Boot Enable
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; ***** CPU REGISTER DEFINITIONS *****************************************
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.def XH = r27
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.def XL = r26
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.def YH = r29
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.def YL = r28
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.def ZH = r31
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.def ZL = r30
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; ***** DATA MEMORY DECLARATIONS *****************************************
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.equ FLASHEND = 0x0fff ; Note: Word address
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.equ IOEND = 0x00ff
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.equ SRAM_START = 0x0100
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.equ SRAM_SIZE = 512
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.equ RAMEND = 0x02ff
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.equ XRAMEND = 0x0000
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.equ E2END = 0x01ff
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.equ EEPROMEND = 0x01ff
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.equ EEADRBITS = 9
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#pragma AVRPART MEMORY PROG_FLASH 8192
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#pragma AVRPART MEMORY EEPROM 512
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#pragma AVRPART MEMORY INT_SRAM SIZE 512
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#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100
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; ***** BOOTLOADER DECLARATIONS ******************************************
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.equ NRWW_START_ADDR = 0x800
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.equ NRWW_STOP_ADDR = 0xfff
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.equ RWW_START_ADDR = 0x0
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.equ RWW_STOP_ADDR = 0x7ff
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.equ PAGESIZE = 64
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.equ FIRSTBOOTSTART = 0xf00
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.equ SECONDBOOTSTART = 0xe00
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.equ THIRDBOOTSTART = 0xc00
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.equ FOURTHBOOTSTART = 0x800
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.equ SMALLBOOTSTART = FIRSTBOOTSTART
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.equ LARGEBOOTSTART = FOURTHBOOTSTART
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; ***** INTERRUPT VECTORS ************************************************
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.equ INT0addr = 0x0002 ; External Interrupt Request 0
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.equ INT1addr = 0x0004 ; External Interrupt Request 1
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.equ INT2addr = 0x0006 ; External Interrupt Request 2
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.equ INT3addr = 0x0008 ; External Interrupt Request 3
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.equ INT4addr = 0x000a ; External Interrupt Request 4
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.equ INT5addr = 0x000c ; External Interrupt Request 5
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.equ INT6addr = 0x000e ; External Interrupt Request 6
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.equ INT7addr = 0x0010 ; External Interrupt Request 7
|
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.equ PCI0addr = 0x0012 ; Pin Change Interrupt Request 0
|
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.equ PCI1addr = 0x0014 ; Pin Change Interrupt Request 1
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.equ USB_GENaddr = 0x0016 ; USB General Interrupt Request
|
|
.equ USB_COMaddr = 0x0018 ; USB Endpoint/Pipe Interrupt Communication Request
|
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.equ WDTaddr = 0x001a ; Watchdog Time-out Interrupt
|
|
.equ ICP1addr = 0x001c ; Timer/Counter2 Capture Event
|
|
.equ OC1Aaddr = 0x001e ; Timer/Counter2 Compare Match B
|
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.equ OC1Baddr = 0x0020 ; Timer/Counter2 Compare Match B
|
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.equ OC1Caddr = 0x0022 ; Timer/Counter2 Compare Match C
|
|
.equ OVF1addr = 0x0024 ; Timer/Counter1 Overflow
|
|
.equ OC0Aaddr = 0x0026 ; Timer/Counter0 Compare Match A
|
|
.equ OC0Baddr = 0x0028 ; Timer/Counter0 Compare Match B
|
|
.equ OVF0addr = 0x002a ; Timer/Counter0 Overflow
|
|
.equ SPIaddr = 0x002c ; SPI Serial Transfer Complete
|
|
.equ URXC1addr = 0x002e ; USART1, Rx Complete
|
|
.equ UDRE1addr = 0x0030 ; USART1 Data register Empty
|
|
.equ UTXC1addr = 0x0032 ; USART1, Tx Complete
|
|
.equ ACIaddr = 0x0034 ; Analog Comparator
|
|
.equ ERDYaddr = 0x0036 ; EEPROM Ready
|
|
.equ SPMRaddr = 0x0038 ; Store Program Memory Read
|
|
|
|
.equ INT_VECTORS_SIZE = 58 ; size in words
|
|
|
|
#endif /* _M8U2DEF_INC_ */
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|
|
|
; ***** END OF FILE ******************************************************
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