232 lines
6.2 KiB
NASM
232 lines
6.2 KiB
NASM
; ***************************************************************************
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; copyright : (C) 2025 by Martin Preuss
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; email : martin@libchipcard.de
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;
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; ***************************************************************************
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; * This file is part of the project "AqHome". *
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; * Please see toplevel file COPYING of that project for license details. *
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; ***************************************************************************
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#ifndef AVR_MODULES_UARTFD_MACROS_ASM
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#define AVR_MODULES_UARTFD_MACROS_ASM
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.macro M_UARTFD_SET_CHARFORMAT
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ldi r16, (1<<UCSZ@01) | (1<<UCSZ@00) ; 1 stop bit, 8 databits
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outr UCSR@0C, r16
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.endmacro
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.macro M_UARTFD_SET_BAUDRATE
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.if clock == 8000000
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ldi r16, 25 ; (19.2Kb/s at 8MHz)
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ldi r17, 0
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.elif clock == 1000000
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ldi r16, 2 ; (19.2Kb/s at 1MHz)
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ldi r17, 0
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.else
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.error "Unhandled clock frequency"
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.endif
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outr UBRR@0H, r17
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outr UBRR@0L, r16
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.endmacro
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.macro M_UARTFD_START_RX
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inr r16, UCSR@0B
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sbr r16, (1<<RXCIE@0) | (1<<RXEN@0) ; enable RX complete interrupt, enable receive
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outr UCSR@0B, r16
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.endmacro
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.macro M_UARTFD_STOP_RX
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inr r16, UCSR@0B
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cbr r16, (1<<RXCIE@0) | (1<<RXEN@0) ; disable RX complete interrupt, disable receive
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outr UCSR@0B, r16
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.endmacro
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.macro M_UARTFD_START_TX
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inr r16, UCSR@0A
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cbr r16, (1<<TXC@0) ; clear TXCn interrupt
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outr UCSR@0A, r16
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inr r16, UCSR@0B
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; sbr r16, (1<<UDRIE@0) | (1<<TXCIE@0) | (1<<TXEN@0) ; enable TX UDRE and TXC interrupt, enable transceive
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sbr r16, (1<<UDRIE@0) | (1<<TXEN@0) ; enable TX UDRE interrupt, enable transceive
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outr UCSR@0B, r16
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.endmacro
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.macro M_UARTFD_STOP_TX
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inr r16, UCSR@0B
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cbr r16, (1<<UDRIE@0) | (1<<TXCIE@0) | (1<<TXEN@0) ; disable TX UDRE and TXC interrupt, disable transceive
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outr UCSR@0B, r16
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.endmacro
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.macro M_UARTFD_STOP_TXIRQS
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inr r16, UCSR@0B
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cbr r16, (1<<UDRIE@0) | (1<<TXCIE@0) ; disable TX UDRE and TXC interrupt
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outr UCSR@0B, r16
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.endmacro
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.macro M_UARTFD_FLUSH_IN
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l_loop_%:
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inr r16, UCSR@0A
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sbrs r16, RXC@0
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rjmp l_end_% ; no data
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inr r16, UDR@0 ; r16=received char
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rjmp l_loop_%
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l_end_%:
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.endmacro
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; @end
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; ---------------------------------------------------------------------------
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; @macro M_UARTFD_RXCHAR_ISR
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;
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; @clobbers r16, r17, X
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.macro M_UARTFD_RXCHAR_ISR
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ldd r16, Y+UARTFD_IFACE_OFFS_STATUS
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andi r16, (1<<UARTFD_IFACE_STATUS_BIT_SKIPPING)
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breq l_readNext_%
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; skipping mode, just skip character
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inr r16, UDR@0 ; r16=received char
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rjmp l_resetReadTimer_% ; skipping
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l_readNext_%:
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inr r16, UCSR@0A ; check for errors
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andi r16, (1<<FE@0) | (1<<DOR@0) | (1<<UPE@0)
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brne l_hwerr_%
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inr r16, UCSR@0A
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sbrs r16, RXC@0
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rjmp l_end_% ; no data
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inr r16, UDR@0 ; r16=received char
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ldd r17, Y+UARTFD_IFACE_OFFS_RBUFLEFT
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tst r17
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breq l_overrun_%
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dec r17
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std Y+UARTFD_IFACE_OFFS_RBUFLEFT, r17
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ldd r17, Y+UARTFD_IFACE_OFFS_RBUFUSED
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inc r17
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std Y+UARTFD_IFACE_OFFS_RBUFUSED, r17
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ldd xl, Y+UARTFD_IFACE_OFFS_RPOS_LOW
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ldd xh, Y+UARTFD_IFACE_OFFS_RPOS_HIGH
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st X+, r16
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std Y+UARTFD_IFACE_OFFS_RPOS_LOW, xl
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std Y+UARTFD_IFACE_OFFS_RPOS_HIGH, xh
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cpi r17, 2 ; exactly 2 bytes in buffer?
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brne l_resetReadTimer_%
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; determine message size
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inc r16 ; last byte was payload length, add byte for crc
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ldd r17, Y+UARTFD_IFACE_OFFS_RBUFLEFT
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cp r17, r16 ; compare remaining length against remaining space
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brcs l_badMsgSize_%
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std Y+UARTFD_IFACE_OFFS_RBUFLEFT, r16
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l_resetReadTimer_%:
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clr r16
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std Y+NET_IFACE_OFFS_READTIMER, r16 ; reset read timer
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rjmp l_end_%
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l_hwerr_%:
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ldd r16, Y+UARTFD_IFACE_OFFS_STATUS
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ori r16, (1<<UARTFD_IFACE_STATUS_BIT_HWERR) | (1<<UARTFD_IFACE_STATUS_BIT_SKIPPING)
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std Y+UARTFD_IFACE_OFFS_STATUS, r16
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rjmp l_end_%
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l_badMsgSize_%:
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ldd r16, Y+UARTFD_IFACE_OFFS_STATUS
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ori r16, (1<<UARTFD_IFACE_STATUS_BIT_BADMSGSIZE) | (1<<UARTFD_IFACE_STATUS_BIT_SKIPPING)
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std Y+UARTFD_IFACE_OFFS_STATUS, r16
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rjmp l_end_%
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l_overrun_%:
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ldd r16, Y+UARTFD_IFACE_OFFS_STATUS
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ori r16, (1<<UARTFD_IFACE_STATUS_BIT_OVERRUN) | (1<<UARTFD_IFACE_STATUS_BIT_SKIPPING)
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std Y+UARTFD_IFACE_OFFS_STATUS, r16
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l_end_%:
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.endmacro
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; @end
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; ---------------------------------------------------------------------------
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; @macro M_UARTFD_TXUDRE_ISR
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;
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; @clobbers R16, R17, X
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.macro M_UARTFD_TXUDRE_ISR
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lds r16, UCSR@0A ; check for UDRE flag
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sbrs r16,UDRE@0
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rjmp l_disable_irq_% ; not ready
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; check whether we have an active write buffer
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ldd r16, Y+UARTFD_IFACE_OFFS_WBUFNUM
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cpi r16, 0xff
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breq l_disable_irq_% ; no buffer
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; check whether there is data in the buffer to send
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ldd r17, Y+UARTFD_IFACE_OFFS_WBUFLEFT ; r17=bytes left
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tst r17
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breq l_disable_irq_% ; nothing left to write
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; get read ptr, read byte, inc read ptr, store ptr and bytesLeft
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ldd xl, Y+UARTFD_IFACE_OFFS_WPOS_LOW
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ldd xh, Y+UARTFD_IFACE_OFFS_WPOS_HIGH
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ld r16, X+ ; r16=byte to write
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std Y+UARTFD_IFACE_OFFS_WPOS_LOW, xl
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std Y+UARTFD_IFACE_OFFS_WPOS_HIGH, xh
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dec r17
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std Y+UARTFD_IFACE_OFFS_WBUFLEFT, r17
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; send byte, reset write timer
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sts UDR@0, r16
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clr r16
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std Y+NET_IFACE_OFFS_WRITETIMER, r16 ; reset write timer
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; still bytes left to write?
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tst r17
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brne l_end_%
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l_disable_irq_%:
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; disable further UDRE interrupts
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lds r16, UCSR@0B
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cbr r16, (1<<UDRIE@0) ; disable TX data register empty interrupt
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sts UCSR@0B, r16
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l_end_%:
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.endmacro
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; @end
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; ---------------------------------------------------------------------------
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; @macro M_UARTFD_TXCHAR_ISR
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;
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; @clobbers R16, R17, X
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.macro M_UARTFD_TXCHAR_ISR
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; disable further TXC interrupts
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inr r16, UCSR@0B
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cbr r16, (1<<TXC@0) ; disable TXC interrupt
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outr UCSR@0B, r16
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.endmacro
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; @end
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#endif
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