90 lines
4.1 KiB
NASM
90 lines
4.1 KiB
NASM
; ***************************************************************************
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; copyright : (C) 2025 by Martin Preuss
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; email : martin@libchipcard.de
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;
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; ***************************************************************************
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; * This file is part of the project "AqHome". *
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; * Please see toplevel file COPYING of that project for license details. *
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; ***************************************************************************
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.equ UART_HW_IFACE_READBUF_SIZE = 8
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.equ UART_HW_IFACE_WRITEBUF_SIZE = 8
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.equ UART_HW_IFACE_OUTMSGBUF_SIZE = 4
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.equ UART_HW_BUFFER_INUSE_BIT = 7
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.equ UART_HW_BUFFER_IFACENUM1_BIT = 1
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.equ UART_HW_BUFFER_IFACENUM0_BIT = 0
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.equ UART_HW_MODE_READMASK = 0x0f
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.equ UART_HW_MODE_WRITEMASK = 0xf0
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.equ UART_HW_MODE_OFF = 0
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.equ UART_HW_MODE_IDLE = 1
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.equ UART_HW_MODE_READING = 2
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.equ UART_HW_MODE_SKIPPING = 3
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.equ UART_HW_MODE_W_IDLE = 0
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.equ UART_HW_MODE_WRITING = 8
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.equ UART_HW_MODE_WAITBUFFEREMPTY = 9
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.equ UART_HW_MODE_WRITEBUFFEREMPTY = 10
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.equ UART_HW_STATUS_UNDERRUN_BIT = 0
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.equ UART_HW_STATUS_OVERRUN_BIT = 1
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.equ UART_HW_STATUS_HWERR_BIT = 2
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.equ UART_HW_STATUS_SOFTERR_BIT = 3
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.equ UART_HW_STATUS_ATTN_BIT = 7
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.equ UART_HW_IFACE_OFFS_IFACENUM = 0 ; interface number (put into received messages)
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.equ UART_HW_IFACE_OFFS_MODE = 1
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.equ UART_HW_IFACE_OFFS_STATUS = 2
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.equ UART_HW_IFACE_OFFS_READTIMER = 3
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.equ UART_HW_IFACE_OFFS_WRITETIMER = 4
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.equ UART_HW_IFACE_OFFS_ERR_OVR = 5
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.equ UART_HW_IFACE_OFFS_ERR_CONTENT = 6
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; ringbuffer for incoming chars
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.equ UART_HW_IFACE_OFFS_READBUF = 7
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.equ UART_HW_IFACE_OFFS_READBUF_MAX = UART_HW_IFACE_OFFS_READBUF
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.equ UART_HW_IFACE_OFFS_READBUF_USED = UART_HW_IFACE_OFFS_READBUF+1
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.equ UART_HW_IFACE_OFFS_READBUF_RDPOS = UART_HW_IFACE_OFFS_READBUF+2
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.equ UART_HW_IFACE_OFFS_READBUF_WRPOS = UART_HW_IFACE_OFFS_READBUF+3
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.equ UART_HW_IFACE_OFFS_READBUF_DATA = UART_HW_IFACE_OFFS_READBUF+4 ; UART_HW_IFACE_READBUF_SIZE bytes
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; ringbuffer for outgoing chars
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.equ UART_HW_IFACE_OFFS_WRITEBUF = UART_HW_IFACE_OFFS_READBUF_DATA+UART_HW_IFACE_READBUF_SIZE
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.equ UART_HW_IFACE_OFFS_WRITEBUF_MAX = UART_HW_IFACE_OFFS_WRITEBUF
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.equ UART_HW_IFACE_OFFS_WRITEBUF_USED = UART_HW_IFACE_OFFS_WRITEBUF+1
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.equ UART_HW_IFACE_OFFS_WRITEBUF_RDPOS = UART_HW_IFACE_OFFS_WRITEBUF+2
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.equ UART_HW_IFACE_OFFS_WRITEBUF_WRPOS = UART_HW_IFACE_OFFS_WRITEBUF+3
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.equ UART_HW_IFACE_OFFS_WRITEBUF_DATA = UART_HW_IFACE_OFFS_WRITEBUF+4
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; ringbuffer for outgoing messages
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.equ UART_HW_IFACE_OFFS_OUTMSGBUF = UART_HW_IFACE_OFFS_WRITEBUF_DATA+UART_HW_IFACE_WRITEBUF_SIZE
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.equ UART_HW_IFACE_OFFS_OUTMSGBUF_MAX = UART_HW_IFACE_OFFS_OUTMSGBUF
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.equ UART_HW_IFACE_OFFS_OUTMSGBUF_USED = UART_HW_IFACE_OFFS_OUTMSGBUF+1
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.equ UART_HW_IFACE_OFFS_OUTMSGBUF_RDPOS = UART_HW_IFACE_OFFS_OUTMSGBUF+2
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.equ UART_HW_IFACE_OFFS_OUTMSGBUF_WRPOS = UART_HW_IFACE_OFFS_OUTMSGBUF+3
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.equ UART_HW_IFACE_OFFS_OUTMSGBUF_DATA = UART_HW_IFACE_OFFS_OUTMSGBUF+4
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; ref to recv buffer
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.equ UART_HW_IFACE_OFFS_READMSG = UART_HW_IFACE_OFFS_OUTMSGBUF_DATA+UART_HW_IFACE_OUTMSGBUF_SIZE
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.equ UART_HW_IFACE_OFFS_READMSG_BUFNUM = UART_HW_IFACE_OFFS_READMSG ; 1 byte
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.equ UART_HW_IFACE_OFFS_READMSG_PTR = UART_HW_IFACE_OFFS_READMSG+1 ; 2 bytes
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.equ UART_HW_IFACE_OFFS_READMSG_USED = UART_HW_IFACE_OFFS_READMSG+3 ; 1 byte
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.equ UART_HW_IFACE_OFFS_READMSG_LEFT = UART_HW_IFACE_OFFS_READMSG+4 ; 1 byte
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; ref to transmit buffer
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.equ UART_HW_IFACE_OFFS_WRITEMSG = UART_HW_IFACE_OFFS_READMSG_LEFT+1
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.equ UART_HW_IFACE_OFFS_WRITEMSG_BUFNUM = UART_HW_IFACE_OFFS_WRITEMSG ; 1 byte
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.equ UART_HW_IFACE_OFFS_WRITEMSG_PTR = UART_HW_IFACE_OFFS_WRITEMSG+1 ; 2 bytes
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.equ UART_HW_IFACE_OFFS_WRITEMSG_USED = UART_HW_IFACE_OFFS_WRITEMSG+3 ; 1 byte
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.equ UART_HW_IFACE_OFFS_WRITEMSG_LEFT = UART_HW_IFACE_OFFS_WRITEMSG+4 ; 1 byte
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.equ UART_HW_IFACE_SIZE = UART_HW_IFACE_OFFS_WRITEMSG_LEFT+1
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