88 lines
2.4 KiB
NASM
88 lines
2.4 KiB
NASM
; ***************************************************************************
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; copyright : (C) 2025 by Martin Preuss
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; email : martin@libchipcard.de
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;
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; ***************************************************************************
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; * This file is part of the project "AqHome". *
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; * Please see toplevel file COPYING of that project for license details. *
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; ***************************************************************************
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; ***************************************************************************
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; code
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.cseg
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; ---------------------------------------------------------------------------
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; @routine ioRawInit
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; Init raw message subsystem.
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;
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; @clobbers none
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ioRawInit:
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; setup pins and interrupts
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cbi COM_DATA_DDR, COM_DATA_PIN ; set DATA port as input
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cbi COM_DATA_OUTPUT, COM_DATA_PIN ; disable internal pullup for TXD
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cbi COM_ATTN_DDR, COM_ATTN_PIN ; set ATTN port as input
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cbi COM_ATTN_OUTPUT, COM_ATTN_PIN ; disable internal pullup for ATTN
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ret
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;@end
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; ---------------------------------------------------------------------------
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; @routine ioRawSendMsg
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; Send a message
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;
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; @clobbers X (R16, R17, R21, R22)
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ioRawSendMsg:
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ioRawSendMsg_loop:
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ldi r16, 0xff ; expect ATTN high
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ldi r17, 3
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rcall ioWaitForAttnState100ms ; wait for up to 300ms
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brcs ioRawSendMsg_attnHigh
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ret
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ioRawSendMsg_attnHigh:
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ldi xl, LOW(flashSendBuffer)
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ldi xh, HIGH(flashSendBuffer)
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rcall uartBitbang_SendPacket ; R16, R22 (R17, R21, X)
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brcc ioRawSendMsg_loop
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine ioRawWaitForValidMsg
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; Wait for valid incoming msg
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;
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; @return CFLAG set if okay (packet received), cleared on error
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; @clobbers:
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ioRawWaitForValidMsg:
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ldi r16, 0 ; expect ATTN low
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ldi r17, 100
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rcall ioWaitForAttnState100ms ; wait for up to 10s
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brcs ioRawWaitForValidMsg_attnLow
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ret
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ioRawWaitForValidMsg_attnLow:
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ldi xl, LOW(flashRecvBuffer)
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ldi xh, HIGH(flashRecvBuffer)
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ldi r16, COM2_MAINTENANCE_ADDR
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ldi r17, FLASH_RECVBUFFER_MAXLEN-3
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rcall uartBitbang_ReceivePacketIntoBuffer
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brcs ioRawWaitForValidMsg_packetReceived
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ret
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ioRawWaitForValidMsg_packetReceived:
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ldi r16, 0xff ; expect ATTN high
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ldi r17, 100
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rjmp ioWaitForAttnState100ms ; wait for up to 10s
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; @end
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