; *************************************************************************** ; copyright : (C) 2024 by Martin Preuss ; email : martin@libchipcard.de ; ; *************************************************************************** ; * This file is part of the project "AqHome". * ; * Please see toplevel file COPYING of that project for license details. * ; *************************************************************************** ; *************************************************************************** ; Source file for temperature sensor node on AtTiny 84 ; ; This is for the full system (i.e. not the boot loader). ; ; All definitions and changes should go into this file. ; ; ; *************************************************************************** ;.equ clock=1000000 ; Define the clock frequency .equ clock=8000000 ; Define the clock frequency ;.equ SEND_DEVICE_EVERY = 3000 .equ SEND_DEVICE_EVERY = 3000 ; every 5mins ;.equ SEND_STATS_EVERY = 3100 ; about every 5mins .equ SEND_STATS_EVERY = 300 ; every 30s .equ SEND_DEBUG_EVERY = 110 .nolist .include "include/tn841def.inc" ; Define device ATtiny841 .list .include "./defs.asm" .include "defs_all.asm" ; *************************************************************************** ; defines ; --------------------------------------------------------------------------- ; generic .include "common/utils_wait.asm" ; --------------------------------------------------------------------------- ; firmware settings including list of modules used .equ FIRMWARE_VERSION_MAJOR = 0 .equ FIRMWARE_VERSION_MINOR = 0 .equ FIRMWARE_VERSION_PATCHLEVEL = 1 ;#define MODULES_TIMER ;#define MODULES_COM ;#define MODULES_COM_WITH_ADDR_PROTO ;#define MODULES_LED #define MODULES_LED_SIMPLE ;#define MODULES_TWI_MASTER ;#define MODULES_LCD ;#define LCD_MINIMAL_FONT ;#define MODULES_SI7021 ;#define MODULES_STATS ;#define MODULES_CNY70 ;#define MODULES_REED ;#define MODULES_OWI_MASTER ;#define MODULES_DS18B20 ;#define MODULES_MOTION .equ NET_BUFFERS_NUM = 8 .equ NET_BUFFERS_SIZE = 32 .equ UART_HW_MSGNUMINBUF_SIZE = 8 .equ UART_HW_MSGNUMOUTBUF_SIZE = 8 ; *************************************************************************** ; code segment .cseg .org 000000 ; --------------------------------------------------------------------------- ; Reset and interrupt vectors rjmp BOOTLOADER_ADDR ; 1: RESET Reset vector use this for flashed system reti ; 2: INT0 External Interrupt Request 0 rjmp ComOnUart0_AttnChangeIsr ; 3: PCINT0 Pin Change Interrupt 0 reti ; 4: PCINT1 Pin Change Interrupt 1 reti ; 5: WDT Watchdog Time-out reti ; 6: TIM1_CAPT Timer/Counter1 Capture Event reti ; 7: TIM1_COMPA (OC1A) Timer/Counter1 Compare Match A reti ; 8: TIM1_COMPB (OC1B) Timer/Counter1 Compare Match B reti ; 9: TIM1_OVF (OVF1) Timer/Counter1 Overflow rjmp baseTimerIrqOC0A ; 10: TIM0_COMPA (OC0A) Timer/Counter0 Compare Match A reti ; 11: TIM0_COMPB (OC0B) Timer/Counter0 Compare Match B reti ; 12: TIM0_OVF (OVF0) Timer/Counter0 Overflow reti ; 13: ANA_COMP0 Analog Comparator 0 reti ; 14: ADC_READY ADC Conversion Complete reti ; 15: EE_RDY (ERDY) EEPROM Ready reti ; 16: ANA_COMP1 Analog Comparator 1 reti ; 17: TIM2_CAPT Timer/Counter2 Capture Event reti ; 18: TIM2_COMPA (OC2A) Timer/Counter2 Compare Match A reti ; 19: TIM2_COMPB (OC2B) Timer/Counter2 Compare Match B reti ; 20: TIM2_OVF (OVF2) Timer/Counter2 Overflow reti ; 21: SPI SPI Serial Transfer Complete reti ; 22: USART0_RXS USART0 Rx Start rjmp ComOnUart0_RxCharIsr ; 23: USART0_RXC USART0 Rx Complete rjmp ComOnUart0_TxUdreIsr ; 24: USART0_DRE USART0 Data Register Empty rjmp ComOnUart0_TxCharIsr ; 25: USART0_TXC USART0 Tx Complete reti ; 26: USART1_RXS USART1 Rx Start rjmp TtyOnUart1_RxCharIsr ; 27: USART1_RXC USART1 Rx Complete rjmp TtyOnUart1_TxUdreIsr ; 28: USART1_DRE USART1 Data Register Empty rjmp TtyOnUart1_TxCharIsr ; 29: USART1_TXC USART1 Tx Complete reti ; 30: TWI Two-Wire-Interface reti ; 31: RESERVED reserved devInfoBlock: ; 12 bytes devInfoManufacturer: .db 'A', 'Q', 'U', 'A' devInfoId: .db DEVICEINFO_ID, 0 devInfoVersion: .db DEVICEINFO_VERSION, DEVICEINFO_REVISION ; version, revision firmwareVersion: .db FIRMWARE_VARIANT_TEMP_WINDOW, FIRMWARE_VERSION_MAJOR .db FIRMWARE_VERSION_MINOR, FIRMWARE_VERSION_PATCHLEVEL firmwareStart: cli ; setup stack .ifdef SPH ; if SPH is defined ldi r16, High(RAMEND) out SPH, r16 ; init MSB stack pointer .endif ldi r16, Low(RAMEND) out SPL, r16 ; init LSB stack pointer rcall systemSetSpeed rcall initHardware ; rcall watchdogOff ; turn off watchdog timer (sometimes it stays on after reboot) rcall Utils_Init rcall Utils_SetupUid rcall initModules sbi LED_SIMPLE_DDR, LED_SIMPLE_PINNUM ; out sbi LED_SIMPLE_PORT, LED_SIMPLE_PINNUM ; off sei main_loop: ; only modify SE, SM1 and SM0 cli in r16, MCUCR ldi r17, (1<r16) brcc checkRecvdMsg_end ; no msg, jmp rcall NET_Buffer_Locate ; (R17) ld r17, X andi r17, (NET_IFACE_BUFFER_IFACENUM1_BIT | NET_IFACE_BUFFER_IFACENUM0_BIT) rcall reverseInterfaceNum ; ldi r17, TTYONUART1_IFACENUM ; DEBUG: send everything to uart1 to test that code first rcall addMsgToInterface brcc checkRecvdMsg_end ; could not add, jmp rcall NET_GetNextIncomingMsgNum ; take off the queue rjmp checkRecvdMsg checkRecvdMsg_end: ret freeRecvdMsg: rcall NET_GetNextIncomingMsgNum ; take off the queue brcc freeRecvdMsg_end rcall NET_Buffer_ReleaseByNum ; delete freeRecvdMsg_end: ret ; @return r17 reversed interface number ; @param r17 buffer num ; @clobbers r17 reverseInterfaceNum: cpi r17, COMONUART0_IFACENUM brne reverseInterfaceNum_notUart0 ldi r17, TTYONUART1_IFACENUM ret reverseInterfaceNum_notUart0: ldi r17, COMONUART0_IFACENUM ret ; @end ; @param r16 buffer num ; @param r17 interface num addMsgToInterface: cpi r17, COMONUART0_IFACENUM brne addMsgToInterface_notUart0 ldi yl, LOW(comOnUart0_iface) ldi yh, HIGH(comOnUart0_iface) rjmp NET_Interface_AddOutgoingMsgNum ; try to add msg to interface addMsgToInterface_notUart0: cpi r17, TTYONUART1_IFACENUM brne addMsgToInterface_end ldi yl, LOW(ttyOnUart1_iface) ldi yh, HIGH(ttyOnUart1_iface) rjmp NET_Interface_AddOutgoingMsgNum ; try to add msg to interface addMsgToInterface_end: clc ret ; @end sendDebug: ldi yl, LOW(ttyOnUart1_iface) ldi yh, HIGH(ttyOnUart1_iface) lds r24, debugMsgCounter lds r25, debugMsgCounter+1 sbiw r25:r24, 1 brne sendDebug_storeCounter ; send device msg rcall NET_Buffer_Alloc ; (R16, R17, X) brcc sendDebug_end push r16 adiw xh:xl, 1 rcall writeDebugMsg sbiw xh:xl, 1 pop r16 rcall NET_Interface_AddOrReleaseOutMsg ; (R16, R17, R18, X) brcc sendDebug_end ; reset counter sendDebug_resetCounter: ldi r24, LOW(SEND_DEBUG_EVERY) ldi r25, HIGH(SEND_DEBUG_EVERY) sendDebug_storeCounter: sts debugMsgCounter, r24 sts debugMsgCounter+1, r25 sendDebug_end: ret writeDebugMsg: push yl push yh ldi yl, LOW(netBuffers) ldi yh, HIGH(netBuffers) rcall writeBufferInfoToRegs mov r0, r17 mov r1, r18 adiw yh:yl, NET_BUFFERS_SIZE rcall writeBufferInfoToRegs mov r2, r17 mov r3, r18 adiw yh:yl, NET_BUFFERS_SIZE rcall writeBufferInfoToRegs mov r4, r17 mov r5, r18 adiw yh:yl, NET_BUFFERS_SIZE rcall writeBufferInfoToRegs mov r6, r17 mov r7, r18 adiw yh:yl, NET_BUFFERS_SIZE rcall writeBufferInfoToRegs mov r8, r17 mov r9, r18 adiw yh:yl, NET_BUFFERS_SIZE rcall writeBufferInfoToRegs mov r10, r17 mov r11, r18 adiw yh:yl, NET_BUFFERS_SIZE clr r12 clr r13 push xl push xh rcall NET_Buffer_CountUsed pop xh pop xl mov r14, r16 pop yh pop yl rcall NETMSG_Debug_Write ; (R16, R17, R18, R19, R20, R21, Z) ret writeBufferInfoToRegs: ldi r17, 0xff ldi r18, 0xff ld r16, Y andi r16, 0x80 breq writeBufferInfoToRegs_end ldd r17, Y+(1+2) ; cmd code ldd r18, Y+(1+3) ; source addr writeBufferInfoToRegs_end: ret DEBUG1: ldi r19, 10 ldi r20, 2 ldi r21, 8 rcall blinkLed rjmp DEBUG1 DEBUG2: ldi r19, 50 ldi r20, 1 ldi r21, 1 rcall blinkLed rjmp DEBUG2 ; @param r19 loop count ; @param r20 on time ; @param r21 off time ; @clobbers (R16, R18, R22, R24, R25) blinkLed: cbi LED_SIMPLE_PORT, LED_SIMPLE_PINNUM ; on mov r22, r20 rcall waitForMultiple100ms ; (R252 sbi LED_SIMPLE_PORT, LED_SIMPLE_PINNUM ; off mov r22, r21 rcall waitForMultiple100ms ; (R22) dec r19 brne blinkLed ret ; @param r22 number of 100ms periods to wait waitForMultiple100ms: waitForMultiple100ms_loop: push r22 rcall waitFor100ms pop r22 dec r22 brne waitForMultiple100ms_loop ret waitFor100ms: ldi r22, 10 waitFor100ms_loop: push r22 rcall waitFor10ms pop r22 dec r22 brne waitFor100ms_loop ret waitFor10ms: ldi r22, 100 waitFor10ms_loop: push r22 rcall Utils_WaitFor100MicroSecs pop r22 dec r22 brne waitFor10ms_loop ret ; *************************************************************************** ; data in SRAM .dseg programRamBegin: flashUid: .byte 4 deviceCounter: .byte 2 sendTStatsCounter: .byte 2 sendRStatsCounter: .byte 2 sendMStatsCounter: .byte 2 debugMsgCounter: .byte 2 programRamEnd: