; ***************************************************************************
; copyright   : (C) 2025 by Martin Preuss
; email       : martin@libchipcard.de
;
; ***************************************************************************
; * This file is part of the project "AqHome".                              *
; * Please see toplevel file COPYING of that project for license details.   *
; ***************************************************************************



; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_RawInit @global
;
; @clobbers R16, R17

UART_HW_Uart1_RawInit:
  ; set baudrate
;.if clock == 8000000
;  ldi r16, 25 ; (19.2Kb/s at 8MHz)
;  ldi r17, 0
;.endif

;.if clock == 1000000
  ldi r16, 3  ; (19.2Kb/s at 1MHz)
  ldi r17, 0  
;.endif

  sts UBRR1H, r17
  sts UBRR1L, r16

  ; set character format (asynchronous USART, 8-bit, one stop bit, no parity)
  ldi r16, (3<<UCSZ10)
  sts UCSR1C, r16

  ret
; @end



; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_RawSendPacket
; Send packet.
;
; @param X buffer to send
; @return CFLAG: set if okay (packet sent), cleared on error
; @clobbers r16, r17, X

UART_HW_Uart1_RawSendPacket:
  adiw xh:xl, 1
  ld r17, X
  sbiw xh:xl, 1
  ldi r16, 3     ; add DEST, LEN, CRC bytes
  add r17, r16
  
  lds r16, UCSR1B
;  cbr r16, (1<<UDRIE1)  ; disable DRE interrupt
  sbr r16, (1<<TXEN1)   ; enable transmit
  sts UCSR1B, r16

;;  clr r16               ; clear all pending interrupts
;;  sts UCSR1A, r16

;ldi r17, 20

UART_HW_Uart1_RawSendPacket_loop:
      lds r16, UCSR1A
      sbrs r16, UDRE1
    rjmp UART_HW_Uart1_RawSendPacket_loop
    sbr r16, (1<<TXC1)
    sts UCSR1A, r16
    ld r16, X+
    sts UDR1, r16
    dec r17
  brne UART_HW_Uart1_RawSendPacket_loop
  ; disable transmit
;  lds r16, UCSR1B
;  cbr r16, (1<<TXEN1)   ; disable transmit
;  sts UCSR1B, r16
  sec
  ret
; @end



; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_EnableRawRecv @global
;
; Enable receiving messages in raw mode.
;
; @clobbers: r16

UART_HW_Uart1_EnableRawRecv:
  lds r16, UCSR1B
  cbr r16, (1<<RXCIE1)                      ; disable RX complete interrupt
  sbr r16, (1<<RXEN1)                       ; enable receive
  sts UCSR1B, r16
  ret
; @end



; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_DisableRawRecv @global
;
; Disable receiving messages in raw mode.
;
; @clobbers: r16

UART_HW_Uart1_DisableRawRecv:
  lds r16, UCSR1B
  cbr r16, (1<<RXCIE1)                      ; disable RX complete interrupt
  cbr r16, (1<<RXEN1)                       ; disable receive
  sts UCSR1B, r16
  ret
; @end



; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_RawRecvPacket
; Receive packet.
;
; @param  R16   COM address to listen to
; @param  R17   maximum value for accepted msg data (i.e. buffersize minus 3)
; @param  R18   max number of secs to wait for incoming message
; @param  X     buffer to receive to
; @return CFLAG set if okay (packet received), cleared on error
; @return R16   error code if CFLAG is cleared (COM2_ERROR_NOTFORME, COM2_ERROR_IOERROR, COM2_ERROR_DATAERROR)
; @clobbers: r16, r17, r18, r19, r22, X

UART_HW_Uart1_RawRecvPacket:
  ; wait for data
  push r16
    mov r16, r18
    rcall uartHwUart1RawWaitForByte            ; (r16, r18, r22)
  pop r16
  brcc UART_HW_Uart1_RawRecvPacket_error

  ; data available, start reading
  mov r19, r17                                 ; max msg payload size
  push r16
    ; read destination address
    rcall uartHwUart1RawRecvByte               ; (R16, R18, R22)
  pop r17                                      ; pop acceptable COM address from R16 to R17
  brcc UART_HW_Uart1_RawRecvPacket_error
#ifndef COM_ACCEPT_ALL_DEST                    ; accept every destination address
  ; compare destination address (accept "FF" and own address)
  cp r16, r17
  breq UART_HW_Uart1_RawRecvPacket_acceptAddr
  cpi r16, 0xff
  breq UART_HW_Uart1_RawRecvPacket_acceptAddr
  ldi r16, COM2_ERROR_NOTFORME
  rjmp UART_HW_Uart1_RawRecvPacket_error
#endif
UART_HW_Uart1_RawRecvPacket_acceptAddr:
  st X+, r16
  ; read msg length
  rcall uartHwUart1RawRecvByte                 ; (R16, R18, R22)
  brcc UART_HW_Uart1_RawRecvPacket_error
  cp r16, r19                                  ; (COM2_BUFFER_SIZE-3)
  brcc UART_HW_Uart1_RawRecvPacket_error
  tst r16
  breq UART_HW_Uart1_RawRecvPacket_error
  st X+, r16
  inc r16
  mov r17, r16
  ; read message content
UART_HW_Uart1_RawRecvPacket_loop:
    rcall uartHwUart1RawRecvByte               ; (R16, R18, R22)
    brcc UART_HW_Uart1_RawRecvPacket_error
    st X+, r16
    dec r17
  brne UART_HW_Uart1_RawRecvPacket_loop
  sec
  rjmp UART_HW_Uart1_RawRecvPacket_end
UART_HW_Uart1_RawRecvPacket_error:
  clc
UART_HW_Uart1_RawRecvPacket_end:
  ret
; @end



; ---------------------------------------------------------------------------
; @routine uartHwUart1RawRecvByte
; Receive one byte.
;
; @return CFLAG set if okay, cleared on error
; @return R16 error code if CFLAG is cleared
; @clobbers: r16 (r18, r22)

uartHwUart1RawRecvByte:
  rcall uartHwUart1RawWaitForByte1ms          ; (r18, r22)
  brcc uartHwUart1RawRecvByte_error
  lds r16, UCSR1A                              ; check for errors
  andi r16, (1<<FE1) | (1<<DOR1) | (1<<UPE1)
  brne uartHwUart1RawRecvByte_error
  lds r16, UDR1
  sec
  ret
uartHwUart1RawRecvByte_error:
  ldi r16, COM2_ERROR_IOERROR
  clc
  ret
; @end



; ---------------------------------------------------------------------------
; @routine uartHwUart1RawWaitForByte
; wait for up to given number of secs for incoming byte
;
; @return CFLAG set if okay, cleared on error
; @param  r16   number of secs to wait
; @clobbers: r16, r18, r22

uartHwUart1RawWaitForByte:
uartHwUart1RawWaitForByte_loop:
    rcall uartHwUart1RawWaitForByte1s         ; (r18, r22)
    brcs uartHwUart1RawWaitForByte_haveByte
    dec r16
  brne uartHwUart1RawWaitForByte_loop
  clc
uartHwUart1RawWaitForByte_haveByte:
  ret
; @end



; ---------------------------------------------------------------------------
; @routine uartHwUart1RawWaitForByte1s
; wait for up to 1s for incoming byte
;
; @return CFLAG set if okay, cleared on error
; @clobbers: r18, r22

uartHwUart1RawWaitForByte1s:
  ldi r18, 10
uartHwUart1RawWaitForByte1s_loop:
    push r18
      rcall uartHwUart1RawWaitForByte100ms     ; (r18, r22)
    pop r18
    brcs uartHwUart1RawWaitForByte1s_haveByte
;    sbi LED_SIMPLE_PORTIN, LED_SIMPLE_PINNUM ; toggle
    dec r18
  brne uartHwUart1RawWaitForByte1s_loop
  clc
uartHwUart1RawWaitForByte1s_haveByte:
  ret
; @end



; ---------------------------------------------------------------------------
; @routine uartHwUart1RawWaitForByte100ms
; wait for up to 100ms for incoming byte
;
; @return CFLAG set if okay, cleared on error
; @clobbers: r18, r22

uartHwUart1RawWaitForByte100ms:
  ldi r18, 100
uartHwUart1RawWaitForByte100ms_loop:
    push r18
      rcall uartHwUart1RawWaitForByte1ms
    pop r18
    brcs uartHwUart1RawWaitForByte100ms_haveByte
    dec r18
  brne uartHwUart1RawWaitForByte100ms_loop
  clc
uartHwUart1RawWaitForByte100ms_haveByte:
  ret
; @end



; ---------------------------------------------------------------------------
; @routine uartHwUart1RawWaitForByte1ms
; wait for up to 1ms for incoming byte
;
; @return CFLAG set if okay, cleared on error
; @clobbers: r18, r22

uartHwUart1RawWaitForByte1ms:
  ldi r18, 100
uartHwUart1RawWaitForByte1ms_loop:
    lds r22, UCSR1A
    sbrc r22, RXC1
      rjmp uartHwUart1RawWaitForByte1ms_haveByte
    rcall Utils_WaitFor10MicroSecs                ; wait for 10us (R22)
    dec r18
  brne uartHwUart1RawWaitForByte1ms_loop
  clc
  ret
uartHwUart1RawWaitForByte1ms_haveByte:
  sec
  ret
; @end



.equ COMIO_RawSendPacket  = UART_HW_Uart1_RawSendPacket
.equ COMIO_RawRecvPacket  = UART_HW_Uart1_RawRecvPacket
.equ COMIO_EnableRawRecv  = UART_HW_Uart1_EnableRawRecv
.equ COMIO_DisableRawRecv = UART_HW_Uart1_DisableRawRecv