; *************************************************************************** ; copyright : (C) 2023 by Martin Preuss ; email : martin@libchipcard.de ; ; *************************************************************************** ; * This file is part of the project "AqHome". * ; * Please see toplevel file COPYING of that project for license details. * ; *************************************************************************** ; doesn't work, yet ; *************************************************************************** ; data .dseg .equ CNY70_FLAGS_ADC_STARTED = 0x01 .equ CNY70_FLAGS_ADC_FINISHED = 0x02 .equ CNY70_FLAGS_ADC_VALID = 0x04 .equ CNY70_TIMER_100MS = 20 ; every 2s cny70DataBegin: cny70Flags: .byte 1 cny70LastData: .byte 1 cny70TimerCounter: .byte 1 cny70DataEnd: ; *************************************************************************** ; code .cseg ; --------------------------------------------------------------------------- ; Init module. ; ; IN: ; - nothing ; OUT: ; - CFLAG: set if okay, clear on error ; USED: CNY70_Init: ; preset SRAM data area ldi xh, HIGH(cny70DataBegin) ldi xl, LOW(cny70DataBegin) clr r16 ldi r17, (cny70DataEnd-cny70DataBegin) rcall Utils_FillSram ; setup pins and interrupts sbi CNY70_DDR_LED, CNY70_PINNUM_LED ; set DATA port as output cbi CNY70_PORT_LED, CNY70_PINNUM_LED ; LED off cbi CNY70_PORT_ADC, CNY70_PINNUM_ADC ; disable internal pullup for ADC cbi CNY70_DDR_ADC, CNY70_PINNUM_ADC ; set ADC port as input ldi r16, (1<