; ***************************************************************************
; copyright   : (C) 2025 by Martin Preuss
; email       : martin@libchipcard.de
;
; ***************************************************************************
; * This file is part of the project "AqHome".                              *
; * Please see toplevel file COPYING of that project for license details.   *
; ***************************************************************************

; Hardware routine  for AtTiny 84 devices


.cseg


; ---------------------------------------------------------------------------
; @routine systemInitHardware
;

systemInitHardware:
  ; set all ports as inputs and enable internal pull-up resistors
;  ldi r16, 0xff
  clr r17

  outr DDRA, r17  ; all input
  outr PUEA, r17  ; disable pull-up on all

  outr DDRB, r17  ; all input
  outr PUEB, r17  ; disable pull-up on all

  ret
; @end



; ---------------------------------------------------------------------------
; @routine systemSetSpeed
;

systemSetSpeed:
.if clock == 1000000
  ldi r17, 0xd8
  ldi r16, (1<<CLKPS1) | (1<<CLKPS0) ; SUT=0, CLKPS=0011b
  sts CCP, r17
  sts CLKPR, r16
.endif

.if clock == 8000000
  ldi r17, 0xd8
  clr r16           ; SUT=0, CLKPS=0
  sts CCP, r17
  sts CLKPR, r16

#if 0
  ; read and set calibration data
  push r15
    inr r15, SREG
    cli
    ldi zl, 0
    ldi zh, 1
    ldi r16, (1<<RSIG) | (1<<SPMEN)
    outr SPMCSR, r16
    lpm r17, Z
    outr OSCCAL0, r17
    outr SREG, r15
  pop r15
#endif

.endif

  ret
; @end



; ---------------------------------------------------------------------------
; @routine systemSleep
;

systemSleep:
  ; only modify SE, SM1 and SM0
  cli
  in r16, MCUCR
  ldi r17, (1<<SE) | (1<<SM1) | (1<<SM0)
  neg r17
  and r16, r17
  ori r16, (1<<SE)           ; sleep mode "idle", enable
  out MCUCR, r16
  sei                        ; make sure interrupts really are enabled
  sleep                      ; sleep, wait for interrupt
  ret
; @end



; ---------------------------------------------------------------------------
; @routine systemSetupTimer0
;

systemSetupTimer0:                            ; setup timer for IRQ every 100ms
  ldi r16, (1<<CS02) | (0<<CS01) | (1<<CS00)  ; Prescaler 1024
  out TCCR0B, r16
  
  ldi r16, (1<<WGM01) | (0<<WGM00)             ; CTC mode
  out TCCR0A, r16

; Settings for clock 1Mhz (default)
; use timer0 with OCR0A=98-1 (irq every 97.65625 millisecs), baseTimerModuleReloadValue 1
;
.if clock == 1000000
  ; CMP-A interrupt about every 100ms
  ldi r16, 98-1      ; (1,000,000/1024)/10 = 97.65625
  out OCR0A, r16

  ldi r16, 1
  sts baseTimerModuleReloadValue, r16
  sts baseTimerModuleTickCounter, r16
.endif

;
; Settings for clock 8Mhz
; use timer0 with OCR0A=78 (irq every 9.984 millisecs), baseTimerModuleReloadValue 10
;
.if clock == 8000000
  ; CMP-A interrupt about every 10ms
  ldi r16, 78-1
  out OCR0A, r16

  ldi r16, 10
  sts baseTimerModuleReloadValue, r16
  sts baseTimerModuleTickCounter, r16
.endif


  ldi r16, (1<<OCF0A)             ; clear pending interrupts
.ifdef TIFR0
  outr TIFR0, r16
.else
  outr TIFR, r16
.endif
  
  ldi r16, (1<<OCIE0A)            ; Timer/Counter0 Output Compare Match A Interrupt Enable
.ifdef TIMSK0
  outr TIMSK0, r16
.else
  outr TIMSK, r16
.endif
  sec
  ret
; @end