; ***************************************************************************
; copyright   : (C) 2025 by Martin Preuss
; email       : martin@libchipcard.de
;
; ***************************************************************************
; * This file is part of the project "AqHome".                              *
; * Please see toplevel file COPYING of that project for license details.   *
; ***************************************************************************



; ---------------------------------------------------------------------------
; @macro M_UART_HW_Uart_Init
;
; @param %0 UART number ("0" for UART0)
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
; @clobbers R16, R17, X

.macro M_UART_HW_Uart_Init
  rcall UART_HW_InterfaceInit

  ; set baudrate
.if clock == 8000000
  ldi r16, 25 ; (19.2Kb/s at 8MHz)
  ldi r17, 0
.endif

.if clock == 1000000
  ldi r16, 2  ; (19.2Kb/s at 1MHz)
  ldi r17, 0  
.endif

  sts UBRR@0H, r17
  sts UBRR@0L, r16

  ; set character format 
  ldi r16, (1<<USBS@0)|(3<<UCSZ@00)
  sts UCSR@0C, r16
.endmacro
; @end



; ---------------------------------------------------------------------------
; @macro M_UART_HW_Uart_StartRx
;
; @param %0 UART number ("0" for UART0)
; @clobbers none

.macro M_UART_HW_Uart_StartRx
  lds r16, UCSR@0B
  sbr r16, (1<<RXCIE@0) | (1<<RXEN@0)  ; enable RX complete interrupt, enable receive
  sts UCSR@0B, r16
.endmacro
; @end



; ---------------------------------------------------------------------------
; @macro M_UART_HW_Uart_StopRx
;
; @param %0 UART number ("0" for UART0)
; @clobbers R16

.macro M_UART_HW_Uart_StopRx
  lds r16, UCSR@0B
  cbr r16, (1<<RXCIE@0 | (1<<RXEN@0))   ; disable RX complete interrupt, disable receive
  sts UCSR@0B, r16
.endmacro
; @end



; ---------------------------------------------------------------------------
; @macro M_UART_HW_Uart_StartTx
;
; @param %0 UART number ("0" for UART0)
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
; @clobbers R16

.macro M_UART_HW_Uart_StartTx
  lds r16, UCSR@0A
  cbr r16, (1<<TXC@0)                               ; clear TXCn interrupt
  sts UCSR@0A, r16
  lds r16, UCSR@0B
  sbr r16, (1<<UDRIE@0) | (1<<TXC@0) | (1<<TXEN@0)  ; enable TX UDRE and TXC1 interrupt, enable transceive
  sts UCSR@0B, r16
.endmacro
; @end



; ---------------------------------------------------------------------------
; @macro M_UART_HW_Uart_StopTx
;
; @param %0 UART number ("0" for UART0)
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
; @clobbers R16

.macro M_UART_HW_Uart_StopTx
  lds r16, UCSR@0B
  cbr r16, (1<<UDRIE@0) | (1<<TXC@0) | (1<<TXEN@0)  ; disable TX UDRE and TXC1 interrupt, enable transceive
  sts UCSR@0B, r16
.endmacro
; @end



; ---------------------------------------------------------------------------
; @macro M_UART_HW_Uart_Flush
;
; Flush receiption buffer.
;
; @param %0 UART number ("0" for UART0)
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
; @clobbers R16

.macro M_UART_HW_Uart_Flush
l_loop_%:
    lds r16, UCSR@0A
    sbrs r16, RXC@0
      rjmp l_end_%
    lds r16, UDR@0
    clr r16
    std Y+UART_HW_IFACE_OFFS_READTIMER, r16
  rjmp l_loop_%
l_end_%:
.endmacro
; @end



; ---------------------------------------------------------------------------
; @macro M_UART_HW_Uart_RxCharIsr
;
; @param %0 UART number ("0" for UART0)
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
; @clobbers R16 (R17, R18, X)

.macro M_UART_HW_Uart_RxCharIsr
#if 0
  lds r16, UCSR@0A                              ; check for errors
  andi r16, (1<<FE@0) | (1<<DOR@0) | (1<<UPE@0)
  breq l_recv_%                                 ; no error, receive next char
  ldd r16, Y+UART_HW_IFACE_OFFS_STATUS          ; set error status
  ori r16, (1<<UART_HW_STATUS_HWERR_BIT)        ; -> HWERR
  rjmp l_setStatusAndEnd_%
l_recv_%:
  lds r16, UCSR@0A
  sbrs r16, RXC@0
    rjmp l_end_%                                ; no data
  lds r16, UDR@0
  rcall UART_HW_InterfaceWriteToReadBuffer      ; (R17, R18, X)
  brcc l_overrun_%
  clr r16
  std Y+UART_HW_IFACE_OFFS_READTIMER, r16       ; reset read timer
  rjmp l_end_%
l_overrun_%:
  ldd r16, Y+UART_HW_IFACE_OFFS_STATUS          ; set overrun error
  ori r16, (1<<UART_HW_STATUS_OVERRUN_BIT)      ; -> OVERRUN
l_setStatusAndEnd_%:
  std Y+UART_HW_IFACE_OFFS_STATUS, r16
l_end_%:
#endif
.endmacro
; @end



; ---------------------------------------------------------------------------
; @macro M_UART_HW_Uart_TxUdreIsr
;
; Handler for UDREn interrupt called when TX data register is empty.
;
; @param %0 UART number ("0" for UART0)
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
; @clobbers R16, R17, X

.macro M_UART_HW_Uart_TxUdreIsr
  lds r16, UCSR@0A
  sbrs r16,UDRE@0
    rjmp l_disable_irq_%                       ; not ready

  ; check write mode
  ldd r16, Y+UART_HW_IFACE_OFFS_WRITEMODE
  cpi r16, UART_HW_WRITEMODE_WRITING
  brne l_disable_irq_%                         ; not in writing mode

  ; check whether we have an active write buffer
  ldd r16, Y+UART_HW_IFACE_OFFS_WRITEBUFNUM
  cpi r16, 0xff
  breq l_disable_irq_%                         ; no buffer

  ; check whether there is data in the buffer to send
  ldd r17, Y+UART_HW_IFACE_OFFS_WRITEBUFLEFT   ; r17=bytes left
  tst r17
  breq l_disable_irq_%                         ; nothing left to write
  
  ; get read ptr, read byte, inc read ptr, store ptr and bytesLeft
  ldd xl, Y+UART_HW_IFACE_OFFS_WRITEBUFPOSLOW
  ldd xh, Y+UART_HW_IFACE_OFFS_WRITEBUFPOSHIGH
  ld r16, X+                                   ; r16=byte to write
  std Y+UART_HW_IFACE_OFFS_WRITEBUFPOSLOW, xl
  std Y+UART_HW_IFACE_OFFS_WRITEBUFPOSHIGH, xh
  dec r17
  std Y+UART_HW_IFACE_OFFS_WRITEBUFLEFT, r17
  
  ; send byte, reset write timer
  sts UDR@0, r16
  clr r16
  std Y+UART_HW_IFACE_OFFS_WRITETIMER, r16     ; reset write timer
  
  ; still bytes left to write?
  tst r17
  brne l_end_%
  ldi r16, UART_HW_WRITEMODE_WAITBUFFEREMPTY
  std Y+UART_HW_IFACE_OFFS_WRITEMODE, r16      ; change mode to WAITBUFFEREMPTY

l_disable_irq_%:
  ; disable further DRE1 interrupts
  lds r16, UCSR@0B
  cbr r16, (1<<UDRIE@0)                        ; disable TX data register empty interrupt
  sts UCSR@0B, r16
l_end_%:
.endmacro
; @end



; ---------------------------------------------------------------------------
; @macro M_UART_HW_Uart_TxCharIsr
;
; Handler for TXCn interrupt called when a last byte has been completely sent and
; the data register is empty.
;
; @param %0 UART number ("0" for UART0)
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
; @clobbers R16

.macro M_UART_HW_Uart_TxCharIsr
  ; check write mode
  ldd r16, Y+UART_HW_IFACE_OFFS_WRITEMODE
  cpi r16, UART_HW_WRITEMODE_WAITBUFFEREMPTY
  brne l_end_%

  ; disable further TXC1 interrupts
  lds r16, UCSR@0B
  cbr r16, (1<<TXC@0)                          ; disable TXC1 interrupt
  sts UCSR@0B, r16

  ; change write mode to WRITEBUFFEREMPTY
  ldi r16, UART_HW_WRITEMODE_WRITEBUFFEREMPTY
  std Y+UART_HW_IFACE_OFFS_WRITEMODE, r16
l_end_%:
.endmacro
; @end